stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

116 files changed, 19019 insertions, 20882 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index 002e59ef5..3a2e9a680 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.907083                       # Nu
 sim_ticks                                1907083088000                       # Number of ticks simulated
 final_tick                               1907083088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20030                       # Simulator instruction rate (inst/s)
-host_op_rate                                    20030                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              680419212                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  20979                       # Simulator instruction rate (inst/s)
+host_op_rate                                    20979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              712669715                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 389460                       # Number of bytes of host memory used
-host_seconds                                  2802.81                       # Real time elapsed on the host
+host_seconds                                  2675.97                       # Real time elapsed on the host
 sim_insts                                    56139550                       # Number of instructions simulated
 sim_ops                                      56139550                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -563,8 +563,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       837991                       # number of writebacks
 system.cpu.dcache.writebacks::total            837991                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       126783                       # number of ReadReq MSHR hits
@@ -605,10 +603,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61084599500
 system.cpu.dcache.overall_mshr_miss_latency::total  61084599500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1528608000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1528608000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2161966000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2161966000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3690574000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3690574000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1528608000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1528608000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118453                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118453                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049434                       # mshr miss rate for WriteReq accesses
@@ -631,11 +627,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements           1471396                       # number of replacements
 system.cpu.icache.tags.tagsinuse           508.107952                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            19138982                       # Total number of references to valid blocks.
@@ -694,8 +687,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1471396                       # number of writebacks
 system.cpu.icache.writebacks::total           1471396                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1472080                       # number of ReadReq MSHR misses
@@ -722,7 +713,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974
 system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           339491                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65257.604073                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            5020229                       # Total number of references to valid blocks.
@@ -843,8 +833,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        76584                       # number of writebacks
 system.cpu.l2cache.writebacks::total            76584                       # number of writebacks
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           15                       # number of UpgradeReq MSHR misses
@@ -883,10 +871,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44631457500
 system.cpu.l2cache.overall_mshr_miss_latency::total  46615488000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1441963500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1441963500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2051300500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2051300500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3493264000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3493264000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1441963500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1441963500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.750000                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.750000                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383353                       # mshr miss rate for ReadExReq accesses
@@ -917,11 +903,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      5733180                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2866165                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1963                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1053,26 +1036,26 @@ system.iocache.ReadReq_misses::tsunami.ide          173                       #
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21917383                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21917383                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245324283                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   5245324283                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21917383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21917383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21917383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21917383                       # number of overall miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5267241666                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5267241666                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5267241666                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5267241666                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1085,36 +1068,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145
 system.iocache.ReadReq_avg_miss_latency::total 126690.075145                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126690.075145                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126690.075145                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126237.068089                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126237.068089                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs            83                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs    13.833333                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13267383                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13267383                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165924983                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3165924983                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13267383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13267383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13267383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13267383                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3179192366                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3179192366                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3179192366                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3179192366                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1127,11 +1108,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145
 system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76690.075145                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76690.075145                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76193.945261                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76193.945261                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
 system.membus.trans_dist::ReadResp             295608                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9623                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 1db8d7737..4b8dc4618 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.929078                       # Nu
 sim_ticks                                1929077876500                       # Number of ticks simulated
 final_tick                               1929077876500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 158135                       # Simulator instruction rate (inst/s)
-host_op_rate                                   158134                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5371969736                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 169237                       # Simulator instruction rate (inst/s)
+host_op_rate                                   169237                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5749129790                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 339544                       # Number of bytes of host memory used
-host_seconds                                   359.10                       # Real time elapsed on the host
+host_seconds                                   335.54                       # Real time elapsed on the host
 sim_insts                                    56786201                       # Number of instructions simulated
 sim_ops                                      56786201                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -746,8 +746,6 @@ system.cpu0.dcache.blocked::no_mshrs           111036                       # nu
 system.cpu0.dcache.blocked::no_targets            116                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs    60.537276                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets   152.336207                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       741086                       # number of writebacks
 system.cpu0.dcache.writebacks::total           741086                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       559859                       # number of ReadReq MSHR hits
@@ -792,10 +790,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  60954715557
 system.cpu0.dcache.overall_mshr_miss_latency::total  60954715557                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1558946000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1558946000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2296787000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2296787000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3855733000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3855733000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1558946000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1558946000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.118415                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.118415                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048081                       # mshr miss rate for WriteReq accesses
@@ -822,11 +818,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements           911237                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          508.249711                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs            7675800                       # Total number of references to valid blocks.
@@ -884,8 +877,6 @@ system.cpu0.icache.blocked::no_mshrs              347                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs    32.965418                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks       911237                       # number of writebacks
 system.cpu0.icache.writebacks::total           911237                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54272                       # number of ReadReq MSHR hits
@@ -918,7 +909,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258
 system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.branchPred.lookups                4129053                       # Number of BP lookups
 system.cpu1.branchPred.condPredicted          3551647                       # Number of conditional branches predicted
 system.cpu1.branchPred.condIncorrect           103168                       # Number of conditional branches incorrect
@@ -1352,8 +1342,6 @@ system.cpu1.dcache.blocked::no_mshrs            22564                       # nu
 system.cpu1.dcache.blocked::no_targets             12                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs    33.664820                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets   131.916667                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks        79554                       # number of writebacks
 system.cpu1.dcache.writebacks::total            79554                       # number of writebacks
 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       136401                       # number of ReadReq MSHR hits
@@ -1398,10 +1386,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3154256462
 system.cpu1.dcache.overall_mshr_miss_latency::total   3154256462                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     32176000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     32176000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    696582500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    696582500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    728758500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    728758500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     32176000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total     32176000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042091                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042091                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036289                       # mshr miss rate for WriteReq accesses
@@ -1428,11 +1414,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827                       # average overall mshr uncacheable latency
 system.cpu1.icache.tags.replacements           244089                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          469.435893                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs            1565201                       # Total number of references to valid blocks.
@@ -1491,8 +1474,6 @@ system.cpu1.icache.blocked::no_mshrs               56                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.875000                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks       244089                       # number of writebacks
 system.cpu1.icache.writebacks::total           244089                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        11093                       # number of ReadReq MSHR hits
@@ -1525,7 +1506,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520
 system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1610,26 +1590,26 @@ system.iocache.ReadReq_misses::tsunami.ide          175                       #
 system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
-system.iocache.overall_misses::total              175                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41727                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
+system.iocache.overall_misses::total            41727                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     22072883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     22072883                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245136282                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   5245136282                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     22072883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     22072883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     22072883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     22072883                       # number of overall miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5267209165                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5267209165                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5267209165                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5267209165                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41727                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1642,36 +1622,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000
 system.iocache.ReadReq_avg_miss_latency::total 126130.760000                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126130.760000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126130.760000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126230.238575                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126230.238575                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41727                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41727                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41727                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41727                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13322883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13322883                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165734984                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3165734984                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13322883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13322883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13322883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13322883                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3179057867                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3179057867                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3179057867                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3179057867                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1684,11 +1662,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000
 system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76130.760000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76130.760000                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76187.069931                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76187.069931                       # average overall mshr miss latency
 system.l2c.tags.replacements                   345263                       # number of replacements
 system.l2c.tags.tagsinuse                65201.794559                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4034348                       # Total number of references to valid blocks.
@@ -1879,8 +1856,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               81472                       # number of writebacks
 system.l2c.writebacks::total                    81472                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
@@ -1956,12 +1931,9 @@ system.l2c.overall_mshr_miss_latency::total  49061475524                       #
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1471043500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     30151000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total   1501194500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2180387500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    660346500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2840734000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3651431000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    690497500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4341928500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1471043500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data     30151000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1501194500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941646                       # mshr miss rate for UpgradeReq accesses
@@ -2017,13 +1989,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 119350.368973
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 85845.208917                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data  9565.672589                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 73994.208399                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq                7193                       # Transaction distribution
 system.membus.trans_dist::ReadResp             297247                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13095                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 6d0ef82f7..d6b9de05c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.876794                       # Nu
 sim_ticks                                1876794488000                       # Number of ticks simulated
 final_tick                               1876794488000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 164316                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164316                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5820514836                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 142986                       # Simulator instruction rate (inst/s)
+host_op_rate                                   142986                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5064945596                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 335448                       # Number of bytes of host memory used
-host_seconds                                   322.44                       # Real time elapsed on the host
+host_seconds                                   370.55                       # Real time elapsed on the host
 sim_insts                                    52982943                       # Number of instructions simulated
 sim_ops                                      52982943                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -734,8 +734,6 @@ system.cpu.dcache.blocked::no_mshrs            133846                       # nu
 system.cpu.dcache.blocked::no_targets              35                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.412332                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   146.257143                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       843569                       # number of writebacks
 system.cpu.dcache.writebacks::total            843569                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       717041                       # number of ReadReq MSHR hits
@@ -780,10 +778,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63069666964
 system.cpu.dcache.overall_mshr_miss_latency::total  63069666964                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1528639000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1528639000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2154562000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2154562000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3683201000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3683201000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1528639000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1528639000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.111881                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.111881                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047061                       # mshr miss rate for WriteReq accesses
@@ -810,11 +806,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements           1074186                       # number of replacements
 system.cpu.icache.tags.tagsinuse           507.868793                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs             8786985                       # Total number of references to valid blocks.
@@ -873,8 +866,6 @@ system.cpu.icache.blocked::no_mshrs               342                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    37.815789                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1074186                       # number of writebacks
 system.cpu.icache.writebacks::total           1074186                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68615                       # number of ReadReq MSHR hits
@@ -907,7 +898,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543
 system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           338591                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65285.567334                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4253578                       # Total number of references to valid blocks.
@@ -1040,8 +1030,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        76108                       # number of writebacks
 system.cpu.l2cache.writebacks::total            76108                       # number of writebacks
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           45                       # number of UpgradeReq MSHR misses
@@ -1084,10 +1072,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46238023002
 system.cpu.l2cache.overall_mshr_miss_latency::total  48112818002                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442000500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442000500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2044145000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2044145000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3486145500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3486145500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1442000500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1442000500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.562500                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.562500                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.083333                       # mshr miss rate for SCUpgradeReq accesses
@@ -1122,11 +1108,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      4961718                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2480443                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2186                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1259,26 +1242,26 @@ system.iocache.ReadReq_misses::tsunami.ide          173                       #
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21828883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21828883                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::tsunami.ide   5246443280                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   5246443280                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21828883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21828883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21828883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21828883                       # number of overall miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5268272163                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5268272163                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5268272163                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5268272163                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1291,36 +1274,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451
 system.iocache.ReadReq_avg_miss_latency::total 126178.514451                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126178.514451                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126178.514451                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126261.765440                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126261.765440                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             7                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13178883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13178883                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3167048471                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3167048471                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13178883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13178883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13178883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13178883                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3180227354                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3180227354                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3180227354                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3180227354                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1333,11 +1314,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451
 system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76178.514451                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76178.514451                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76218.750246                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76218.750246                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
 system.membus.trans_dist::ReadResp             296606                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9599                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 864d8545a..555ee4194 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.843617                       # Nu
 sim_ticks                                1843616607000                       # Number of ticks simulated
 final_tick                               1843616607000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 222443                       # Simulator instruction rate (inst/s)
-host_op_rate                                   222443                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5619525357                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 248643                       # Simulator instruction rate (inst/s)
+host_op_rate                                   248643                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6281412703                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 335188                       # Number of bytes of host memory used
-host_seconds                                   328.07                       # Real time elapsed on the host
+host_seconds                                   293.50                       # Real time elapsed on the host
 sim_insts                                    72977545                       # Number of instructions simulated
 sim_ops                                      72977545                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -644,8 +644,6 @@ system.cpu0.dcache.blocked::no_mshrs            58664                       # nu
 system.cpu0.dcache.blocked::no_targets             11                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs    28.111823                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets   183.363636                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       836302                       # number of writebacks
 system.cpu0.dcache.writebacks::total           836302                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       286455                       # number of ReadReq MSHR hits
@@ -704,12 +702,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total  13534205301
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    296833500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    314974000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    611807500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    374975500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    441435000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    816410500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    671809000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    756409000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1428218000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    296833500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    314974000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total    611807500                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.077888                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.078352                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037572                       # mshr miss rate for ReadReq accesses
@@ -747,13 +742,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28101.652148
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220530.089153                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225626.074499                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223124.544128                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230187.538367                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223964.992390                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226780.694444                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225818.151261                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224653.697654                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225199.936928                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 99775.966387                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 93547.371547                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96469.173762                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements           969392                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.185439                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs           43108744                       # Total number of references to valid blocks.
@@ -846,8 +837,6 @@ system.cpu0.icache.blocked::no_mshrs              386                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.572539                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks       969392                       # number of writebacks
 system.cpu0.icache.writebacks::total           969392                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        21576                       # number of ReadReq MSHR hits
@@ -892,7 +881,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 13877.737624
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14186.253536                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13756.958453                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::total 13877.737624                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
@@ -1418,26 +1406,26 @@ system.iocache.ReadReq_misses::tsunami.ide          173                       #
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide      9857962                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total      9857962                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::tsunami.ide   1957317692                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   1957317692                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide      9857962                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total      9857962                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide      9857962                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total      9857962                       # number of overall miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   1967175654                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1967175654                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   1967175654                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1967175654                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1450,53 +1438,50 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56982.439306
 system.iocache.ReadReq_avg_miss_latency::total 56982.439306                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 47105.258279                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 47105.258279                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 56982.439306                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 56982.439306                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 56982.439306                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 56982.439306                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 47146.211001                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 47146.211001                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 47146.211001                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 47146.211001                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide           68                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total           68                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        15504                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        15504                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide           68                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total           68                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide           68                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total           68                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        15572                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        15572                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        15572                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        15572                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6457962                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total      6457962                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1181451904                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   1181451904                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide      6457962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total      6457962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide      6457962                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total      6457962                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   1187909866                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1187909866                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   1187909866                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1187909866                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.393064                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.393064                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.373123                       # mshr miss rate for WriteLineReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::total     0.373123                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.393064                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.393064                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.393064                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.393064                       # mshr miss rate for overall accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.373206                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.373206                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.373206                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.373206                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 94970.029412                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 94970.029412                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76203.038184                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76203.038184                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 94970.029412                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 94970.029412                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 94970.029412                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 94970.029412                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76284.990110                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76284.990110                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76284.990110                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76284.990110                       # average overall mshr miss latency
 system.l2c.tags.replacements                   337717                       # number of replacements
 system.l2c.tags.tagsinuse                65421.749224                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4019101                       # Total number of references to valid blocks.
@@ -1716,8 +1701,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               75320                       # number of writebacks
 system.l2c.writebacks::total                    75320                       # number of writebacks
 system.l2c.UpgradeReq_mshr_misses::cpu2.data           15                       # number of UpgradeReq MSHR misses
@@ -1778,12 +1761,9 @@ system.l2c.overall_mshr_miss_latency::total   8481752004                       #
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    280001500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    297523000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total    577524500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    356232500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    418765500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total    774998000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    636234000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data    716288500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1352522500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    280001500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    297523000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total    577524500                       # number of overall MSHR uncacheable cycles
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.681818                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.136364                       # mshr miss rate for SCUpgradeReq accesses
@@ -1833,13 +1813,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 121109.061370
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208024.888559                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 213125.358166                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210621.626550                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218681.706568                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212463.470320                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215277.222222                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213860.168067                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212737.897238                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 213264.348786                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94118.151261                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88364.419364                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 91063.465784                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq                7144                       # Transaction distribution
 system.membus.trans_dist::ReadResp             295030                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9812                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index 8f982bce7..9d2732791 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.848878                       # Nu
 sim_ticks                                2848878048000                       # Number of ticks simulated
 final_tick                               2848878048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 194660                       # Simulator instruction rate (inst/s)
-host_op_rate                                   235713                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4372273286                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 620428                       # Number of bytes of host memory used
-host_seconds                                   651.58                       # Real time elapsed on the host
+host_inst_rate                                 186843                       # Simulator instruction rate (inst/s)
+host_op_rate                                   226247                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4196685224                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 620168                       # Number of bytes of host memory used
+host_seconds                                   678.84                       # Real time elapsed on the host
 sim_insts                                   126836472                       # Number of instructions simulated
 sim_ops                                     153585571                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -694,8 +694,6 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       757698                       # number of writebacks
 system.cpu0.dcache.writebacks::total           757698                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        75572                       # number of ReadReq MSHR hits
@@ -746,10 +744,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14125657000
 system.cpu0.dcache.overall_mshr_miss_latency::total  14125657000                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6702357000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6702357000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5444959500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5444959500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12147316500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12147316500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6702357000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6702357000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017541                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017541                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018822                       # mshr miss rate for WriteReq accesses
@@ -782,11 +778,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements          2042425                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.725794                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs           69271608                       # Total number of references to valid blocks.
@@ -845,8 +838,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      2042425                       # number of writebacks
 system.cpu0.icache.writebacks::total          2042425                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2042958                       # number of ReadReq MSHR misses
@@ -885,7 +876,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued      1927381                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified      1927559                       # number of prefetch candidates identified
 system.cpu0.l2cache.prefetcher.pfBufferHit          155                       # number of redundant prefetches already in prefetch queue
@@ -1080,8 +1070,6 @@ system.cpu0.l2cache.blocked::no_mshrs               1                       # nu
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu0.l2cache.unused_prefetches           10897                       # number of HardPF blocks evicted w/o reference
 system.cpu0.l2cache.writebacks::writebacks       237171                       # number of writebacks
 system.cpu0.l2cache.writebacks::total          237171                       # number of writebacks
@@ -1162,11 +1150,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total  30542659429
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6445890500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6971910500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5229022000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5229022000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11674912500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12200932500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6445890500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6971910500                       # number of overall MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008562                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.016410                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009054                       # mshr miss rate for ReadReq accesses
@@ -1224,12 +1210,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714                       # average overall mshr uncacheable latency
 system.cpu0.toL2Bus.snoop_filter.tot_requests      5755490                       # Total number of requests made to the snoop filter.
 system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2900081                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        44333                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1622,8 +1605,6 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       155125                       # number of writebacks
 system.cpu1.dcache.writebacks::total           155125                       # number of writebacks
 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12753                       # number of ReadReq MSHR hits
@@ -1674,10 +1655,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5005376500
 system.cpu1.dcache.overall_mshr_miss_latency::total   5005376500                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    389467000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    389467000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    251809500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    251809500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    641276500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    641276500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    389467000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    389467000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035506                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035506                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027923                       # mshr miss rate for WriteReq accesses
@@ -1710,11 +1689,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871                       # average overall mshr uncacheable latency
 system.cpu1.icache.tags.replacements           856657                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          499.135889                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs            6021932                       # Total number of references to valid blocks.
@@ -1773,8 +1749,6 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks       856657                       # number of writebacks
 system.cpu1.icache.writebacks::total           856657                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       857169                       # number of ReadReq MSHR misses
@@ -1813,7 +1787,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857                       # average overall mshr uncacheable latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued       119555                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified       119603                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit           42                       # number of redundant prefetches already in prefetch queue
@@ -2010,8 +1983,6 @@ system.cpu1.l2cache.blocked::no_mshrs               1                       # nu
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           30                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu1.l2cache.unused_prefetches             580                       # number of HardPF blocks evicted w/o reference
 system.cpu1.l2cache.writebacks::writebacks        29115                       # number of writebacks
 system.cpu1.l2cache.writebacks::total           29115                       # number of writebacks
@@ -2094,11 +2065,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total   4332115741
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14575500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    365633500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    380209000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    234344500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    234344500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14575500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    599978000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    614553500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    365633500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    380209000                       # number of overall MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026536                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.080791                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.032323                       # mshr miss rate for ReadReq accesses
@@ -2158,12 +2127,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606                       # average overall mshr uncacheable latency
 system.cpu1.toL2Bus.snoop_filter.tot_requests      2128285                       # Total number of requests made to the snoop filter.
 system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1071677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18282                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -2334,26 +2300,26 @@ system.iocache.ReadReq_misses::realview.ide          243                       #
 system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          243                       # number of overall misses
-system.iocache.overall_misses::total              243                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36467                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36467                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36467                       # number of overall misses
+system.iocache.overall_misses::total            36467                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     31660877                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     31660877                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::realview.ide   4578259357                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   4578259357                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31660877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31660877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31660877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31660877                       # number of overall miss cycles
+system.iocache.demand_miss_latency::realview.ide   4609920234                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4609920234                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4609920234                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4609920234                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36467                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36467                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36467                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36467                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2366,36 +2332,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897
 system.iocache.ReadReq_avg_miss_latency::total 130291.674897                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 130291.674897                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 130291.674897                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 130291.674897                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 130291.674897                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126413.476129                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126413.476129                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126413.476129                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126413.476129                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        36467                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36467                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36467                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36467                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     19510877                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     19510877                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2765398414                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   2765398414                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19510877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19510877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19510877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19510877                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2784909291                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2784909291                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2784909291                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2784909291                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2408,11 +2372,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897
 system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 80291.674897                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 80291.674897                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76367.929662                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76367.929662                       # average overall mshr miss latency
 system.l2c.tags.replacements                   132278                       # number of replacements
 system.l2c.tags.tagsinuse                63284.055151                       # Cycle average of tags in use
 system.l2c.tags.total_refs                     475189                       # Total number of references to valid blocks.
@@ -2707,8 +2670,6 @@ system.l2c.blocked::no_mshrs                        9                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs            45                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              102335                       # number of writebacks
 system.l2c.writebacks::total                   102335                       # number of writebacks
 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
@@ -2818,14 +2779,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5869096507
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12223000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    312114003                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total   6637196510                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4740559503                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    195045002                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4935604505                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10609656010                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5869096507                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12223000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    507159005                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11572801015                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    312114003                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6637196510                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.226284                       # mshr miss rate for UpgradeReq accesses
@@ -2911,15 +2869,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               39041                       # Transaction distribution
 system.membus.trans_dist::ReadResp             216336                       # Transaction distribution
 system.membus.trans_dist::WriteReq              31035                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index cc9440c8e..3f52f900f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.858505                       # Nu
 sim_ticks                                2858505242500                       # Number of ticks simulated
 final_tick                               2858505242500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 194204                       # Simulator instruction rate (inst/s)
-host_op_rate                                   234807                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4961098243                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 583728                       # Number of bytes of host memory used
-host_seconds                                   576.18                       # Real time elapsed on the host
+host_inst_rate                                 187730                       # Simulator instruction rate (inst/s)
+host_op_rate                                   226980                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4795719535                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 583724                       # Number of bytes of host memory used
+host_seconds                                   596.05                       # Real time elapsed on the host
 sim_insts                                   111897168                       # Number of instructions simulated
 sim_ops                                     135292215                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -651,8 +651,6 @@ system.cpu.dcache.blocked::no_mshrs                23                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.304348                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       699681                       # number of writebacks
 system.cpu.dcache.writebacks::total            699681                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76216                       # number of ReadReq MSHR hits
@@ -701,10 +699,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27438355500
 system.cpu.dcache.overall_mshr_miss_latency::total  27438355500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277881000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277881000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5085127500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5085127500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11363008500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11363008500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6277881000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6277881000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017764                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017764                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015869                       # mshr miss rate for WriteReq accesses
@@ -735,11 +731,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184357.303412                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184357.303412                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193541.389177                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193541.389177                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements           2894371                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.208818                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            54430342                       # Total number of references to valid blocks.
@@ -798,8 +791,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      2894371                       # number of writebacks
 system.cpu.icache.writebacks::total           2894371                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2894895                       # number of ReadReq MSHR misses
@@ -838,7 +829,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            96490                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65016.669962                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            7024998                       # Total number of references to valid blocks.
@@ -1018,8 +1008,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        88112                       # number of writebacks
 system.cpu.l2cache.writebacks::total            88112                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
@@ -1089,11 +1077,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total  19994125000
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    427218000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888707000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6315925000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4767887000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4767887000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    427218000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10656594000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11083812000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5888707000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6315925000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001706                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000208                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001612                       # mshr miss rate for ReadReq accesses
@@ -1143,12 +1129,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      7506242                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      3768367                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58373                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1316,26 +1299,26 @@ system.iocache.ReadReq_misses::realview.ide          234                       #
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          234                       # number of overall misses
-system.iocache.overall_misses::total              234                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
+system.iocache.overall_misses::total            36458                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     29059377                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     29059377                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::realview.ide   4548977125                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   4548977125                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     29059377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     29059377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     29059377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     29059377                       # number of overall miss cycles
+system.iocache.demand_miss_latency::realview.ide   4578036502                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4578036502                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4578036502                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4578036502                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1348,36 +1331,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795
 system.iocache.ReadReq_avg_miss_latency::total 124185.371795                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124185.371795                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124185.371795                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124185.371795                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124185.371795                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125570.149268                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125570.149268                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125570.149268                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125570.149268                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     17359377                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     17359377                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736351620                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   2736351620                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17359377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17359377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17359377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17359377                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2753710997                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2753710997                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2753710997                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2753710997                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1390,11 +1371,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795
 system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74185.371795                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74185.371795                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75531.049344                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75531.049344                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               34891                       # Transaction distribution
 system.membus.trans_dist::ReadResp              72400                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index c05f0ab9f..9ae10924b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.832863                       # Number of seconds simulated
-sim_ticks                                2832863135500                       # Number of ticks simulated
-final_tick                               2832863135500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                2832862976500                       # Number of ticks simulated
+final_tick                               2832862976500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  89708                       # Simulator instruction rate (inst/s)
-host_op_rate                                   108808                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2246897924                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 584736                       # Number of bytes of host memory used
-host_seconds                                  1260.79                       # Real time elapsed on the host
-sim_insts                                   113102806                       # Number of instructions simulated
-sim_ops                                     137183832                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  87854                       # Simulator instruction rate (inst/s)
+host_op_rate                                   106560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2200515158                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 584732                       # Number of bytes of host memory used
+host_seconds                                  1287.36                       # Real time elapsed on the host
+sim_insts                                   113100501                       # Number of instructions simulated
+sim_ops                                     137180951                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1320448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9385192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1320384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9384040                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10708200                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1320448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1320448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8027392                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10706984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1320384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1320384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8026368                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8044916                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8043892                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22879                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22878                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147146                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170083                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125428                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170064                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          125412                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129809                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               129793                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            429                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               466118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3312971                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               466095                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3312564                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3779992                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          466118                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466118                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2833667                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3779563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          466095                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             466095                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2833306                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2839853                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2833667                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2839492                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2833306                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           429                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              466118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3319156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              466095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3318750                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6619845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170084                       # Number of read requests accepted
-system.physmem.writeReqs                       129809                       # Number of write requests accepted
-system.physmem.readBursts                      170084                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129809                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10877056                       # Total number of bytes read from DRAM
+system.physmem.bw_total::total                6619055                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170065                       # Number of read requests accepted
+system.physmem.writeReqs                       129793                       # Number of write requests accepted
+system.physmem.readBursts                      170065                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129793                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10875840                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      8320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8057984                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10708264                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8044916                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   8056896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10707048                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8043892                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                      130                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11273                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10987                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11172                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12956                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11272                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10588                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10986                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11169                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12952                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                9956                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10483                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10745                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10596                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10173                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10481                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10743                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10600                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10174                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              10343                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               9301                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10027                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11029                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10190                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10133                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8501                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7944                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8565                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10025                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11028                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10189                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10128                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8502                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7941                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8563                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                8669                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7612                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7608                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7365                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7701                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8000                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7958                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7699                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7999                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7959                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7673                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               7751                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6981                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7673                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8385                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7672                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8384                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7646                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7477                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832862903500                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832862744500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166532                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166513                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125428                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150650                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16386                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       724                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 125412                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150612                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       728                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -159,118 +159,117 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6620                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6367                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     6633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6951                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7619                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8448                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1259                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                      366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       39                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61981                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      305.496459                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.645422                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.944153                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23140     37.33%     37.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14875     24.00%     61.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6518     10.52%     71.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3622      5.84%     77.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2531      4.08%     81.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1654      2.67%     84.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1506      2.43%     86.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1111      1.79%     88.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7024     11.33%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61981                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6159                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.593765                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      568.835471                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6158     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::35                      262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       58                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61915                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.784899                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.937223                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.895489                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23052     37.23%     37.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14889     24.05%     61.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6490     10.48%     71.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3653      5.90%     77.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2551      4.12%     81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1649      2.66%     84.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1497      2.42%     86.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1106      1.79%     88.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7028     11.35%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61915                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6142                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.666884                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      569.620654                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6141     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6159                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6159                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.442604                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.500292                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.099847                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5468     88.78%     88.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             102      1.66%     90.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.50%     90.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              55      0.89%     91.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              28      0.45%     92.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.32%     92.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              47      0.76%     93.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.19%     93.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             146      2.37%     95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              14      0.23%     96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.08%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              12      0.19%     96.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              62      1.01%     97.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.10%     97.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               7      0.11%     97.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              23      0.37%     98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              90      1.46%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.05%     99.56% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6142                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6142                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.496418                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.503929                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.596363                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5449     88.72%     88.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             115      1.87%     90.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              28      0.46%     91.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              44      0.72%     91.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              34      0.55%     92.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              18      0.29%     92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              53      0.86%     93.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.11%     93.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             141      2.30%     95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              11      0.18%     96.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.13%     96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.13%     96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              63      1.03%     97.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               7      0.11%     97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.13%     97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.41%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              94      1.53%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     99.56% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::96-99               1      0.02%     99.58% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::100-103             1      0.02%     99.59% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::104-107             1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.13%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.05%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             5      0.08%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6159                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2118470000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5305107500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849770000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12464.96                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.11%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             6      0.10%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.08%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6142                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2126742000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5313023250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849675000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12515.03                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31214.96                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31265.03                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
@@ -280,40 +279,40 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139692                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94186                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.19                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9446245.51                       # Average gap between requests
-system.physmem.pageHitRate                      79.05                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  242388720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  132255750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 687663600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                417033360                       # Energy for write commands per rank (pJ)
+system.physmem.avgWrQLen                        23.43                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139707                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94201                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.21                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9447347.56                       # Average gap between requests
+system.physmem.pageHitRate                      79.07                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  242207280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  132156750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 687546600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                416962080                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83434510665                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626525439500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896467659275                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.454308                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705731371250                       # Time in different power states
+system.physmem_0.actBackEnergy            83427429555                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626531651000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896466320945                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.453835                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705741524500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32529373750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32519220500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  226187640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  123415875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 637969800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                398837520                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  225870120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  123242625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 637938600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                398798640                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82104234975                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627692348000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896211361490                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.363834                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2707689162500                       # Time in different power states
+system.physmem_1.actBackEnergy            82153488960                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627649142750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896216849375                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.365771                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2707616089750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30578679500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30651593250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
@@ -333,19 +332,19 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46808005                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23978413                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1175283                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29454237                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13525326                       # Number of BTB hits
+system.cpu.branchPred.lookups                46806016                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23977735                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1175497                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29454915                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13525299                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             45.919798                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11724965                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              34889                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         7914908                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            7768670                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses           146238                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        60204                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             45.918649                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11724113                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              34916                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7913969                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            7767748                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           146221                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        60350                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -376,29 +375,29 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks              9709                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksShort         9709                       # Table walker walks initiated with short descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples         9709                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0         9709    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total         9709                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks              9708                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort         9708                       # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples         9708                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0         9708    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total         9708                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.dtb.walker.walksPending::samples    375751000                       # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::0    375751000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::total    375751000                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K         6239     82.69%     82.69% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::4K         6238     82.69%     82.69% # Table walker page sizes translated
 system.cpu.checker.dtb.walker.walkPageSizes::1M         1306     17.31%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total         7545                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9709                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::total         7544                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9708                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9709                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7545                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9708                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7544                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7545                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total        17254                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7544                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total        17252                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24576844                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8297                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19632942                       # DTB write hits
+system.cpu.checker.dtb.read_hits             24576303                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8296                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19632669                       # DTB write hits
 system.cpu.checker.dtb.write_misses              1412                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
@@ -409,12 +408,12 @@ system.cpu.checker.dtb.align_faults                 0                       # Nu
 system.cpu.checker.dtb.prefetch_faults           1622                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24585141                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19634354                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24584599                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19634081                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44209786                       # DTB hits
-system.cpu.checker.dtb.misses                    9709                       # DTB misses
-system.cpu.checker.dtb.accesses              44219495                       # DTB accesses
+system.cpu.checker.dtb.hits                  44208972                       # DTB hits
+system.cpu.checker.dtb.misses                    9708                       # DTB misses
+system.cpu.checker.dtb.accesses              44218680                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -462,7 +461,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin::total         7995                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            115801229                       # ITB inst hits
+system.cpu.checker.itb.inst_hits            115798779                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4825                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -479,11 +478,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115806054                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115801229                       # DTB hits
+system.cpu.checker.itb.inst_accesses        115803604                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115798779                       # DTB hits
 system.cpu.checker.itb.misses                    4825                       # DTB misses
-system.cpu.checker.itb.accesses             115806054                       # DTB accesses
-system.cpu.checker.numCycles                139034298                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses             115803604                       # DTB accesses
+system.cpu.checker.numCycles                139031272                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -515,79 +514,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     72355                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                72355                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29395                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23194                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19766                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52589                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   463.728156                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2807.068133                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191        51286     97.52%     97.52% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383          905      1.72%     99.24% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575          316      0.60%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     72368                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72368                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29394                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23209                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19765                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52603                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   464.308119                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2802.300904                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191        51295     97.51%     97.51% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383          909      1.73%     99.24% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575          317      0.60%     99.84% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::24576-32767           38      0.07%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959           15      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151           23      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959           17      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151           21      0.04%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52589                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17730                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8394.043940                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17507     98.74%     98.74% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          217      1.22%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::total        52603                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17713                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8411.296807                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17487     98.72%     98.72% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          220      1.24%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17730                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131327621316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.619198                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.492781                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131267451816     99.95%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      41041000      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       8807000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6837500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1021000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       576000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1403500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       474000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::total        17713                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131327462316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.619046                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.492812                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131267362816     99.95%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      40987500      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       8789000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6827500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1022500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       578500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1418000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       467000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17         9500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131327621316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6380     82.61%     82.61% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1343     17.39%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7723                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72355                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131327462316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6375     82.60%     82.60% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1343     17.40%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7718                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72368                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72355                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7723                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72368                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7718                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7723                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        80078                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7718                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80086                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25411177                       # DTB read hits
-system.cpu.dtb.read_misses                      62688                       # DTB read misses
-system.cpu.dtb.write_hits                    19865478                       # DTB write hits
-system.cpu.dtb.write_misses                      9667                       # DTB write misses
+system.cpu.dtb.read_hits                     25410889                       # DTB read hits
+system.cpu.dtb.read_misses                      62740                       # DTB read misses
+system.cpu.dtb.write_hits                    19865162                       # DTB write hits
+system.cpu.dtb.write_misses                      9628                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       361                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.align_faults                       362                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                   2060                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1317                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25473865                       # DTB read accesses
-system.cpu.dtb.write_accesses                19875145                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1318                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25473629                       # DTB read accesses
+system.cpu.dtb.write_accesses                19874790                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45276655                       # DTB hits
-system.cpu.dtb.misses                           72355                       # DTB misses
-system.cpu.dtb.accesses                      45349010                       # DTB accesses
+system.cpu.dtb.hits                          45276051                       # DTB hits
+system.cpu.dtb.misses                           72368                       # DTB misses
+system.cpu.dtb.accesses                      45348419                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -617,58 +616,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     12837                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                12837                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3369                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7745                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore         1723                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11114                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   758.457801                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  3142.171422                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        10521     94.66%     94.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          120      1.08%     95.74% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          234      2.11%     97.85% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383          132      1.19%     99.04% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479           45      0.40%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                     12817                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                12817                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3368                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7731                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore         1718                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11099                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   753.896747                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  3151.109885                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        10511     94.70%     94.70% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191          118      1.06%     95.77% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          237      2.14%     97.90% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383          123      1.11%     99.01% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           46      0.41%     99.42% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671            4      0.04%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::53248-57343            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11114                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         5038                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12015.680826                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9674.005789                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7624.491394                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         4083     81.04%     81.04% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          936     18.58%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11099                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         5044                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12037.073751                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  9689.647863                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7634.465398                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         4079     80.87%     80.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          946     18.75%     99.62% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::32768-49151           16      0.32%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         5038                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23953376916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.632532                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.482296                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      8804085500     36.76%     36.76% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     15147384416     63.24%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2         1819000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total         5044                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  23953217916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.646337                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.478297                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      8473460000     35.38%     35.38% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     15477752916     64.62%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2         1917000      0.01%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::3           88000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23953376916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2980     89.89%     89.89% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           335     10.11%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3315                       # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total  23953217916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2992     89.96%     89.96% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           334     10.04%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3326                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12837                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        12837                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12817                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        12817                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3315                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3315                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        16152                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     65992511                       # ITB inst hits
-system.cpu.itb.inst_misses                      12837                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        16143                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     65995629                       # ITB inst hits
+system.cpu.itb.inst_misses                      12817                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -677,98 +676,98 @@ system.cpu.itb.flush_tlb                          128                       # Nu
 system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3079                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3089                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2160                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2166                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66005348                       # ITB inst accesses
-system.cpu.itb.hits                          65992511                       # DTB hits
-system.cpu.itb.misses                           12837                       # DTB misses
-system.cpu.itb.accesses                      66005348                       # DTB accesses
-system.cpu.numCycles                        278422079                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66008446                       # ITB inst accesses
+system.cpu.itb.hits                          65995629                       # DTB hits
+system.cpu.itb.misses                           12817                       # DTB misses
+system.cpu.itb.accesses                      66008446                       # DTB accesses
+system.cpu.numCycles                        278423951                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104965644                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184047232                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46808005                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33018961                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161470061                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6057656                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     190492                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8321                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        345001                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       554797                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  65991288                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1042618                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6254                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270563337                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.829471                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.217030                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104963925                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184057531                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46806016                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33017160                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161476606                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6057796                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     189442                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8697                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        337421                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       555442                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          188                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  65994399                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1047621                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6260                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270560619                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.829508                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217052                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171642539     63.44%     63.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29152189     10.77%     74.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14033587      5.19%     79.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55735022     20.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171637462     63.44%     63.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29152121     10.77%     74.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14032929      5.19%     79.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55738107     20.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270563337                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168119                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.661037                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77947938                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121878006                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64302075                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3866348                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2568970                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3407378                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total            270560619                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168111                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.661069                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77946486                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121877263                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64301274                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3866559                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2569037                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3407655                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                467954                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              156978056                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3511118                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2568970                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83705242                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11815574                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76555831                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62411209                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33506511                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146428655                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                918489                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                467718                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  65503                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  18531                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30749318                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150222579                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             676982359                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        163959933                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10887                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141740582                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8481991                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2839527                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2643996                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13883864                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26339284                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21214862                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1704584                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2138851                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143220356                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2117775                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143040703                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            261102                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8154295                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14292577                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         121903                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270563337                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.528677                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865235                       # Number of insts issued each cycle
+system.cpu.decode.DecodedInsts              156976144                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3511593                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2569037                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83703987                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11810773                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76556801                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62410429                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33509592                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146427061                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                918712                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                467058                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  65507                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  18530                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30752508                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150221263                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             676972712                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        163957736                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10899                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141737618                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8483639                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2839333                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2643784                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13883095                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26339486                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21214202                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1704469                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2149070                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143218821                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2117732                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143038678                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            260968                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8155598                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14296072                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         121861                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270560619                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528675                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865256                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182376042     67.41%     67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45230245     16.72%     84.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31877858     11.78%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10262059      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              817100      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182379690     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45219626     16.71%     84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31881926     11.78%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10262341      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              817003      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -776,44 +775,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270563337                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270560619                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7341205     32.76%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     32      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5622623     25.09%     57.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9446888     42.15%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7341670     32.77%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5623214     25.10%     57.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9441955     42.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95846012     67.01%     67.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               114315      0.08%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95844496     67.01%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               114325      0.08%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
@@ -837,98 +836,98 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8579      0.01%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8580      0.01%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26129650     18.27%     85.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            20939810     14.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26129578     18.27%     85.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20939362     14.64%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143040703                       # Type of FU issued
-system.cpu.iq.rate                           0.513755                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22410748                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156674                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579280960                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         153497939                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    139990284                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35633                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11369                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165425721                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23393                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323902                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143038678                       # Type of FU issued
+system.cpu.iq.rate                           0.513744                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22406871                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156649                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579270173                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153497654                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    139987851                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35641                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13126                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11370                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165419813                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23399                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323906                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1435157                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          717                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18681                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       624055                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1435915                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          710                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18680                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       623667                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88621                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6303                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88637                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6231                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2568970                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1238473                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                546153                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145518660                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2569037                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1239960                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                546279                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145517187                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26339284                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21214862                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1094251                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17896                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                509714                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18681                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         277446                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471378                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               748824                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142140939                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25734314                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            827514                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26339486                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21214202                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1094236                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17880                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                509843                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18680                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         277456                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471588                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               749044                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142138491                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25734027                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            827925                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        180529                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46562087                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26490837                       # Number of branches executed
-system.cpu.iew.exec_stores                   20827773                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510523                       # Inst execution rate
-system.cpu.iew.wb_sent                      141772110                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140001653                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63237844                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95709593                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502840                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660726                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7370888                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995872                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            715425                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267671554                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.513087                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.118264                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        180634                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46561433                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26490215                       # Number of branches executed
+system.cpu.iew.exec_stores                   20827406                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510511                       # Inst execution rate
+system.cpu.iew.wb_sent                      141769563                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     139999221                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63237138                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95708451                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.502828                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660727                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7372199                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995871                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            715636                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267668720                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.513081                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.118378                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194234773     72.56%     72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43288369     16.17%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15457266      5.77%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4372596      1.63%     96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6412647      2.40%     98.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1623966      0.61%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       797879      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       412108      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1071950      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194241015     72.57%     72.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43280699     16.17%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15455980      5.77%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4372366      1.63%     96.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6407128      2.39%     98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1628567      0.61%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       798347      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412274      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1072344      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267671554                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113257711                       # Number of instructions committed
-system.cpu.commit.committedOps              137338737                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267668720                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113255406                       # Number of instructions committed
+system.cpu.commit.committedOps              137335856                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45494934                       # Number of memory references committed
-system.cpu.commit.loads                      24904127                       # Number of loads committed
+system.cpu.commit.refs                       45494106                       # Number of memory references committed
+system.cpu.commit.loads                      24903571                       # Number of loads committed
 system.cpu.commit.membars                      814876                       # Number of memory barriers committed
-system.cpu.commit.branches                   26024432                       # Number of branches committed
+system.cpu.commit.branches                   26023568                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120166310                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4884393                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120163713                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4884102                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91722407     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91720354     66.79%     66.79% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          112817      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
@@ -957,36 +956,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc         8579      0.01%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24904127     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20590807     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24903571     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20590535     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137338737                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1071950                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389122780                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292297911                       # The number of ROB writes
-system.cpu.timesIdled                          890833                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7858742                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387304193                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113102806                       # Number of Instructions Simulated
-system.cpu.committedOps                     137183832                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.461673                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.461673                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.406228                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.406228                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155527774                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88490356                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9528                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137335856                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1072344                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389119867                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292294903                       # The number of ROB writes
+system.cpu.timesIdled                          890799                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7863332                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387302003                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113100501                       # Number of Instructions Simulated
+system.cpu.committedOps                     137180951                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.461739                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.461739                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.406217                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.406217                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155524958                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88488763                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9529                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502164459                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53130606                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               347857043                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521711                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            838824                       # number of replacements
+system.cpu.cc_regfile_reads                 502156064                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53129749                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               347863698                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521708                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            838747                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.925928                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40057266                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            839336                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.724947                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            40056709                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839259                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.728662                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.925928                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
@@ -996,268 +995,259 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          131
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179127418                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179127418                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23264892                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23264892                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15542105                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15542105                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345700                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345700                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441341                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441341                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         179125101                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179125101                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23264147                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23264147                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15542285                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15542285                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345698                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345698                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441334                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441334                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       460350                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       460350                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38806997                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38806997                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39152697                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39152697                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       704654                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        704654                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3607879                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3607879                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177723                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177723                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27366                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27366                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_hits::cpu.data      38806432                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38806432                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39152130                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39152130                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       705134                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        705134                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3607427                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3607427                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177712                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177712                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        27363                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        27363                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4312533                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4312533                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4490256                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4490256                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11719889500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11719889500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232482188697                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232482188697                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376930500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    376930500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      4312561                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4312561                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4490273                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4490273                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11711380000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11711380000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 232487777697                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 232487777697                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376699000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    376699000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       276000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       276000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244202078197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244202078197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244202078197                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244202078197                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23969546                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23969546                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19149984                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19149984                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523423                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523423                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468707                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468707                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 244199157697                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 244199157697                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 244199157697                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 244199157697                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23969281                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23969281                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19149712                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19149712                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523410                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523410                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468697                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468697                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       460355                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       460355                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43119530                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43119530                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43642953                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43642953                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029398                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029398                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188401                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188401                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339540                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339540                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058386                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058386                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     43118993                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43118993                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43642403                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43642403                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029418                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029418                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188380                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188380                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339527                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339527                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058381                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058381                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102886                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102886                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16632.119452                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16632.119452                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64437.357433                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64437.357433                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13773.679018                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13773.679018                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100015                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100015                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102888                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102888                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16608.729688                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16608.729688                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64446.980548                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.728794                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.728794                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55200                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55200                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56626.135544                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56626.135544                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.889903                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54384.889903                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       869086                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56625.090682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56625.090682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.033598                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54384.033598                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       871366                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6856                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   126.615093                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.095391                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       696811                       # number of writebacks
-system.cpu.dcache.writebacks::total            696811                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       290488                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       290488                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307970                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3307970                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18888                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18888                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3598458                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3598458                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3598458                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3598458                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414166                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414166                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       696773                       # number of writebacks
+system.cpu.dcache.writebacks::total            696773                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       291027                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       291027                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307518                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3307518                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18885                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18885                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3598545                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3598545                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3598545                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3598545                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414107                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414107                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299909                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       299909                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119577                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119577                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119568                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119568                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8478                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total         8478                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       714075                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       714075                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       833652                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       833652                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       714016                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       714016                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       833584                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       833584                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6390908000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6390908000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19966536471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19966536471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1698802000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1698802000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    127413000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    127413000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6386388500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6386388500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19974009472                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19974009472                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1699913000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1699913000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    127031000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    127031000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       271000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       271000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26357444471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26357444471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28056246471                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28056246471                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276240500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276240500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075717451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075717451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11351957951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11351957951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017279                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017279                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26360397972                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26360397972                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28060310972                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28060310972                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276272000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276272000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6276272000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6276272000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017277                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017277                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015661                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015661                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228452                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228452                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228440                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228440                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018088                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018088                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016560                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016560                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019102                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019102                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15430.788621                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15430.788621                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66575.316083                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66575.316083                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14206.762170                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14206.762170                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15028.662420                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.662420                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016559                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016559                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019100                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019100                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15422.073281                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15422.073281                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66600.233644                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66600.233644                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.123311                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.123311                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14983.604624                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14983.604624                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54200                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54200                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36911.311096                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36911.311096                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33654.626236                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33654.626236                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.370073                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.370073                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.807722                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.807722                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193343.290374                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193343.290374                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1886159                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64010374                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1886671                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.927682                       # Average number of references to valid blocks.
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.replacements           1886245                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154077                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64013417                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1886757                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.927749                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       16319051500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154077                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          67874994                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         67874994                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64010374                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64010374                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64010374                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64010374                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64010374                       # number of overall hits
-system.cpu.icache.overall_hits::total        64010374                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1977910                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1977910                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1977910                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1977910                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1977910                       # number of overall misses
-system.cpu.icache.overall_misses::total       1977910                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28157815494                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28157815494                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28157815494                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28157815494                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28157815494                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28157815494                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     65988284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     65988284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     65988284                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     65988284                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     65988284                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     65988284                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029974                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029974                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029974                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029974                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029974                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029974                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.145979                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14236.145979                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14236.145979                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14236.145979                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5784                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          67878198                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         67878198                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64013417                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64013417                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64013417                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64013417                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64013417                       # number of overall hits
+system.cpu.icache.overall_hits::total        64013417                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1977977                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1977977                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1977977                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1977977                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1977977                       # number of overall misses
+system.cpu.icache.overall_misses::total       1977977                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28160163493                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28160163493                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28160163493                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28160163493                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28160163493                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28160163493                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     65991394                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     65991394                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     65991394                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total     65991394                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029973                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029973                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029973                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029973                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029973                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029973                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.850829                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14236.850829                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.850829                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14236.850829                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.850829                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14236.850829                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         6440                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               186                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               190                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    31.096774                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    33.894737                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1886159                       # number of writebacks
-system.cpu.icache.writebacks::total           1886159                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91199                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91199                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91199                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91199                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91199                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91199                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1886711                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1886711                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1886711                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1886711                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1886711                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1886711                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1886245                       # number of writebacks
+system.cpu.icache.writebacks::total           1886245                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91172                       # number of ReadReq MSHR hits
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+system.cpu.icache.demand_mshr_hits::cpu.inst        91172                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91172                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1886805                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1886805                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1886805                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total      1886805                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25184628997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25184628997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25184628997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25184628997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25184628997                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25184628997                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25187429497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  25187429497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25187429497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  25187429497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25187429497                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  25187429497                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377605500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377605500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377605500                       # number of overall MSHR uncacheable cycles
@@ -1268,235 +1258,232 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028592
 system.cpu.icache.demand_mshr_miss_rate::total     0.028592                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028592                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.028592                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13348.429620                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13348.429620                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13348.429620                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.248861                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.248861                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96795                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65029.426786                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5006508                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162120                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.881495                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96776                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65028.780058                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5006507                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162101                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.885109                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49617.960434                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.737497                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.672901                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10365.912312                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5032.143644                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.757110                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.672900                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10369.952431                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5025.112172                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.757146                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000164                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000041                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158171                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.076784                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992270                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65312                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2859                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6695                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55598                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2860                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6691                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55601                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996582                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         44296397                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        44296397                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        58090                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total          70197                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       696811                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       696811                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1848237                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1848237                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           57                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           57                       # number of UpgradeReq hits
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 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       161756                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1866721                       # number of ReadCleanReq hits
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-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       528738                       # number of ReadSharedReq hits
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 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           19                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total           25                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2715                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2715                       # number of UpgradeReq misses
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       135513                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       135513                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19912                       # number of ReadCleanReq misses
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
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 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2632000                       # number of demand (read+write) miss cycles
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 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2632000                       # number of overall miss cycles
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-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.979437                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132666.666667                       # average ReadReq miss latency
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        54000                       # average SCUpgradeReq miss latency
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 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138526.315789                       # average overall miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        89238                       # number of writebacks
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          112                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           19                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total           25                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2715                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2715                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2719                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2719                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135513                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       135513                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19886                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19886                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13239                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13239                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135508                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       135508                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19885                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19885                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13226                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13226                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           19                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19886                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       148752                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168663                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19885                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       148734                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168644                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           19                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19886                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       148752                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168663                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19885                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       148734                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168644                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34132                       # number of ReadReq MSHR uncacheable
@@ -1506,145 +1493,140 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3003
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61717                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       736000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3178000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    184658000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    184658000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       735500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3177500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    184950500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    184950500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       211500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       211500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16248351500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16248351500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2434936503                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2434936503                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1655244000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1655244000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16255528500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16255528500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2436802003                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2436802003                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1652257000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1652257000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       736000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2434936503                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17903595500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20341710003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       735500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2436802003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17907785500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20347765003                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       736000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2434936503                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17903595500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20341710003                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       735500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2436802003                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17907785500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20347765003                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340067500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887116000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227183500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756897000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756897000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887147000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227214500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340067500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644013000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10984080500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5887147000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6227214500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000497                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000356                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.979437                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.979437                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.977706                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.977706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455860                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455860                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010540                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024422                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024422                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010539                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010539                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024401                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024401                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177221                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060318                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000497                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010539                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177216                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060313                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177221                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060318                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000497                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010539                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177216                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060313                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total       127120                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.996317                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.996317                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122583.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total       127100                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68021.515263                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68021.515263                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119902.529647                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119902.529647                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122444.760284                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125027.872196                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125027.872196                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119959.917496                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122544.732361                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122583.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122544.732361                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120655.137467                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.984580                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.143326                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172445.060721                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172445.060721                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181285.775113                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177974.958277                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5483816                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757778                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5483921                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757867                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44951                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops          378                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          378                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq         128774                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2557705                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557731                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       822252                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1886159                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       149793                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2772                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       822205                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1886245                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       149751                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2781                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2777                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1886711                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       542312                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2786                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297260                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297260                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1886805                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542244                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5665508                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2640654                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30972                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133892                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8471026                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241506672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98506345                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48452                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       232436                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          340293905                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      194298                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3054873                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.024677                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.155138                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5665772                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2640441                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30896                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133904                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8471013                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241517552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98498985                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       232368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          340297169                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      194360                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3054889                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.024700                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.155211                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2979489     97.53%     97.53% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              75384      2.47%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2979432     97.53%     97.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              75457      2.47%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3054873                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5401857499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3054889                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5401923998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       258877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834033066                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834168078                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1305567557                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1305452066                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      18867982                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18839481                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75841383                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75872379                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
@@ -1696,7 +1678,7 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43093000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             43093500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1706,9 +1688,9 @@ system.iobus.reqLayer3.occupancy                27500                       # La
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                93500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               649500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               652000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1730,11 +1712,11 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6154500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6160000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33075500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33076500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187134993                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187162988                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
@@ -1758,26 +1740,26 @@ system.iocache.ReadReq_misses::realview.ide          223                       #
 system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          223                       # number of overall misses
-system.iocache.overall_misses::total              223                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28155877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28155877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4550151116                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4550151116                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28155877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28155877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28155877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28155877                       # number of overall miss cycles
+system.iocache.demand_misses::realview.ide        36447                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36447                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36447                       # number of overall misses
+system.iocache.overall_misses::total            36447                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28153877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28153877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4551268111                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4551268111                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4579421988                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4579421988                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4579421988                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4579421988                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36447                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36447                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36447                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36447                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1786,40 +1768,38 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126259.538117                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126259.538117                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125611.503865                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125611.503865                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126259.538117                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126259.538117                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             4                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126250.569507                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126250.569507                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125642.339637                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125642.339637                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125646.061075                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125646.061075                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125646.061075                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125646.061075                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17005877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17005877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737535612                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2737535612                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17005877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17005877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17005877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17005877                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36447                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36447                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36447                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36447                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17003877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17003877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2738656099                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2738656099                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2755659976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2755659976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2755659976                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2755659976                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1828,65 +1808,64 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76259.538117                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76259.538117                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75572.427451                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75572.427451                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75607.319560                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75607.319560                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67504                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67490                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       125428                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7780                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4584                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       125412                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7777                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4588                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133644                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133644                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33373                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133639                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133639                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33359                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450558                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558073                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 631001                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 630948                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16435996                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16599385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16433756                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16597145                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18916505                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18914265                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              487                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402766                       # Request fanout histogram
+system.membus.snoop_fanout::samples            402739                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402766    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402739    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402766                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83667000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402739                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83678000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1740000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1737499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           876048370                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           875953366                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          978678250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          978576250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 1d7221486..b0a0917e9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,166 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.827390                       # Number of seconds simulated
-sim_ticks                                2827390179000                       # Number of ticks simulated
-final_tick                               2827390179000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.837405                       # Number of seconds simulated
+sim_ticks                                2837404742000                       # Number of ticks simulated
+final_tick                               2837404742000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115301                       # Simulator instruction rate (inst/s)
-host_op_rate                                   139868                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2711751203                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 622004                       # Number of bytes of host memory used
-host_seconds                                  1042.64                       # Real time elapsed on the host
-sim_insts                                   120217407                       # Number of instructions simulated
-sim_ops                                     145833000                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 116559                       # Simulator instruction rate (inst/s)
+host_op_rate                                   141347                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2740803117                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 620980                       # Number of bytes of host memory used
+host_seconds                                  1035.25                       # Real time elapsed on the host
+sim_insts                                   120667663                       # Number of instructions simulated
+sim_ops                                     146328933                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         1792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1297536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1327400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8611392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         1728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1294720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1292968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8487552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          512                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           181424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           629012                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       447552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           177584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           590804                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       372608                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12497708                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1297536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       181424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1478960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8852800                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12219756                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1294720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       177584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1472304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8624448                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8870364                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           28                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             22521                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21261                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       134553                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8642012                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           27                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22477                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20723                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       132618                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            8                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2903                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9849                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         6993                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2843                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9252                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         5822                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                198133                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138325                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                193790                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          134757                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142716                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           634                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              458916                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              469479                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3045703                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               139148                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            90                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              456304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              455687                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2991308                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           180                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               64167                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              222471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       158292                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4420228                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         458916                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          64167                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             523083                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3131085                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6198                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               62587                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              208220                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       131320                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4306667                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         456304                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          62587                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             518891                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3039555                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6176                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3137297                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3131085                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          634                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             458916                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             475677                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3045703                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3045745                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3039555                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           90                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             456304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             461863                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2991308                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          180                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              64167                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             222485                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       158292                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7557525                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        198134                       # Number of read requests accepted
-system.physmem.writeReqs                       142716                       # Number of write requests accepted
-system.physmem.readBursts                      198134                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     142716                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12670976                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8883264                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12497772                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8870364                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu1.inst              62587                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             208234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       131320                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             338                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7352412                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        193791                       # Number of read requests accepted
+system.physmem.writeReqs                       139148                       # Number of write requests accepted
+system.physmem.readBursts                      193791                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     139148                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12392320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10304                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8655168                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12219820                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8642012                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      161                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12497                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12182                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12917                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12745                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14769                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12267                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12449                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12406                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12316                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12005                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11767                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10930                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12080                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12638                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12372                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11644                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9110                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9003                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9525                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8599                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8760                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8787                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8590                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8640                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8402                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8397                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7923                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8683                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8738                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8625                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7873                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12077                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11849                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12654                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12755                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14933                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12164                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12136                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11937                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12161                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11860                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11714                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10962                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11429                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12078                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11741                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11180                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8714                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8695                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9246                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9229                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8656                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8632                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8647                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8231                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8368                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8311                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8380                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8024                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8294                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8191                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8117                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7502                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2827389912000                       # Total gap between requests
+system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2837404463500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    3087                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  194468                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  190125                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 138325                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     63072                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     74912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13439                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10395                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8664                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7526                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::8                      4708                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1378                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      855                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      585                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      259                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 134757                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     61827                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     74131                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::9                      1309                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::14                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,163 +188,160 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16                     3705                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::18                     4665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7929                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7989                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9885                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    12144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8596                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1397                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      519                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      283                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41                      183                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::47                       91                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::49                      110                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::53                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       32                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        90813                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      237.346812                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     134.326622                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     300.184335                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          49078     54.04%     54.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17700     19.49%     73.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6123      6.74%     80.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3320      3.66%     83.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2774      3.05%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1638      1.80%     88.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          995      1.10%     89.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          978      1.08%     90.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8207      9.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          90813                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6724                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.444230                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      548.218856                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6721     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6724                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6724                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.642623                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.824239                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.739703                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5581     83.00%     83.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             483      7.18%     90.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              96      1.43%     91.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              46      0.68%     92.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              45      0.67%     92.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              26      0.39%     93.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              56      0.83%     94.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              16      0.24%     94.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             112      1.67%     96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              17      0.25%     96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.07%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              15      0.22%     96.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              76      1.13%     97.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.07%     97.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.07%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              30      0.45%     98.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              72      1.07%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               5      0.07%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.04%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.01%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.10%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.03%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.04%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             6      0.09%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6724                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6642491804                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10354691804                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    989920000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       33550.65                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3607                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                       60                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        87851                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      239.580927                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     135.192901                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     302.402140                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          47357     53.91%     53.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17068     19.43%     73.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5804      6.61%     79.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3391      3.86%     83.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2670      3.04%     86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1518      1.73%     88.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          937      1.07%     89.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          934      1.06%     90.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8172      9.30%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          87851                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6505                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.766180                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      576.399644                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6503     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6505                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6505                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.789700                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.910113                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.034203                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5345     82.17%     82.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             508      7.81%     89.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             102      1.57%     91.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              40      0.61%     92.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              39      0.60%     92.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              25      0.38%     93.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              50      0.77%     93.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              17      0.26%     94.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             116      1.78%     95.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              12      0.18%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.11%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              11      0.17%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              77      1.18%     97.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               7      0.11%     97.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.08%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.40%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              87      1.34%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.05%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             9      0.14%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.08%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6505                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6373061511                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10003624011                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    968150000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       32913.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  52300.65                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.48                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.42                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.14                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  51663.61                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.31                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.05                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        28.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165266                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     80705                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.14                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8295114.90                       # Average gap between requests
-system.physmem.pageHitRate                      73.03                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  356771520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  194667000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 797401800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                463449600                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184671358560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80516584620                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1625805455250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1892805688350                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.453328                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2704566595208                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94412760000                       # Time in different power states
+system.physmem.avgWrQLen                        23.46                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     161607                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     79408                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.46                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.71                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8522295.27                       # Average gap between requests
+system.physmem.pageHitRate                      73.28                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  346988880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  189329250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 783931200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                453924000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185325366720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80760068955                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1631599751250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1899459360255                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.435829                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2714212324269                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94747120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     28410820792                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28445283231                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  329774760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  179936625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 746865600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                435980880                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184671358560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80145816435                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1626130690500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1892640423360                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.394877                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2705113148361                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94412760000                       # Time in different power states
+system.physmem_1.actEnergy                  317164680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  173056125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 726375000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                422411760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185325366720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80003948850                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1632263014500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1899231337635                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.355466                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2715316377598                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94747120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27864169139                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27339711152                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          176                       # Number of bytes read from this memory
@@ -355,13 +352,13 @@ system.realview.nvmem.bytes_inst_read::total          288
 system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.inst           11                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             18                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst           39                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.inst           62                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total              102                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           39                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu1.inst           62                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total          102                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           40                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           39                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           62                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             102                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
@@ -370,19 +367,19 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               53911245                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         24947324                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           985007                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            32642222                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               14256732                       # Number of BTB hits
+system.cpu0.branchPred.lookups               53928985                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         24980647                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           980964                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            32646997                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               14259525                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            43.675740                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15584760                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             34685                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups       10159968                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           9991718                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses          168250                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted        52822                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            43.677907                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15577797                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             34581                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups       10158007                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           9989505                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          168502                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        52676                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -413,87 +410,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    71875                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               71875                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26071                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21701                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        24103                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        47772                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   520.796701                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3158.268863                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        46423     97.18%     97.18% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          981      2.05%     99.23% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          165      0.35%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767          156      0.33%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959           17      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           25      0.05%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    71164                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               71164                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25792                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21511                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        23861                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        47303                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   513.360675                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3057.570781                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        45975     97.19%     97.19% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          952      2.01%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          188      0.40%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          150      0.32%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           13      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           18      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-122879            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        47772                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        18721                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11203.514770                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9623.609798                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  9038.861696                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        18593     99.32%     99.32% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535           88      0.47%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839           23      0.12%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607           16      0.09%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        18721                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  87200107652                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.546732                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.508218                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0    39687331700     45.51%     45.51% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    47447148952     54.41%     99.92% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2       30000500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::3       16923500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4        5972000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::5        3342500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6        3974500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::7        1269500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8         992000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::9         652500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkWaitTime::total        47303                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        18252                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10854.262547                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9468.640105                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6407.913673                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        18169     99.55%     99.55% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           76      0.42%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            6      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        18252                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  80034835468                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.679509                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.477500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0    25803805568     32.24%     32.24% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    54166837400     67.68%     99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2       30476500      0.04%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::3       15818500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4        5905000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::5        3281500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6        3666500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::7        1298500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8         960000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::9         729000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::10        669000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::11        287500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12        887500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::11        276500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12        755500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::13        113500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14        101000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::15        441500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  87200107652                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5974     77.64%     77.64% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1720     22.36%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         7694                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        71875                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walksPending::14        120500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::15        122000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  80034835468                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5842     79.40%     79.40% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1516     20.60%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7358                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        71164                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        71875                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7694                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        71164                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7358                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7694                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        79569                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7358                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        78522                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    24391036                       # DTB read hits
-system.cpu0.dtb.read_misses                     61424                       # DTB read misses
-system.cpu0.dtb.write_hits                   18141184                       # DTB write hits
-system.cpu0.dtb.write_misses                    10451                       # DTB write misses
+system.cpu0.dtb.read_hits                    24435903                       # DTB read hits
+system.cpu0.dtb.read_misses                     60770                       # DTB read misses
+system.cpu0.dtb.write_hits                   18100495                       # DTB write hits
+system.cpu0.dtb.write_misses                    10394                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3871                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      259                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2351                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3811                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      278                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2366                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      984                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24452460                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18151635                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      972                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24496673                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18110889                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         42532220                       # DTB hits
-system.cpu0.dtb.misses                          71875                       # DTB misses
-system.cpu0.dtb.accesses                     42604095                       # DTB accesses
+system.cpu0.dtb.hits                         42536398                       # DTB hits
+system.cpu0.dtb.misses                          71164                       # DTB misses
+system.cpu0.dtb.accesses                     42607562                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -523,55 +519,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    11562                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort               11562                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4001                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6396                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore         1165                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        10397                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   461.575454                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  2367.707906                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095         9981     96.00%     96.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          185      1.78%     97.78% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287          127      1.22%     99.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           59      0.57%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479           11      0.11%     99.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575           23      0.22%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767            2      0.02%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            4      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959            3      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        10397                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         4031                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 11997.147110                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11095.550949                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5265.028524                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         3778     93.72%     93.72% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          218      5.41%     99.13% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           33      0.82%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         4031                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  22774753212                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.815515                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.388020                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     4202728000     18.45%     18.45% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    18570993712     81.54%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2         925000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         106500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  22774753212                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2507     87.47%     87.47% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          359     12.53%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2866                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    11512                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               11512                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3903                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6443                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         1166                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        10346                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   443.263097                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2195.478359                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095         9924     95.92%     95.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          200      1.93%     97.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          136      1.31%     99.17% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           57      0.55%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479            9      0.09%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           14      0.14%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            3      0.03%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        10346                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         4037                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 11847.659153                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 10978.083476                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5361.043324                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         3811     94.40%     94.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          205      5.08%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           19      0.47%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::147456-163839            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         4037                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  19905249824                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.798667                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.401122                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     4008511500     20.14%     20.14% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    15895875324     79.86%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         793000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3          70000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  19905249824                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2512     87.50%     87.50% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          359     12.50%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2871                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11562                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11562                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11512                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11512                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2866                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2866                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        14428                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    74050785                       # ITB inst hits
-system.cpu0.itb.inst_misses                     11562                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2871                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2871                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        14383                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    74030113                       # ITB inst hits
+system.cpu0.itb.inst_misses                     11512                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -580,1041 +576,1016 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2601                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2605                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     2163                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     2155                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                74062347                       # ITB inst accesses
-system.cpu0.itb.hits                         74050785                       # DTB hits
-system.cpu0.itb.misses                          11562                       # DTB misses
-system.cpu0.itb.accesses                     74062347                       # DTB accesses
-system.cpu0.numCycles                       210807967                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                74041625                       # ITB inst accesses
+system.cpu0.itb.hits                         74030113                       # DTB hits
+system.cpu0.itb.misses                          11512                       # DTB misses
+system.cpu0.itb.accesses                     74041625                       # DTB accesses
+system.cpu0.numCycles                       210680851                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          21220653                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     200130599                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   53911245                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          39833210                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    180362708                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                5820684                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    154995                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               66964                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       420974                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       452324                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       103497                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 74050081                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               272746                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   5705                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         205692457                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.188766                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.306289                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          21171726                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     200049751                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   53928985                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          39826827                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    180241612                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                5811272                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    155130                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               70350                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       431363                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       450452                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       103873                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 74029415                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               271959                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   5637                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         205530142                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.189019                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.306227                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                98524588     47.90%     47.90% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                31037557     15.09%     62.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                14908217      7.25%     70.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                61222095     29.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                98403220     47.88%     47.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                31059279     15.11%     62.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                14883047      7.24%     70.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                61184596     29.77%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           205692457                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.255736                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.949350                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26429213                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            111222366                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 60319076                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              5157963                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               2563839                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             3171648                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               350947                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             158388827                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4014782                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               2563839                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                35280795                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               13301493                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      85153816                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 56482950                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             12909564                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             141500597                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1085672                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1524488                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                177088                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 62946                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               8550384                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          145816753                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            652563275                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       157207618                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups            11000                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            133932927                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                11883815                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           2738789                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       2591099                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 23044959                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            25364147                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           19673316                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1767343                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2535257                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 138424520                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1769995                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                136412034                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           484040                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       11120854                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     22999814                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        127192                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    205692457                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.663184                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       0.962224                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           205530142                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.255975                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.949539                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26358424                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            111125063                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 60339651                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              5146338                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               2560666                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3166290                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               349435                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             158330686                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              3996082                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               2560666                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                35191325                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               13316748                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      85113900                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 56510449                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             12837054                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             141455630                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1082284                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1522598                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                176451                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 63363                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8486313                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          145805955                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            652241827                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       157050612                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            10963                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            133960988                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                11844956                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           2734835                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       2587650                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 23017642                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            25406580                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           19629611                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1770048                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2573383                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 138387691                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1764615                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                136383682                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           482804                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       11087380                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     22916211                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        126267                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    205530142                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.663570                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.962312                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          126945183     61.72%     61.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           34499506     16.77%     78.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           31998886     15.56%     94.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           11080832      5.39%     99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1167990      0.57%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 60      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          126796339     61.69%     61.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           34494575     16.78%     78.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           31991292     15.57%     94.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           11085283      5.39%     99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1162591      0.57%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 62      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      205692457                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      205530142                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               11130033     43.82%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                    71      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.82% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5937286     23.38%     67.20% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              8330186     32.80%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               11095363     43.83%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    72      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5922142     23.40%     67.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8295120     32.77%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2315      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             91960000     67.41%     67.42% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult              113905      0.08%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          8243      0.01%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             91932498     67.41%     67.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult              113960      0.08%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8109      0.01%     67.50% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.50% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.50% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            25115664     18.41%     85.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           19211906     14.08%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            25157178     18.45%     85.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           19169621     14.06%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             136412034                       # Type of FU issued
-system.cpu0.iq.rate                          0.647091                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   25397576                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.186183                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         504359597                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        151322890                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    132769388                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              38543                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             13252                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses        11438                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             161782111                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  25184                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          383563                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             136383682                       # Type of FU issued
+system.cpu0.iq.rate                          0.647347                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   25312697                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.185599                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         504054876                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        151247362                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    132748931                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              38130                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             13196                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses        11435                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             161669314                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  24750                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          382212                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2036205                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2638                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        20853                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       948035                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2031269                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2587                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        20948                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       944545                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       126036                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       394781                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       125569                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       392740                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               2563839                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1921080                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               231914                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          140382056                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               2560666                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1904881                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               242910                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          140340084                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             25364147                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            19673316                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            906447                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 31018                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               175567                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         20853                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        275420                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       424017                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              699437                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            135325292                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             24646519                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1015002                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             25406580                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            19629611                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            903245                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 30849                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               186908                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         20948                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        273967                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       422470                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              696437                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            135301485                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             24689718                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1011162                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       187541                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    43690093                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                26111417                       # Number of branches executed
-system.cpu0.iew.exec_stores                  19043574                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.641936                       # Inst execution rate
-system.cpu0.iew.wb_sent                     134725872                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    132780826                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 67751819                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                109549817                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.629866                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.618457                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10037586                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1642803                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           638504                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    202442995                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.638330                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.339217                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       187778                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    43692090                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                26150301                       # Number of branches executed
+system.cpu0.iew.exec_stores                  19002372                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.642211                       # Inst execution rate
+system.cpu0.iew.wb_sent                     134704568                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    132760366                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 67768009                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                109468646                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.630149                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.619063                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10008673                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1638348                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           635994                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    202285941                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.638783                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.339502                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    140546392     69.43%     69.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     34245976     16.92%     86.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     12926596      6.39%     92.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3383235      1.67%     94.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      4977119      2.46%     96.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      2872114      1.42%     98.28% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1322991      0.65%     98.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       578946      0.29%     99.21% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1589626      0.79%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    140398916     69.41%     69.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     34201466     16.91%     86.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     12970060      6.41%     92.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3407217      1.68%     94.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      4957947      2.45%     96.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      2836864      1.40%     98.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1346808      0.67%     98.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       576737      0.29%     99.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1589926      0.79%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    202442995                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           106684229                       # Number of instructions committed
-system.cpu0.commit.committedOps             129225495                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    202285941                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           106719327                       # Number of instructions committed
+system.cpu0.commit.committedOps             129216760                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      42053222                       # Number of memory references committed
-system.cpu0.commit.loads                     23327941                       # Number of loads committed
-system.cpu0.commit.membars                     666720                       # Number of memory barriers committed
-system.cpu0.commit.branches                  25467916                       # Number of branches committed
+system.cpu0.commit.refs                      42060376                       # Number of memory references committed
+system.cpu0.commit.loads                     23375310                       # Number of loads committed
+system.cpu0.commit.membars                     665131                       # Number of memory barriers committed
+system.cpu0.commit.branches                  25508530                       # Number of branches committed
 system.cpu0.commit.fp_insts                     11428                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                112793765                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             4892953                       # Number of function calls committed.
+system.cpu0.commit.int_insts                112737159                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             4888773                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        87052485     67.36%     67.36% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult         111545      0.09%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         8243      0.01%     67.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       23327941     18.05%     85.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      18725281     14.49%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        87036683     67.36%     67.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult         111592      0.09%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8109      0.01%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       23375310     18.09%     85.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      18685066     14.46%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        129225495                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1589626                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   316721982                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  281765642                       # The number of ROB writes
-system.cpu0.timesIdled                         131866                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        5115510                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5443972636                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  106532386                       # Number of Instructions Simulated
-system.cpu0.committedOps                    129073652                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.978816                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.978816                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.505353                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.505353                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               146797472                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               83857123                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     9583                       # number of floating regfile reads
+system.cpu0.commit.op_class_0::total        129216760                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1589926                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   316533140                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  281685162                       # The number of ROB writes
+system.cpu0.timesIdled                         132617                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5150709                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5464128831                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  106567484                       # Number of Instructions Simulated
+system.cpu0.committedOps                    129064917                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.976971                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.976971                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.505824                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.505824                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               146676309                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               83772418                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     9577                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                    2716                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                477737826                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                51222601                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              282455977                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1264842                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           752726                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          494.858519                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           38773458                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           753238                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            51.475706                       # Average number of references to valid blocks.
+system.cpu0.cc_regfile_reads                477802916                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                51327219                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              282498014                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1261276                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           747573                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          499.341020                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           38792744                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           748085                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            51.856064                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        426635500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.858519                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966521                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.966521                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   499.341020                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.975275                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.975275                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         83704103                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        83704103                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     22086605                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       22086605                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     15435818                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15435818                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       316186                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       316186                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       372593                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       372593                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370988                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       370988                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     37522423                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        37522423                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     37838609                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       37838609                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       688506                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       688506                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1977745                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1977745                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       154100                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       154100                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25656                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        25656                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20273                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20273                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2666251                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2666251                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2820351                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2820351                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9974637500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   9974637500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36928416860                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  36928416860                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    417346500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    417346500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    525290500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    525290500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       179000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       179000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  46903054360                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  46903054360                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  46903054360                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  46903054360                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     22775111                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     22775111                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     17413563                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17413563                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       470286                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       470286                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       398249                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       398249                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391261                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       391261                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     40188674                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     40188674                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     40658960                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     40658960                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030231                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.030231                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113575                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.113575                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.327673                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.327673                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064422                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064422                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051815                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051815                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066343                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.066343                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069366                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.069366                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14487.364671                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14487.364671                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18671.980897                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.980897                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16267.013564                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16267.013564                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25910.842007                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25910.842007                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         83715991                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        83715991                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     22140887                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       22140887                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15403032                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15403032                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       315432                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       315432                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       371543                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       371543                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       369802                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       369802                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     37543919                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        37543919                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     37859351                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       37859351                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       684637                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       684637                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1972030                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1972030                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       153419                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       153419                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25627                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25627                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20274                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20274                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2656667                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2656667                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2810086                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2810086                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9946449500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   9946449500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36588625370                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  36588625370                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    415520500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    415520500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    535292500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    535292500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       777000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       777000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  46535074870                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  46535074870                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  46535074870                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  46535074870                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     22825524                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     22825524                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17375062                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17375062                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       468851                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       468851                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397170                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       397170                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       390076                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       390076                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     40200586                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     40200586                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     40669437                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     40669437                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029994                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.029994                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113498                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.113498                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.327223                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.327223                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064524                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064524                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051974                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051974                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066085                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.066085                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069096                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.069096                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14528.063047                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14528.063047                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18553.787402                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18553.787402                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16214.168650                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16214.168650                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26402.905199                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26402.905199                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17591.387443                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17591.387443                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16630.218849                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16630.218849                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          989                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      5684279                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               52                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         212555                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    19.019231                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    26.742627                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       752726                       # number of writebacks
-system.cpu0.dcache.writebacks::total           752726                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       276877                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       276877                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1641015                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1641015                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18966                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18966                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1917892                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1917892                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1917892                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1917892                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       411629                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       411629                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       336730                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       336730                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107461                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       107461                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6690                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6690                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20273                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20273                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       748359                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       748359                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       855820                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       855820                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31816                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31816                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60315                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60315                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5149646500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5149646500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7737247391                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7737247391                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1800196500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1800196500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    108932500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    108932500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    505022500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    505022500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       174000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       174000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12886893891                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  12886893891                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14687090391                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  14687090391                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6623903000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6623903000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5395425500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5395425500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12019328500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12019328500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.018074                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.018074                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019337                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019337                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228501                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228501                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016799                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016799                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051815                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051815                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018621                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.018621                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.021049                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.021049                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12510.407430                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12510.407430                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22977.600425                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22977.600425                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16752.091456                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.091456                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16282.884903                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16282.884903                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24911.088640                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24911.088640                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17516.337151                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17516.337151                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16560.018046                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16560.018046                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         1975                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      5610717                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               47                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         211787                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    42.021277                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    26.492263                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       747573                       # number of writebacks
+system.cpu0.dcache.writebacks::total           747573                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       276373                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       276373                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1635448                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1635448                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18943                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18943                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1911821                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1911821                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1911821                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1911821                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       408264                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       408264                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       336582                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       336582                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106895                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       106895                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6684                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6684                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20274                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20274                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       744846                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       744846                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       851741                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       851741                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31822                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31822                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28485                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28485                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60307                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60307                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5115635000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5115635000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7714022398                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7714022398                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1800093000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1800093000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    106991500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    106991500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    515034500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    515034500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       761000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       761000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12829657398                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12829657398                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14629750398                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  14629750398                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6627444500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6627444500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6627444500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6627444500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017886                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017886                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019372                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019372                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.227994                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227994                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016829                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016829                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051974                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051974                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018528                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018528                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020943                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020943                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12530.213293                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12530.213293                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22918.701529                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22918.701529                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16839.824126                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16839.824126                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16007.106523                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16007.106523                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25403.694387                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25403.694387                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17220.202992                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17220.202992                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17161.424588                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17161.424588                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208194.084737                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208194.084737                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189319.818239                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189319.818239                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199275.942966                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199275.942966                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1311471                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.728689                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           72677991                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1311983                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            55.395528                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       8207383000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.728689                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999470                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999470                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17224.577158                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17224.577158                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17176.289973                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17176.289973                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208266.120923                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208266.120923                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109895.111679                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109895.111679                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.replacements          1304852                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.377336                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           72663769                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1305364                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            55.665522                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       8205905000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.377336                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998784                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998784                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          124                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        149404895                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       149404895                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     72677991                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       72677991                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     72677991                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        72677991                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     72677991                       # number of overall hits
-system.cpu0.icache.overall_hits::total       72677991                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1368448                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1368448                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1368448                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1368448                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1368448                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1368448                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14924586060                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14924586060                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14924586060                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14924586060                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14924586060                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14924586060                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     74046439                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     74046439                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     74046439                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     74046439                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     74046439                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     74046439                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018481                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.018481                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018481                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.018481                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018481                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.018481                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10906.213506                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10906.213506                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10906.213506                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10906.213506                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10906.213506                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10906.213506                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1977903                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets         1805                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           120515                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             16                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.412090                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets   112.812500                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1311471                       # number of writebacks
-system.cpu0.icache.writebacks::total          1311471                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56430                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        56430                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        56430                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        56430                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        56430                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        56430                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1312018                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1312018                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1312018                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1312018                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1312018                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1312018                       # number of overall MSHR misses
+system.cpu0.icache.tags.tag_accesses        149356824                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       149356824                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     72663769                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       72663769                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     72663769                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        72663769                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     72663769                       # number of overall hits
+system.cpu0.icache.overall_hits::total       72663769                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1361937                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1361937                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1361937                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1361937                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1361937                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1361937                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14920933108                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14920933108                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14920933108                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14920933108                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14920933108                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14920933108                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     74025706                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     74025706                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     74025706                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     74025706                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     74025706                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     74025706                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018398                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.018398                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018398                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.018398                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018398                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.018398                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10955.670569                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10955.670569                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10955.670569                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10955.670569                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10955.670569                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10955.670569                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1976630                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         1824                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           119804                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             15                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.498865                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   121.600000                       # average number of cycles each access was blocked
+system.cpu0.icache.writebacks::writebacks      1304852                       # number of writebacks
+system.cpu0.icache.writebacks::total          1304852                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56524                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        56524                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        56524                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        56524                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        56524                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        56524                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1305413                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1305413                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1305413                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1305413                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1305413                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1305413                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13396366068                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  13396366068                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13396366068                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  13396366068                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13396366068                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  13396366068                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13391499134                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  13391499134                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13391499134                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  13391499134                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13391499134                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  13391499134                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    420576498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    420576498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    420576498                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    420576498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017719                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017719                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017719                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017719                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017719                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017719                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10210.504786                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10210.504786                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10210.504786                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10210.504786                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10210.504786                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10210.504786                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017635                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017635                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017635                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017635                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017635                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017635                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10258.438620                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10258.438620                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10258.438620                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10258.438620                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10258.438620                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10258.438620                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1932548                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1935408                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         2604                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1921401                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1924253                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2599                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       246016                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          282767                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16108.615116                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3429175                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          298912                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           11.472189                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       246531                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          284359                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16097.390005                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3405020                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          300497                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           11.331294                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14681.579143                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.440463                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.496999                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1415.098510                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.896092                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000698                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000030                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.086371                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.983192                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          981                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14688.513215                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.811138                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.794692                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1396.270960                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.896516                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000721                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000049                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.085222                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.982507                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          968                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15155                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           39                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          298                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          453                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          191                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15161                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           20                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          306                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          421                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          221                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          511                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4586                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7902                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2036                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059875                       # Percentage of cache occupancy per task id
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 system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.924988                       # Percentage of cache occupancy per task id
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 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.264715                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.264715                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040962                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040962                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.184861                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.184861                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.005818                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.008909                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040962                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.212712                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.102967                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.005818                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.008909                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040962                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.212712                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.102967                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.807910                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker        26128                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31828.810021                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3226.018871                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3226.018871                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2068.934050                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2068.934050                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.268489                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.268489                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042904                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042904                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.187470                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.187470                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.005868                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.006909                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042904                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.215824                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.105236                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.005868                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.006909                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042904                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.215824                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.105236                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33335.211268                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27716.494845                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32129.424779                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3394.742021                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3394.742021                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2139.858933                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2139.858933                       # average SCUpgradeReq miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54984.246011                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54984.246011                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69820.633732                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69820.633732                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35205.261837                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35205.261837                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.807910                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker        26128                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69820.633732                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43790.109586                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 49957.098498                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.807910                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker        26128                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69820.633732                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43790.109586                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 49957.098498                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          204                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53678.704488                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53678.704488                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68104.124632                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68104.124632                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34980.369483                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34980.369483                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33335.211268                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27716.494845                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68104.124632                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43120.992120                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 49191.256044                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33335.211268                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27716.494845                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68104.124632                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43120.992120                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 49191.256044                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          103                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    25.750000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.unused_prefetches           10407                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks       233202                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          233202                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.unused_prefetches           10783                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       233335                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          233335                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
 system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        32963                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        32963                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           42                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           42                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          774                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          774                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           42                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        33737                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        33780                       # number of demand (read+write) MSHR hits
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-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        33737                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        33780                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          353                       # number of ReadReq MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_misses::total          478                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       262414                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       262414                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55429                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55429                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20273                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20273                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41558                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41558                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        53700                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        53700                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        96397                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        96397                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          353                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          125                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        53700                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       137955                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       192133                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          353                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        53700                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       137955                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total       454547                       # number of overall MSHR misses
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+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           49                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          794                       # number of ReadSharedReq MSHR hits
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55896                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55896                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20274                       # number of SCUpgradeReq MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31816                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34819                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
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 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60315                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63318                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9841000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2516000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     12357000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  22141788258                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  22141788258                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1433561500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1433561500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    351805000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    351805000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       136500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       136500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2493972500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2493972500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3428273498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3428273498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2782772498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2782772498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      9841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2516000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3428273498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5276744998                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   8717375496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      9841000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2516000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3428273498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5276744998                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  22141788258                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  30859163754                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60307                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63310                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9704000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2096500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     11800500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21751180640                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21751180640                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1466856000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1466856000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    361881500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    361881500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       639000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       639000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2468105500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2468105500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3476206000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3476206000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2780887498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2780887498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      9704000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2096500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3476206000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5248992998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   8736999498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      9704000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2096500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3476206000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5248992998                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21751180640                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  30488180138                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    398052500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6369072500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6767125000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5178546465                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5178546465                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6372573500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6770626000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    398052500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11547618965                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11945671465                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005801                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.008909                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.006384                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000002                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6372573500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6770626000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005868                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.006838                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.006051                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.147623                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.147623                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040930                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040930                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.183388                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.183388                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.005801                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.008909                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040930                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.170914                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.087571                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.005801                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.008909                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040930                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.170914                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.151684                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.151684                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042866                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042866                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.185948                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.185948                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.005868                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.006838                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042866                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.173957                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.089817                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.005868                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.006838                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042866                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.173957                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.207175                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        20128                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25851.464435                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84377.313169                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25863.022966                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25863.022966                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17353.376412                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17353.376412                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.208656                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26165.188470                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83862.236822                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26242.593388                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26242.593388                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.536352                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17849.536352                       # average SCUpgradeReq mshr miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
 system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60011.850907                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60011.850907                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63841.219702                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63841.219702                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28867.833003                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28867.833003                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker        20128                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63841.219702                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38249.755341                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45371.568112                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker        20128                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63841.219702                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38249.755341                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67889.929433                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57928.589870                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57928.589870                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62123.918793                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62123.918793                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28665.101564                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28665.101564                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62123.918793                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.119561                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44570.615622                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27335.211268                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21838.541667                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62123.918793                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.119561                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83862.236822                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66949.015881                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200184.576942                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194351.503489                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181709.760518                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181709.760518                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200256.850606                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194418.549892                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191455.176407                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188661.541189                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      4281853                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2162712                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        32662                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       328300                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       324452                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3848                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        121117                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2006967                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28499                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28499                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       741466                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1556492                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       207602                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       320187                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        85477                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42629                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       113152                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           18                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       299842                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       296502                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1312018                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       596340                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3402                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3941483                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2739757                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        30823                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       130322                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6842385                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    167949424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104071122                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        56120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       243396                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         272320062                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1018529                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3250936                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.119239                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.327701                       # Request fanout histogram
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105668.885867                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106944.021482                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests      4258986                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2151003                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        32472                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       329266                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       324071                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         5195                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        120454                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1996565                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28485                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28485                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       738714                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1547561                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       211301                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       317009                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        86208                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42633                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113720                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           30                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       299261                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       296052                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1305413                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       592862                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3357                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3921638                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2727487                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        30828                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       129308                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6809261                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    167102064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    103511640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        56156                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       241976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         270911836                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1020612                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      3240855                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.120146                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.330026                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2867147     88.19%     88.19% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            379941     11.69%     99.88% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              3848      0.12%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2856673     88.15%     88.15% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            378987     11.69%     99.84% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              5195      0.16%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3250936                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    4282821452                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3240855                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    4259428994                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    113625688                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115114135                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1971630792                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1961743252                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1296047217                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1289450748                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     16802481                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     16799978                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     69515913                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     68856412                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                3871087                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2220502                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           213805                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             1955914                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1266404                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3975194                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2297364                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           224488                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2012976                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1308063                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            64.747428                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 774472                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              5638                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups         216728                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits            192718                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses           24010                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted         5536                       # Number of mispredicted indirect branches.
+system.cpu1.branchPred.BTBHitPct            64.981550                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 784876                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              5668                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups         213732                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits            189273                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           24459                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted         5870                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1644,89 +1615,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    15135                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               15135                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8000                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3062                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         4073                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        11062                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   636.232146                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3393.246458                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        10520     95.10%     95.10% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          182      1.65%     96.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          208      1.88%     98.63% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383           44      0.40%     99.02% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           10      0.09%     99.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575           20      0.18%     99.29% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671            4      0.04%     99.33% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767           63      0.57%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863            5      0.05%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959            2      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::40960-45055            2      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    15858                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               15858                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8476                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3068                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         4314                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        11544                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   612.006237                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3319.733995                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        11004     95.32%     95.32% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          170      1.47%     96.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          217      1.88%     98.67% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383           35      0.30%     98.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           27      0.23%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           16      0.14%     99.35% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671            4      0.03%     99.38% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           61      0.53%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863            4      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-45055            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::45056-49151            2      0.02%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::53248-57343            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        11062                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         3287                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11641.922726                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10290.587277                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7252.269841                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         2804     85.31%     85.31% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          438     13.33%     98.63% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151           35      1.06%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            8      0.24%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::total        11544                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         3223                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11620.074465                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10250.129632                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7588.563203                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         2748     85.26%     85.26% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          431     13.37%     98.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151           35      1.09%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            6      0.19%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455            2      0.06%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         3287                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  78326908560                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.188289                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.393350                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    63608298256     81.21%     81.21% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    14703547304     18.77%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2       10074500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3        1868000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4         997000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5         536500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6        1004000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7         156000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8          32000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9          91000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10         15500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11         43500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12        105500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13          9000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14          4500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15        126000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  78326908560                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1232     71.42%     71.42% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          493     28.58%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1725                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15135                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total         3223                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  88338958560                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.197151                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.399884                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    70951902092     80.32%     80.32% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    17371924968     19.67%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       10393500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        1802000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4         890500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5         405500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6         991000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7         249000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8          24000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9         135000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10          9000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11         41000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12         36000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13         10500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14          6000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15        138500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  88338958560                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1231     73.23%     73.23% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          450     26.77%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1681                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15858                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15135                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1725                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15858                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1681                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1725                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        16860                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1681                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        17539                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3481626                       # DTB read hits
-system.cpu1.dtb.read_misses                     13250                       # DTB read misses
-system.cpu1.dtb.write_hits                    2942267                       # DTB write hits
-system.cpu1.dtb.write_misses                     1885                       # DTB write misses
+system.cpu1.dtb.read_hits                     3568678                       # DTB read hits
+system.cpu1.dtb.read_misses                     13961                       # DTB read misses
+system.cpu1.dtb.write_hits                    3021632                       # DTB write hits
+system.cpu1.dtb.write_misses                     1897                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1665                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       44                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   252                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1646                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       39                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   351                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      252                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3494876                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2944152                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3582639                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3023529                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6423893                       # DTB hits
-system.cpu1.dtb.misses                          15135                       # DTB misses
-system.cpu1.dtb.accesses                      6439028                       # DTB accesses
+system.cpu1.dtb.hits                          6590310                       # DTB hits
+system.cpu1.dtb.misses                          15858                       # DTB misses
+system.cpu1.dtb.accesses                      6606168                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1756,59 +1728,56 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     5379                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                5379                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2691                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2153                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          535                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         4844                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   218.414533                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  1692.156629                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-2047         4709     97.21%     97.21% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::2048-4095           42      0.87%     98.08% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-6143           42      0.87%     98.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::6144-8191           13      0.27%     99.22% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-10239           10      0.21%     99.42% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::10240-12287            7      0.14%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-14335            4      0.08%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::14336-16383            5      0.10%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-18431            2      0.04%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-26623            2      0.04%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::26624-28671            6      0.12%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-30719            2      0.04%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         4844                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1373                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 10949.016752                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  9997.704100                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5248.867098                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          278     20.25%     20.25% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383         1006     73.27%     93.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575           56      4.08%     97.60% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           16      1.17%     98.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959            9      0.66%     99.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151            5      0.36%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.15%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::73728-81919            1      0.07%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1373                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  18192386416                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.925541                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.262684                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1355392264      7.45%      7.45% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    16836194152     92.55%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2         800000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  18192386416                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          695     82.94%     82.94% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          143     17.06%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          838                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     5405                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                5405                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2736                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2193                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          476                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         4929                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   233.921688                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  1867.315872                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-4095         4828     97.95%     97.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-8191           62      1.26%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-12287           17      0.34%     99.55% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-16383            7      0.14%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-20479            2      0.04%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-28671            8      0.16%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-32767            2      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-36863            3      0.06%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         4929                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1313                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11012.566641                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10237.942197                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  4989.359306                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          243     18.51%     18.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383          995     75.78%     94.29% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575           50      3.81%     98.10% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           10      0.76%     98.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959            8      0.61%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            4      0.30%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.15%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::81920-90111            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1313                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  15319490028                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.914748                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.279455                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1306821764      8.53%      8.53% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    14011918764     91.46%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2         701000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3          48500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  15319490028                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          694     82.92%     82.92% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          143     17.08%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          837                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         5379                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         5379                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         5405                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         5405                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          838                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          838                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         6217                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                     6965528                       # ITB inst hits
-system.cpu1.itb.inst_misses                      5379                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          837                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          837                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         6242                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     7144027                       # ITB inst hits
+system.cpu1.itb.inst_misses                      5405                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1817,1019 +1786,1002 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     902                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     901                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      384                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      383                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 6970907                       # ITB inst accesses
-system.cpu1.itb.hits                          6965528                       # DTB hits
-system.cpu1.itb.misses                           5379                       # DTB misses
-system.cpu1.itb.accesses                      6970907                       # DTB accesses
-system.cpu1.numCycles                        32092744                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 7149432                       # ITB inst accesses
+system.cpu1.itb.hits                          7144027                       # DTB hits
+system.cpu1.itb.misses                           5405                       # DTB misses
+system.cpu1.itb.accesses                      7149432                       # DTB accesses
+system.cpu1.numCycles                        32549087                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           7782299                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      20640770                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3871087                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           2233594                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     22614955                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 645830                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     74008                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               29636                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       160010                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       275842                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        16624                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  6964682                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                92359                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   1934                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          31276289                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.805380                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.188121                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           8029847                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      21178907                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3975194                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           2282212                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     22801485                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 668344                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     75754                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               30605                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       165807                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       282475                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        16137                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  7143243                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                97050                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   1864                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          31736282                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.814476                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.191251                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                19613481     62.71%     62.71% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 4233968     13.54%     76.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 1331194      4.26%     80.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 6097646     19.50%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                19759016     62.26%     62.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 4355316     13.72%     75.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1372720      4.33%     80.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 6249230     19.69%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            31276289                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.120622                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.643160                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 6336736                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             16565133                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  7246187                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               914830                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                213403                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              597831                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               111765                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              19357447                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               835377                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                213403                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 7521212                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2374588                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      11566982                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  6962571                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2637533                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              18397316                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               130089                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               214163                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 27812                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 12950                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1772414                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           18194678                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             86130501                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        21182613                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups                5                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             16531195                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1663483                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            369349                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        301926                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2462039                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             3681622                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            3198899                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           554263                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          453752                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  17730825                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             507077                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 17704327                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            59995                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1478553                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      3387139                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         37397                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     31276289                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.566062                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.918538                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            31736282                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.122129                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.650676                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 6554868                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             16518365                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  7517718                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               925247                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                220084                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              615416                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               116450                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              19951417                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               870614                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                220084                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 7767251                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2357969                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      11576087                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  7215568                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2599323                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              18979477                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               138008                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               212778                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 28608                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 12545                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1724298                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           18792497                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             88805063                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        21879536                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups                8                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             17041996                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1750501                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            370474                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        302824                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2489623                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             3780648                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            3305194                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           561156                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          470424                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  18301855                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             511708                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 18248720                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            63617                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1549546                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      3571368                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         37688                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     31736282                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.575011                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.923740                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           20752127     66.35%     66.35% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            5297030     16.94%     83.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            3493708     11.17%     94.46% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            1513821      4.84%     99.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             219597      0.70%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                  6      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           20906070     65.87%     65.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            5429676     17.11%     82.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3608533     11.37%     94.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            1566039      4.93%     99.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             225959      0.71%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                  5      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       31276289                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       31736282                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                1110256     27.87%     27.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   673      0.02%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1321373     33.17%     61.07% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              1550767     38.93%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                1149585     28.00%     28.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   664      0.02%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     28.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1347729     32.82%     60.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1608151     39.16%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               24      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             10922763     61.70%     61.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               25931      0.15%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          3184      0.02%     61.86% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.86% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.86% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.86% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             3652522     20.63%     82.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            3099903     17.51%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             11270903     61.76%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               26506      0.15%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.91% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3164      0.02%     61.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             3745042     20.52%     82.45% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            3203081     17.55%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              17704327                       # Type of FU issued
-system.cpu1.iq.rate                          0.551661                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    3983069                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.224977                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          70728007                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         19724904                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     17354196                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total              18248720                       # Type of FU issued
+system.cpu1.iq.rate                          0.560652                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    4106129                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.225009                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          72403468                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         20371628                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     17886914                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes                 2                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              21687372                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses              22354825                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           71019                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           72854                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       284912                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          435                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         8471                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       200526                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       302030                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          600                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         8546                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       208715                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        36020                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        53245                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        35721                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        53336                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                213403                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 522979                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               149253                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           18243784                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles                220084                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 521586                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               152596                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           18819577                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              3681622                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             3198899                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            268198                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  4775                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               139704                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          8471                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         19696                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect        91512                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              111208                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             17534609                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              3585774                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           154586                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts              3780648                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             3305194                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            269579                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  5003                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               142623                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          8546                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         21067                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        96357                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              117424                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             18070032                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              3674514                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           162831                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                         5882                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     6645326                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 2522938                       # Number of branches executed
-system.cpu1.iew.exec_stores                   3059552                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.546373                       # Inst execution rate
-system.cpu1.iew.wb_sent                      17440127                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     17354196                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  8664228                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 13427268                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.540751                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.645271                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        1321053                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         469680                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           104293                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     30960244                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.541417                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.301399                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                         6014                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     6835502                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 2611240                       # Number of branches executed
+system.cpu1.iew.exec_stores                   3160988                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.555162                       # Inst execution rate
+system.cpu1.iew.wb_sent                      17973633                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     17886914                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  8930641                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 13891389                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.549537                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.642890                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        1385631                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         474020                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           110400                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     31408226                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.549763                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.309086                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     22892252     73.94%     73.94% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      4806577     15.52%     89.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1404802      4.54%     94.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       524965      1.70%     95.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       440442      1.42%     97.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       285091      0.92%     98.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       183452      0.59%     98.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7        97903      0.32%     98.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       324760      1.05%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     23101421     73.55%     73.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      4945584     15.75%     89.30% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1441278      4.59%     93.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       545057      1.74%     95.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       459061      1.46%     97.08% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       290803      0.93%     98.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       192288      0.61%     98.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       102090      0.33%     98.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       330644      1.05%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     30960244                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            13688085                       # Number of instructions committed
-system.cpu1.commit.committedOps              16762412                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     31408226                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            14103243                       # Number of instructions committed
+system.cpu1.commit.committedOps              17267080                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       6395083                       # Number of memory references committed
-system.cpu1.commit.loads                      3396710                       # Number of loads committed
-system.cpu1.commit.membars                     189727                       # Number of memory barriers committed
-system.cpu1.commit.branches                   2413565                       # Number of branches committed
+system.cpu1.commit.refs                       6575097                       # Number of memory references committed
+system.cpu1.commit.loads                      3478618                       # Number of loads committed
+system.cpu1.commit.membars                     192402                       # Number of memory barriers committed
+system.cpu1.commit.branches                   2497510                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 14968527                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              408976                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 15405118                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              417187                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        10339164     61.68%     61.68% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          24981      0.15%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         3184      0.02%     61.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        3396710     20.26%     82.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       2998373     17.89%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        10663290     61.76%     61.76% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          25529      0.15%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.90% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3164      0.02%     61.92% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.92% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.92% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.92% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        3478618     20.15%     82.07% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       3096479     17.93%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         16762412                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               324760                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    47828529                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   36474807                       # The number of ROB writes
-system.cpu1.timesIdled                          47199                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         816455                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5622120065                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   13685021                       # Number of Instructions Simulated
-system.cpu1.committedOps                     16759348                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.345100                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.345100                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.426421                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.426421                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                19625898                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               11372751                       # number of integer regfile writes
-system.cpu1.cc_regfile_reads                 63035720                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                 5356524                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads               45569068                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                348886                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           147018                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          469.878055                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            5728782                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           147355                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            38.877418                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     104643213000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.878055                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.917731                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.917731                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          334                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.658203                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12638529                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12638529                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3017876                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3017876                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2482754                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2482754                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41945                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        41945                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69025                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        69025                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61066                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        61066                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5500630                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5500630                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5542575                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5542575                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       174243                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       174243                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       312530                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       312530                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23398                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        23398                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17766                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17766                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23154                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23154                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       486773                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        486773                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       510171                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       510171                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3329111500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3329111500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11702941948                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  11702941948                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    365873000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    365873000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    624012000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    624012000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1848000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1848000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  15032053448                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  15032053448                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  15032053448                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  15032053448                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3192119                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3192119                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2795284                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2795284                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        65343                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        65343                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86791                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        86791                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84220                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        84220                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      5987403                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      5987403                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6052746                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6052746                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.054585                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.054585                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111806                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.111806                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.358080                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.358080                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.204699                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.204699                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274923                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274923                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.081300                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.081300                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.084288                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.084288                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19106.141997                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 19106.141997                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37445.819435                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 37445.819435                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20593.999775                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20593.999775                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26950.505312                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26950.505312                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total         17267080                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               330644                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    48838333                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   37625273                       # The number of ROB writes
+system.cpu1.timesIdled                          48215                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         812805                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5641687887                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   14100179                       # Number of Instructions Simulated
+system.cpu1.committedOps                     17264016                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.308417                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.308417                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.433197                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.433197                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                20251179                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               11682425                       # number of integer regfile writes
+system.cpu1.cc_regfile_reads                 64899787                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                 5579511                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads               46382322                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                351060                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           151453                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          475.445915                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5884950                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           151796                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            38.768808                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      94652365000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   475.445915                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.928605                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.928605                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          343                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.669922                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12967805                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12967805                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3097715                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3097715                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2551654                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2551654                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42598                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        42598                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69930                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        69930                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61845                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61845                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5649369                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5649369                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5691967                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5691967                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       178499                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       178499                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       318856                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       318856                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23937                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        23937                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17809                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17809                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23272                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23272                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       497355                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        497355                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       521292                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       521292                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3304865000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3304865000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11283001947                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  11283001947                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    363785500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    363785500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    633675000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    633675000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1492000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1492000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  14587866947                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  14587866947                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  14587866947                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  14587866947                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3276214                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3276214                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2870510                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2870510                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66535                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        66535                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        87739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85117                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        85117                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6146724                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6146724                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6213259                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6213259                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.054483                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.054483                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111080                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.111080                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.359766                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.359766                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.202977                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.202977                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.273412                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.273412                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.080914                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.080914                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.083900                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.083900                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18514.753584                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 18514.753584                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35385.885625                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 35385.885625                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20427.059352                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20427.059352                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27229.073565                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27229.073565                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30881.033763                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 30881.033763                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29464.735252                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 29464.735252                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          465                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1794947                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               35                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          29761                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    13.285714                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    60.312053                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       147018                       # number of writebacks
-system.cpu1.dcache.writebacks::total           147018                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        60609                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        60609                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       234531                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       234531                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12556                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12556                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       295140                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       295140                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       295140                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       295140                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       113634                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       113634                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        77999                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        77999                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        22718                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        22718                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5210                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5210                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23154                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23154                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       191633                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       191633                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       214351                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       214351                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3075                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3075                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2419                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2419                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5494                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5494                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1698407500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1698407500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2883249956                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2883249956                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    419765000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    419765000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    102736000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    102736000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    600876000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    600876000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1830000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1830000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4581657456                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4581657456                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5001422456                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5001422456                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    438427500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    438427500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    301840000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    301840000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    740267500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    740267500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035598                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035598                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027904                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027904                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.347673                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.347673                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060029                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060029                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274923                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274923                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032006                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.032006                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035414                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035414                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14946.296883                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14946.296883                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36965.216939                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36965.216939                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.198697                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18477.198697                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19719.001919                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19719.001919                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25951.282716                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25951.282716                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29330.894325                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 29330.894325                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27984.060655                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 27984.060655                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          243                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1664555                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          30437                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.571429                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    54.688537                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks       151454                       # number of writebacks
+system.cpu1.dcache.writebacks::total           151454                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        61419                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        61419                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       240138                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       240138                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12559                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12559                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       301557                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       301557                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       301557                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       301557                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       117080                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       117080                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78718                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        78718                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23077                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        23077                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5250                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5250                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23272                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23272                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       195798                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       195798                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       218875                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       218875                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3052                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3052                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2407                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2407                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5459                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5459                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1724704000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1724704000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2823186957                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2823186957                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    411595000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    411595000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     99724500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     99724500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    610417000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    610417000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1478000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1478000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4547890957                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4547890957                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4959485957                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4959485957                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    433858500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    433858500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    433858500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    433858500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035736                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035736                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027423                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027423                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.346840                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.346840                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059837                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.059837                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.273412                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.273412                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031854                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031854                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035227                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035227                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14730.987359                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14730.987359                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35864.566643                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35864.566643                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17835.723881                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17835.723881                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18995.142857                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18995.142857                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26229.675146                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26229.675146                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23908.499350                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23908.499350                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23332.862716                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23332.862716                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142578.048780                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142578.048780                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124778.834229                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124778.834229                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134741.081179                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134741.081179                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           532644                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.385087                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            6412298                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           533156                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            12.027058                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      79429210500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.385087                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975361                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975361                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23227.463799                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23227.463799                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22658.987810                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22658.987810                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142155.471822                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142155.471822                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79475.819747                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79475.819747                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.replacements           550819                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.430777                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6572284                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           551331                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            11.920759                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      79423447000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.430777                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975451                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975451                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          494                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          493                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         14462114                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        14462114                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      6412298                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        6412298                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      6412298                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         6412298                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      6412298                       # number of overall hits
-system.cpu1.icache.overall_hits::total        6412298                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       552179                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       552179                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       552179                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        552179                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       552179                       # number of overall misses
-system.cpu1.icache.overall_misses::total       552179                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5065871620                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5065871620                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5065871620                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5065871620                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5065871620                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5065871620                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      6964477                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      6964477                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      6964477                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      6964477                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      6964477                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      6964477                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.079285                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.079285                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.079285                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.079285                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.079285                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.079285                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9174.328651                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9174.328651                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9174.328651                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9174.328651                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9174.328651                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9174.328651                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       470749                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          422                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            34696                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.567818                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets   105.500000                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       532644                       # number of writebacks
-system.cpu1.icache.writebacks::total           532644                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19019                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        19019                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        19019                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        19019                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        19019                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        19019                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       533160                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       533160                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       533160                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       533160                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       533160                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       533160                       # number of overall MSHR misses
+system.cpu1.icache.tags.tag_accesses         14837444                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14837444                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6572284                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6572284                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6572284                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6572284                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6572284                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6572284                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       570771                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       570771                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       570771                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        570771                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       570771                       # number of overall misses
+system.cpu1.icache.overall_misses::total       570771                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5205454773                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5205454773                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5205454773                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5205454773                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5205454773                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5205454773                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      7143055                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      7143055                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      7143055                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      7143055                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      7143055                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      7143055                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.079906                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.079906                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.079906                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.079906                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.079906                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.079906                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9120.040740                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9120.040740                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9120.040740                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9120.040740                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9120.040740                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9120.040740                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       475905                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          114                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            36443                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.058886                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          114                       # average number of cycles each access was blocked
+system.cpu1.icache.writebacks::writebacks       550819                       # number of writebacks
+system.cpu1.icache.writebacks::total           550819                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19437                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        19437                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        19437                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        19437                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        19437                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        19437                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       551334                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       551334                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       551334                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       551334                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       551334                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       551334                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          102                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          102                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4631400380                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4631400380                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4631400380                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4631400380                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4631400380                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4631400380                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13655000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13655000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13655000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     13655000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.076554                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.076554                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.076554                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.076554                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.076554                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.076554                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8686.698890                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8686.698890                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8686.698890                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8686.698890                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8686.698890                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8686.698890                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133872.549020                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133872.549020                       # average overall mshr uncacheable latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       119604                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       120343                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          669                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4760291519                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4760291519                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4760291519                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4760291519                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4760291519                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4760291519                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13829000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13829000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13829000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     13829000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.077185                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.077185                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.077185                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.077185                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.077185                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.077185                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8634.133790                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8634.133790                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8634.133790                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8634.133790                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8634.133790                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8634.133790                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135578.431373                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135578.431373                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135578.431373                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       116080                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       116662                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          527                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        49745                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           36294                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15213.941609                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1184366                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           51460                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           23.015274                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        50226                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           32901                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15108.183095                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1229209                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           48015                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           25.600521                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14744.109202                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    10.751628                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     4.727886                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   454.352894                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.899909                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000656                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000289                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.027731                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.928585                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          946                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           64                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14156                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            7                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          620                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          319                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           10                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14647.178223                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     9.951767                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.912776                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   448.140330                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.893993                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000607                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000178                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.027352                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.922130                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          986                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           56                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14072                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          621                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          357                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           22                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          800                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2726                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10630                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.057739                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003906                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.864014                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        23534667                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       23534667                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        11642                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         5450                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         17092                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks        91128                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total        91128                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       577481                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       577481                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        16562                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        16562                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       522608                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       522608                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        77065                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        77065                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        11642                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         5450                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       522608                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data        93627                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         633327                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        11642                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         5450                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       522608                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data        93627                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        633327                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          472                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          270                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          742                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29194                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29194                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23153                       # number of SCUpgradeReq misses
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-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32879                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        32879                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        10546                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        10546                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        64491                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        64491                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          472                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          270                       # number of demand (read+write) misses
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-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          472                       # number of overall misses
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-system.cpu1.l2cache.overall_misses::total       108658                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10388000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5548000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     15936000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     61302500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     61302500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     60199500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     60199500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1803000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1803000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1873781500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1873781500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    637936000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    637936000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1490442997                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1490442997                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10388000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5548000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    637936000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3364224497                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10388000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5548000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    637936000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3364224497                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4018096497                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        12114                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         5720                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        17834                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks        91128                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total        91128                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       577481                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       577481                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29194                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29194                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23153                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23153                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadExReq_accesses::total        49441                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       533154                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       533154                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       141556                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       141556                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        12114                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.demand_accesses::cpu1.data       190997                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       741985                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        12114                       # number of overall (read+write) accesses
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-system.cpu1.l2cache.overall_accesses::cpu1.data       190997                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       741985                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038963                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.047203                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.041606                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          780                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2641                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10651                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.060181                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003418                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.858887                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        24271230                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       24271230                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        12198                       # number of ReadReq hits
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+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29202                       # number of UpgradeReq misses
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+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     66927000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     66927000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     66665000                       # number of SCUpgradeReq miss cycles
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+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1457000                       # number of SCUpgradeFailReq miss cycles
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+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1788683500                       # number of ReadExReq miss cycles
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+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    627007000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    627007000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1473931999                       # number of ReadSharedReq miss cycles
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+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10024000                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3262615499                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3905082999                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        12644                       # number of ReadReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_accesses::total        18519                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks        93872                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total        93872                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       597157                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       597157                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29202                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29202                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23272                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23272                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50161                       # number of ReadExReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       551333                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       551333                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       145401                       # number of ReadSharedReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.035274                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.045106                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.038393                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000002                       # miss rate for WritebackClean accesses
+system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000002                       # miss rate for WritebackClean accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.665015                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.665015                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.019780                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.019780                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.455586                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.455586                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038963                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.047203                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.019780                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.509799                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.146442                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038963                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.047203                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.019780                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.509799                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.146442                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22008.474576                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20548.148148                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21477.088949                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2099.832157                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2099.832157                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2600.073425                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2600.073425                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1803000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1803000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56990.221722                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56990.221722                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60490.802200                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60490.802200                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23110.868137                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23110.868137                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.474576                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20548.148148                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60490.802200                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34550.934549                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 36979.297401                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22008.474576                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20548.148148                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60490.802200                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34550.934549                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 36979.297401                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999957                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999957                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.651143                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.651143                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018851                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018851                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.443553                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.443553                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.035274                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.045106                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018851                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.496799                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.141438                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.035274                       # miss rate for overall accesses
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+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018851                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.496799                       # miss rate for overall accesses
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+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22475.336323                       # average ReadReq miss latency
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+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2291.863571                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2864.724335                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2864.724335                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 54763.440696                       # average ReadExReq miss latency
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+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60329.741172                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60329.741172                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22854.139193                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22854.139193                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22475.336323                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20515.094340                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60329.741172                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33581.550090                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 36071.670706                       # average overall miss latency
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+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20515.094340                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60329.741172                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33581.550090                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 36071.670706                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          182                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    60.666667                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.unused_prefetches             518                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks        29343                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           29343                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1270                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         1270                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           29                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           29                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1299                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         1302                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            3                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1299                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1302                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          472                       # number of ReadReq MSHR misses
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-system.cpu1.l2cache.HardPFReq_mshr_misses::total        21229                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29194                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29194                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23153                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23153                       # number of SCUpgradeReq MSHR misses
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-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31609                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31609                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        10543                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        10543                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        64462                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        64462                       # number of ReadSharedReq MSHR misses
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-system.cpu1.l2cache.demand_mshr_misses::cpu1.data        96071                       # number of demand (read+write) MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        10543                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        96071                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total       128585                       # number of overall MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3075                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3177                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2419                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2419                       # number of WriteReq MSHR uncacheable
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 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5494                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5596                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7556000                       # number of ReadReq MSHR miss cycles
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-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1356296825                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    583735000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    583735000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    426936499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    426936499                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1695000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1581842500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1581842500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    574617500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    574617500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1102358997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1102358997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7556000                       # number of demand (read+write) MSHR miss cycles
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-system.cpu1.l2cache.demand_mshr_miss_latency::total   3270302997                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7556000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3928000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    574617500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2684201497                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total   4626599822                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12890000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    413788000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    426678000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    283458994                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    283458994                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12890000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    697246994                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    710136994                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038963                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.047203                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.041606                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5459                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5561                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7348000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3846500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11194500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1151290913                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1151290913                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    600355000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    600355000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    435611000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    435611000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1373000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1373000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1514716000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1514716000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    564636500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    564636500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1085937999                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1085937999                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7348000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3846500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    564636500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2600653999                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3176484999                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7348000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3846500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    564636500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2600653999                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1151290913                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4327775912                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13064000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    409389000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    422453000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13064000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    409389000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    422453000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.035274                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.045106                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.038393                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for WritebackClean accesses
+system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000002                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.639328                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.639328                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019775                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.019775                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.455382                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.455382                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038963                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.047203                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.019775                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.502997                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.144688                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038963                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.047203                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.019775                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.502997                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999957                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999957                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.631148                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.631148                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018847                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018847                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.443346                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.443346                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.035274                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.045106                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018847                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.491517                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.140086                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.035274                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.045106                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018847                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.491517                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.173299                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15477.088949                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63888.870178                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19995.033226                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19995.033226                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18439.791776                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18439.791776                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1695000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1695000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50044.053909                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50044.053909                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54502.276392                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54502.276392                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17100.912119                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17100.912119                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54502.276392                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27939.768473                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30462.228446                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54502.276392                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27939.768473                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35980.867302                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134565.203252                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134302.171860                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117180.237288                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117180.237288                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126910.628686                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126900.820944                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1463686                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       739552                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11057                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       170999                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       169235                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1764                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         24298                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       736701                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2419                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2419                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       121677                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       588534                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        90826                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        26224                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        69999                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41335                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        85194                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        56383                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        54101                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       533160                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       217797                       # Transaction distribution
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.165930                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15744.725738                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58201.855973                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20558.694610                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20558.694610                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18719.049461                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18719.049461                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47844.720301                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47844.720301                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54338.995284                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54338.995284                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16845.911593                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16845.911593                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54338.995284                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27055.762458                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29624.757508                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16475.336323                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14515.094340                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54338.995284                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27055.762458                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58201.855973                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34075.634125                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134137.942333                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133941.978440                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128078.431373                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 74993.405386                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75967.092250                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1509011                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       762131                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11245                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       172130                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       169820                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2310                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         24888                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       759622                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2407                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2407                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       121244                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       608400                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        89967                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        23852                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        71187                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41516                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85044                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           30                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        57431                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        54716                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       551334                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       224940                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateReq           24                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1599162                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       719912                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        12717                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        26238                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2358029                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     68212704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24362994                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        22880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        48456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          92647034                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     368307                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1093026                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.175061                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.384243                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1653690                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       733597                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        12997                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        27256                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2427540                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     70539360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24952640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        23500                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          95566076                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     366639                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1114936                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.173156                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.383819                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0            903444     82.66%     82.66% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            187818     17.18%     99.84% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              1764      0.16%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0            924188     82.89%     82.89% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            188438     16.90%     99.79% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              2310      0.21%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1093026                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1422321490                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1114936                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1467946497                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     79991516                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     80180559                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    799908367                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    827154896                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    318043852                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    324971252                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      6997998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      7123996                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     14133980                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     14622978                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31018                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31018                       # Transaction distribution
@@ -2881,33 +2833,33 @@ system.iobus.pkt_size_system.bridge.master::total       162812
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40405500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             40401000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               112500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               323000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               323500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                89000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               574500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               585000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               22000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
@@ -2915,25 +2867,25 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6085500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6085000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            34122000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34109000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187170938                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187090970                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.550737                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.555535                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256092273000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.550737                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.909421                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.909421                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         256148567000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.555535                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909721                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909721                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2943,26 +2895,26 @@ system.iocache.ReadReq_misses::realview.ide          252                       #
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          252                       # number of overall misses
-system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32570877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32570877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4577184061                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4577184061                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32570877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32570877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32570877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32570877                       # number of overall miss cycles
+system.iocache.demand_misses::realview.ide        36476                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36476                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36476                       # number of overall misses
+system.iocache.overall_misses::total            36476                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     32635877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32635877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4576397093                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4576397093                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4609032970                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4609032970                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4609032970                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4609032970                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36476                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36476                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36476                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36476                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2971,40 +2923,38 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129249.511905                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129249.511905                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126357.775536                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126357.775536                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129249.511905                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129249.511905                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129249.511905                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129249.511905                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 129507.448413                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 129507.448413                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126336.050491                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126336.050491                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126357.960577                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126357.960577                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126357.960577                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126357.960577                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             2                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            2                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36206                       # number of writebacks
 system.iocache.writebacks::total                36206                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          252                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          252                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          252                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19970877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19970877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2764245413                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2764245413                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19970877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19970877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19970877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19970877                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36476                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36476                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36476                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36476                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     20035877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     20035877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2763475432                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2763475432                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2783511309                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2783511309                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2783511309                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2783511309                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -3013,604 +2963,590 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79249.511905                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79249.511905                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76309.778407                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76309.778407                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 79249.511905                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 79249.511905                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 79249.511905                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 79249.511905                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   130481                       # number of replacements
-system.l2c.tags.tagsinuse                63162.524815                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     437656                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   194611                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.248876                       # Average number of references to valid blocks.
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79507.448413                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 79507.448413                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76288.522306                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76288.522306                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76310.760747                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76310.760747                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76310.760747                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76310.760747                       # average overall mshr miss latency
+system.l2c.tags.replacements                   125494                       # number of replacements
+system.l2c.tags.tagsinuse                63202.959531                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     439435                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   189556                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.318233                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   13531.746388                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    17.289436                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     1.065903                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8160.706658                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2775.310647                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33971.574296                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     4.602927                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909521                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1734.289932                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      612.780861                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2352.248246                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.206478                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000070                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.576740                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.910038                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1686.284360                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        33327                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          127                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5989                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        24666                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          626                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4321                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        28334                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.469711                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000305                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.508530                       # Percentage of cache occupancy per task id
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-system.l2c.tags.data_accesses                 6042349                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       262546                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          262546                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           32542                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            2076                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               34618                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2163                       # number of SCUpgradeReq hits
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-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          186                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu0.data        48429                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        46477                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu1.inst         7717                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data         5261                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3686                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           146069                       # number of ReadSharedReq hits
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-system.l2c.demand_hits::total                  150938                       # number of demand (read+write) hits
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-system.l2c.UpgradeReq_misses::cpu0.data          9567                       # number of UpgradeReq misses
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-system.l2c.UpgradeReq_misses::total             11783                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          708                       # number of SCUpgradeReq misses
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+system.l2c.ReadSharedReq_misses::total         170988                       # number of ReadSharedReq misses
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 system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2825                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              9842                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         6993                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                194884                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           28                       # number of overall misses
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-system.l2c.overall_misses::cpu0.inst            19538                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            20938                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       134710                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker            6                       # number of overall misses
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+system.l2c.demand_misses::cpu1.l2cache.prefetcher         5822                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                190554                       # number of demand (read+write) misses
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+system.l2c.overall_misses::cpu0.data            20423                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       132775                       # number of overall misses
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 system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2825                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             9842                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher         6993                       # number of overall misses
-system.l2c.overall_misses::total               194884                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data     21715500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      4407500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     26123000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      5011500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2024500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      7036000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1773470500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1179481000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   2952951500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      4090000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       388000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2590822501                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data   1287354500                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       838000                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.data    152189500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1275537407                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  27002299072                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      4090000                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu1.dtb.walker       838000                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::total     29955250572                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      4090000                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu1.dtb.walker       838000                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu1.data   1331670500                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total    29955250572                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       262546                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       262546                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data         4292                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           46401                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         2871                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::total          4883                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::cpu1.data         9804                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            25362                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          214                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       181187                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::total             345822                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.227196                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.516309                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.253938                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.246604                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.614811                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.398321                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.752667                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.895859                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.808020                       # miss rate for ReadExReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.160050                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.267976                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.167563                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::total     0.544190                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.130841                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.inst       0.267976                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.610394                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::total           0.563538                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.130841                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.030303                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.363836                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.285980                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.071429                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.267976                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.610394                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.563538                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2269.833804                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1988.944043                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2217.007553                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7078.389831                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1636.620857                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  3617.480720                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151449.231426                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134291.358306                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 144095.618016                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146071.428571                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132604.284011                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139505.255743                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139666.666667                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       132500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134307.079646                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143710.576015                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 154837.686991                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146071.428571                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 132604.284011                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 146185.165727                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139666.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker       132500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 134307.079646                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 135304.866897                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 153708.106217                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 146071.428571                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 132604.284011                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 146185.165727                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139666.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker       132500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 134307.079646                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 135304.866897                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 153708.106217                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              1429                       # number of cycles access was blocked
+system.l2c.overall_misses::cpu1.inst             2756                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             9251                       # number of overall misses
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+system.l2c.overall_misses::total               190554                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data     30450500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      6079500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     36530000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      4673500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3850000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      8523500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   1715723499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1100336500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2816059999                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      3865000                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2588066000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data   1270606500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  20899436571                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      1078000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker       146500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst    371480000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data    137505000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1077632372                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  26350342443                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      3865000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       526500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   2588066000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   2986329999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  20899436571                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      1078000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker       146500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    371480000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1237841500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1077632372                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     29166402442                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      3865000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       526500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   2588066000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   2986329999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  20899436571                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      1078000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker       146500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    371480000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1237841500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1077632372                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    29166402442                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       259619                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       259619                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        42823                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4476                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           47299                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2938                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2190                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          5128                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15270                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9634                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            24904                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          226                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           68                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        55956                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        58211                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       180144                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           36                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           12                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        10390                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data         5948                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8937                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       319928                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          226                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           68                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           55956                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           73481                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180144                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           36                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           12                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           10390                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           15582                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8937                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              344832                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          226                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           68                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          55956                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          73481                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180144                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           36                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           12                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          10390                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          15582                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8937                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             344832                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.235317                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.562779                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.266306                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.286249                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.603196                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.421607                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.739489                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.858833                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.785657                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.119469                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.058824                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.348256                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.156860                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.737049                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.222222                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.083333                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.265255                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.164257                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.651449                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.534458                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.119469                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.058824                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.348256                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.277936                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.737049                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.222222                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.083333                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.265255                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.593698                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.651449                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.552600                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.119469                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.058824                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.348256                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.277936                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.737049                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.222222                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.083333                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.265255                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.593698                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.651449                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.552600                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3021.782276                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2413.457721                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2900.127024                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5557.074911                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2914.458743                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  3942.414431                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151941.507173                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132987.249214                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 143926.198457                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143148.148148                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       131625                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132809.873249                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139153.050049                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       134750                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       146500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134789.550073                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140742.067554                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 154106.384325                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143148.148148                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker       131625                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 132809.873249                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 146223.865201                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       134750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker       146500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 134789.550073                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 133806.237164                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 153061.087366                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143148.148148                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker       131625                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 132809.873249                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 146223.865201                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157404.907332                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       134750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker       146500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 134789.550073                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 133806.237164                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185096.594297                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 153061.087366                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               270                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       10                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    142.900000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs            54                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              102119                       # number of writebacks
-system.l2c.writebacks::total                   102119                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           10                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           25                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             13                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 25                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            13                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                25                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3254                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3254                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9567                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2216                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11783                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          708                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1237                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1945                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11710                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8783                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         20493                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           28                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19528                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9226                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134710                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            6                       # number of ReadSharedReq MSHR misses
+system.l2c.writebacks::writebacks               98551                       # number of writebacks
+system.l2c.writebacks::total                    98551                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            3                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            7                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  7                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 7                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         2889                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         2889                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        10077                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2519                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        12596                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          841                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1321                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         2162                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11292                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8274                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19566                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           27                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            4                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19484                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9131                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       132775                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            8                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2812                       # number of ReadSharedReq MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    343998000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5796362003                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11053000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    358428504                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6509841507                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4693982535                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    242306006                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4936288541                       # number of WriteReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    343998000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10490344538                       # number of overall MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    600734510                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11446130048                       # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total   6509436006                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.227196                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.516309                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.253938                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.246604                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.614811                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.398321                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.752667                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.895859                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.808020                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.130841                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.030303                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.363650                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.160015                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.071429                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.266743                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.167563                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.544112                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.130841                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.030303                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.363650                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.285952                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.071429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.266743                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.610394                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.563466                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.130841                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.030303                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.363650                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.285952                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.071429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.266743                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.610394                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.563466                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72697.972196                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72196.525271                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72603.666299                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74620.056497                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73853.274050                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.390746                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141449.018360                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124290.790391                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 134095.252867                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122626.563959                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129515.337633                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124367.545164                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133709.634561                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144844.415396                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122626.563959                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136190.127532                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124367.545164                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125304.258789                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 143713.943682                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122626.563959                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136190.127532                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124367.545164                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125304.258789                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 143713.943682                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.235317                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.562779                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.266306                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.286249                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.603196                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.421607                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.739489                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.858833                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.785657                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.119469                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.058824                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.348202                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.156860                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.737049                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.222222                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.264870                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.164257                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.651449                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.534436                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.119469                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.058824                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.348202                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.277936                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.737049                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.222222                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.264870                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.593698                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.651449                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.552579                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.119469                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.058824                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.348202                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.277936                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.737049                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.222222                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.264870                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.593698                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.651449                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.552579                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72750.620224                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72427.947598                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72686.090822                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74677.170036                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73875.094625                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74187.095282                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141941.065267                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122986.164491                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 133925.484718                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       121625                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122815.183997                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129152.558208                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       124750                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       136500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124831.953125                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130740.024565                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144108.095461                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       121625                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122815.183997                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136223.400969                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       124750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       136500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124831.953125                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123805.051238                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 143062.511107                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133148.148148                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       121625                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122815.183997                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136223.400969                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147404.569482                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       124750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       136500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124831.953125                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123805.051238                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175093.604260                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 143062.511107                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182183.869845                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116675.945312                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171343.181823                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164706.920769                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100167.840430                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159657.433890                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182256.143737                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110068.627451                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116253.197770                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171409.205972                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173925.964321                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109403.480240                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 166100.187895                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               37993                       # Transaction distribution
-system.membus.trans_dist::ReadResp             212610                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30918                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30918                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       138325                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            16163                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            72828                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40466                       # Transaction distribution
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96170.510985                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110068.627451                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 64966.275660                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 94520.474037                       # average overall mshr uncacheable latency
+system.membus.trans_dist::ReadReq               37976                       # Transaction distribution
+system.membus.trans_dist::ReadResp             209208                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30892                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30892                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       134757                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            15369                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            74473                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40549                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40267                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            20420                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        174618                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39381                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19462                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        171233                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           36                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13740                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       656523                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       778231                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13654                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       645275                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       766897                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72949                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72949                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 851180                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839846                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19049928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19240508                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27308                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18543624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18734032                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21558652                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           119912                       # Total snoops (count)
-system.membus.snoop_fanout::samples            587818                       # Request fanout histogram
+system.membus.pkt_size::total                21052176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           120651                       # Total snoops (count)
+system.membus.snoop_fanout::samples            580873                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  587818    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  580873    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              587818                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81915500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              580873                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81906000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               24500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11626486                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11549500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1006913072                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           984548482                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1122228815                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1099659305                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1359881                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1332381                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3653,56 +3589,57 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       988623                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       533441                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       142864                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          21333                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        20424                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          909                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              37996                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            474339                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30918                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30918                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       400884                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          117322                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          107373                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         43404                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         150777                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50440                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50440                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       436359                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests       989892                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       534223                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       146584                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          20158                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        19282                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          876                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              37979                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            475706                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30892                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30892                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       394392                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          117024                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          109072                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43515                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         152587                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           30                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           30                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50322                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50322                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       437743                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1256848                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       266902                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1523750                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34918134                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4292486                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               39210620                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          443927                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           909712                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.336026                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.474459                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1265601                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       259494                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1525095                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35019900                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3939924                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               38959824                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          441873                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           907771                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.341587                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.476273                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 604934     66.50%     66.50% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 303869     33.40%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    909      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 598564     65.94%     65.94% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 308331     33.97%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    876      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             909712                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          874582688                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             907771                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          872211768                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           356119                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         652718656                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         658378956                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         208359113                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         205665017                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1876                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1873                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2727                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 9195b9140..1a957c7d0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.832863                       # Number of seconds simulated
-sim_ticks                                2832863135500                       # Number of ticks simulated
-final_tick                               2832863135500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                2832862976500                       # Number of ticks simulated
+final_tick                               2832862976500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115587                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140197                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2895087258                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 586016                       # Number of bytes of host memory used
-host_seconds                                   978.51                       # Real time elapsed on the host
-sim_insts                                   113102806                       # Number of instructions simulated
-sim_ops                                     137183832                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 118929                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144250                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2978848657                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 586012                       # Number of bytes of host memory used
+host_seconds                                   950.99                       # Real time elapsed on the host
+sim_insts                                   113100501                       # Number of instructions simulated
+sim_ops                                     137180951                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1320448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9385192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1320384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9384040                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10708200                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1320448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1320448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8027392                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10706984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1320384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1320384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8026368                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8044916                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8043892                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22879                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22878                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147146                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170083                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125428                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170064                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          125412                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129809                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               129793                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            429                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               466118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3312971                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               466095                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3312564                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3779992                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          466118                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466118                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2833667                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3779563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          466095                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             466095                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2833306                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2839853                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2833667                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2839492                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2833306                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           429                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              466118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3319156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              466095                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3318750                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6619845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170084                       # Number of read requests accepted
-system.physmem.writeReqs                       129809                       # Number of write requests accepted
-system.physmem.readBursts                      170084                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129809                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10877056                       # Total number of bytes read from DRAM
+system.physmem.bw_total::total                6619055                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170065                       # Number of read requests accepted
+system.physmem.writeReqs                       129793                       # Number of write requests accepted
+system.physmem.readBursts                      170065                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129793                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10875840                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      8320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8057984                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10708264                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8044916                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   8056896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10707048                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8043892                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                      130                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11273                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10987                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11172                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12956                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11272                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10588                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10986                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11169                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12952                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                9956                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10483                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10745                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10596                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10173                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10481                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10743                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10600                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10174                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              10343                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               9301                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10027                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11029                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10190                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10133                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8501                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7944                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8565                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10025                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11028                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10189                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10128                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8502                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7941                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8563                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                8669                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7612                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7608                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7365                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7701                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8000                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7958                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7699                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7999                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7959                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7673                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               7751                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6981                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7673                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8385                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7672                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8384                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7646                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7477                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832862903500                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832862744500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166532                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166513                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125428                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150650                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16386                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       724                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 125412                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150612                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       728                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -159,118 +159,117 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6620                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6367                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     6633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6951                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7619                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27                     7506                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1259                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                      366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       39                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61981                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      305.496459                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.645422                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.944153                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23140     37.33%     37.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14875     24.00%     61.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6518     10.52%     71.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3622      5.84%     77.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2531      4.08%     81.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1654      2.67%     84.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1506      2.43%     86.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1111      1.79%     88.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7024     11.33%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61981                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6159                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.593765                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      568.835471                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6158     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::35                      262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      120                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::57                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       58                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61915                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.784899                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.937223                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.895489                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23052     37.23%     37.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14889     24.05%     61.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6490     10.48%     71.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3653      5.90%     77.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2551      4.12%     81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1649      2.66%     84.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1497      2.42%     86.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1106      1.79%     88.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7028     11.35%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61915                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6142                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.666884                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      569.620654                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6141     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6159                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6159                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.442604                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.500292                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.099847                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5468     88.78%     88.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             102      1.66%     90.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.50%     90.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              55      0.89%     91.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              28      0.45%     92.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.32%     92.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              47      0.76%     93.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.19%     93.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             146      2.37%     95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              14      0.23%     96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.08%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              12      0.19%     96.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              62      1.01%     97.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.10%     97.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               7      0.11%     97.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              23      0.37%     98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              90      1.46%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.05%     99.56% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6142                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6142                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.496418                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.503929                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.596363                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5449     88.72%     88.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             115      1.87%     90.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              28      0.46%     91.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              44      0.72%     91.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              34      0.55%     92.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              18      0.29%     92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              53      0.86%     93.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               7      0.11%     93.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             141      2.30%     95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              11      0.18%     96.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.13%     96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.13%     96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              63      1.03%     97.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               7      0.11%     97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.13%     97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.41%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              94      1.53%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     99.56% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::96-99               1      0.02%     99.58% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::100-103             1      0.02%     99.59% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::104-107             1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.13%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.05%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             5      0.08%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6159                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2118470000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5305107500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849770000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12464.96                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.11%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             6      0.10%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.08%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6142                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2126742000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5313023250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849675000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12515.03                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31214.96                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31265.03                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
@@ -280,40 +279,40 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139692                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94186                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.19                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9446245.51                       # Average gap between requests
-system.physmem.pageHitRate                      79.05                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  242388720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  132255750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 687663600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                417033360                       # Energy for write commands per rank (pJ)
+system.physmem.avgWrQLen                        23.43                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139707                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94201                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.21                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9447347.56                       # Average gap between requests
+system.physmem.pageHitRate                      79.07                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  242207280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  132156750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 687546600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                416962080                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83434510665                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626525439500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896467659275                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.454308                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705731371250                       # Time in different power states
+system.physmem_0.actBackEnergy            83427429555                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626531651000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896466320945                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.453835                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705741524500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32529373750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32519220500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  226187640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  123415875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 637969800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                398837520                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  225870120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  123242625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 637938600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                398798640                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82104234975                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627692348000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896211361490                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.363834                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2707689162500                       # Time in different power states
+system.physmem_1.actBackEnergy            82153488960                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627649142750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896216849375                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.365771                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2707616089750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30578679500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30651593250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
@@ -333,19 +332,19 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46808005                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23978413                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1175283                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29454237                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13525326                       # Number of BTB hits
+system.cpu.branchPred.lookups                46806016                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23977735                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1175497                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29454915                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13525299                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             45.919798                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11724965                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              34889                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         7914908                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            7768670                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses           146238                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        60204                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             45.918649                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11724113                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              34916                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7913969                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            7767748                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           146221                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        60350                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -376,79 +375,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     72355                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                72355                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29395                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23194                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19766                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52589                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   463.728156                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2807.068133                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191        51286     97.52%     97.52% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383          905      1.72%     99.24% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575          316      0.60%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     72368                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72368                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29394                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23209                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19765                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52603                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   464.308119                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2802.300904                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191        51295     97.51%     97.51% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383          909      1.73%     99.24% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575          317      0.60%     99.84% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::24576-32767           38      0.07%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959           15      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151           23      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959           17      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151           21      0.04%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52589                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17730                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8394.043940                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17507     98.74%     98.74% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          217      1.22%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::total        52603                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17713                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8411.296807                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17487     98.72%     98.72% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          220      1.24%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17730                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131327621316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.619198                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.492781                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131267451816     99.95%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      41041000      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       8807000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6837500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1021000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       576000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1403500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       474000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::total        17713                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131327462316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.619046                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.492812                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131267362816     99.95%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      40987500      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       8789000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6827500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1022500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       578500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1418000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       467000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17         9500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131327621316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6380     82.61%     82.61% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1343     17.39%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7723                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72355                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131327462316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6375     82.60%     82.60% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1343     17.40%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7718                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72368                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72355                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7723                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72368                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7718                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7723                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        80078                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7718                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80086                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25411177                       # DTB read hits
-system.cpu.dtb.read_misses                      62688                       # DTB read misses
-system.cpu.dtb.write_hits                    19865478                       # DTB write hits
-system.cpu.dtb.write_misses                      9667                       # DTB write misses
+system.cpu.dtb.read_hits                     25410889                       # DTB read hits
+system.cpu.dtb.read_misses                      62740                       # DTB read misses
+system.cpu.dtb.write_hits                    19865162                       # DTB write hits
+system.cpu.dtb.write_misses                      9628                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       361                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.align_faults                       362                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                   2060                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1317                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25473865                       # DTB read accesses
-system.cpu.dtb.write_accesses                19875145                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1318                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25473629                       # DTB read accesses
+system.cpu.dtb.write_accesses                19874790                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45276655                       # DTB hits
-system.cpu.dtb.misses                           72355                       # DTB misses
-system.cpu.dtb.accesses                      45349010                       # DTB accesses
+system.cpu.dtb.hits                          45276051                       # DTB hits
+system.cpu.dtb.misses                           72368                       # DTB misses
+system.cpu.dtb.accesses                      45348419                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -478,58 +477,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     12837                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                12837                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3369                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7745                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore         1723                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11114                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   758.457801                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  3142.171422                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        10521     94.66%     94.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          120      1.08%     95.74% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          234      2.11%     97.85% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383          132      1.19%     99.04% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479           45      0.40%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                     12817                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                12817                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3368                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7731                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore         1718                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11099                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   753.896747                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  3151.109885                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        10511     94.70%     94.70% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191          118      1.06%     95.77% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          237      2.14%     97.90% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383          123      1.11%     99.01% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           46      0.41%     99.42% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671            4      0.04%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::53248-57343            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11114                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         5038                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12015.680826                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9674.005789                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7624.491394                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         4083     81.04%     81.04% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          936     18.58%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11099                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         5044                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12037.073751                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  9689.647863                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7634.465398                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         4079     80.87%     80.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          946     18.75%     99.62% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::32768-49151           16      0.32%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         5038                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23953376916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.632532                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.482296                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      8804085500     36.76%     36.76% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     15147384416     63.24%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2         1819000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total         5044                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  23953217916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.646337                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.478297                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      8473460000     35.38%     35.38% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     15477752916     64.62%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2         1917000      0.01%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::3           88000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23953376916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2980     89.89%     89.89% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           335     10.11%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3315                       # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total  23953217916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2992     89.96%     89.96% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           334     10.04%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3326                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12837                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        12837                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12817                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        12817                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3315                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3315                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        16152                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     65992511                       # ITB inst hits
-system.cpu.itb.inst_misses                      12837                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        16143                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     65995629                       # ITB inst hits
+system.cpu.itb.inst_misses                      12817                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -538,98 +537,98 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3079                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3089                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2160                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2166                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66005348                       # ITB inst accesses
-system.cpu.itb.hits                          65992511                       # DTB hits
-system.cpu.itb.misses                           12837                       # DTB misses
-system.cpu.itb.accesses                      66005348                       # DTB accesses
-system.cpu.numCycles                        278422079                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66008446                       # ITB inst accesses
+system.cpu.itb.hits                          65995629                       # DTB hits
+system.cpu.itb.misses                           12817                       # DTB misses
+system.cpu.itb.accesses                      66008446                       # DTB accesses
+system.cpu.numCycles                        278423951                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104965644                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184047232                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46808005                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33018961                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161470061                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6057656                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     190492                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8321                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        345001                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       554797                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  65991288                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1042618                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6254                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270563337                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.829471                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.217030                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104963925                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184057531                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46806016                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33017160                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161476606                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6057796                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     189442                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8697                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        337421                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       555442                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          188                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  65994399                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1047621                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6260                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270560619                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.829508                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217052                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171642539     63.44%     63.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29152189     10.77%     74.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14033587      5.19%     79.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55735022     20.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171637462     63.44%     63.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29152121     10.77%     74.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14032929      5.19%     79.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55738107     20.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270563337                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168119                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.661037                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77947938                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121878006                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64302075                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3866348                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2568970                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3407378                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total            270560619                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168111                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.661069                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77946486                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121877263                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64301274                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3866559                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2569037                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3407655                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                467954                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              156978056                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3511118                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2568970                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83705242                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11815574                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76555831                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62411209                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33506511                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146428655                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                918489                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                467718                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  65503                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  18531                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30749318                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150222579                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             676982359                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        163959933                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10887                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141740582                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8481991                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2839527                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2643996                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13883864                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26339284                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21214862                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1704584                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2138851                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143220356                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2117775                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143040703                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            261102                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8154295                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14292577                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         121903                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270563337                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.528677                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865235                       # Number of insts issued each cycle
+system.cpu.decode.DecodedInsts              156976144                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3511593                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2569037                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83703987                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11810773                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76556801                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62410429                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33509592                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146427061                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                918712                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                467058                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  65507                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  18530                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30752508                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150221263                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             676972712                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        163957736                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10899                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141737618                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8483639                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2839333                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2643784                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13883095                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26339486                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21214202                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1704469                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2149070                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143218821                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2117732                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143038678                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            260968                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8155598                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14296072                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         121861                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270560619                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528675                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865256                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182376042     67.41%     67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45230245     16.72%     84.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31877858     11.78%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10262059      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              817100      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182379690     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45219626     16.71%     84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31881926     11.78%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10262341      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              817003      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -637,44 +636,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270563337                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270560619                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7341205     32.76%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     32      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5622623     25.09%     57.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9446888     42.15%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7341670     32.77%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5623214     25.10%     57.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9441955     42.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95846012     67.01%     67.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               114315      0.08%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95844496     67.01%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               114325      0.08%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
@@ -698,98 +697,98 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8579      0.01%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8580      0.01%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26129650     18.27%     85.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            20939810     14.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26129578     18.27%     85.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20939362     14.64%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143040703                       # Type of FU issued
-system.cpu.iq.rate                           0.513755                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22410748                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156674                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579280960                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         153497939                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    139990284                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35633                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11369                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165425721                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23393                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323902                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143038678                       # Type of FU issued
+system.cpu.iq.rate                           0.513744                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22406871                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156649                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579270173                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153497654                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    139987851                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35641                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13126                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11370                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165419813                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23399                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323906                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1435157                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          717                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18681                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       624055                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1435915                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          710                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18680                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       623667                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88621                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6303                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88637                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6231                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2568970                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1238473                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                546153                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145518660                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2569037                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1239960                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                546279                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145517187                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26339284                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21214862                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1094251                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17896                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                509714                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18681                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         277446                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471378                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               748824                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142140939                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25734314                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            827514                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26339486                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21214202                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1094236                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17880                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                509843                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18680                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         277456                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471588                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               749044                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142138491                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25734027                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            827925                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        180529                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46562087                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26490837                       # Number of branches executed
-system.cpu.iew.exec_stores                   20827773                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510523                       # Inst execution rate
-system.cpu.iew.wb_sent                      141772110                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140001653                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63237844                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95709593                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502840                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660726                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7370888                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995872                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            715425                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267671554                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.513087                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.118264                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        180634                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46561433                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26490215                       # Number of branches executed
+system.cpu.iew.exec_stores                   20827406                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510511                       # Inst execution rate
+system.cpu.iew.wb_sent                      141769563                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     139999221                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63237138                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95708451                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.502828                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660727                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7372199                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995871                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            715636                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267668720                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.513081                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.118378                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194234773     72.56%     72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43288369     16.17%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15457266      5.77%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4372596      1.63%     96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6412647      2.40%     98.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1623966      0.61%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       797879      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       412108      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1071950      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194241015     72.57%     72.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43280699     16.17%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15455980      5.77%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4372366      1.63%     96.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6407128      2.39%     98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1628567      0.61%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       798347      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412274      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1072344      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267671554                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113257711                       # Number of instructions committed
-system.cpu.commit.committedOps              137338737                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267668720                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113255406                       # Number of instructions committed
+system.cpu.commit.committedOps              137335856                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45494934                       # Number of memory references committed
-system.cpu.commit.loads                      24904127                       # Number of loads committed
+system.cpu.commit.refs                       45494106                       # Number of memory references committed
+system.cpu.commit.loads                      24903571                       # Number of loads committed
 system.cpu.commit.membars                      814876                       # Number of memory barriers committed
-system.cpu.commit.branches                   26024432                       # Number of branches committed
+system.cpu.commit.branches                   26023568                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120166310                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4884393                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120163713                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4884102                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91722407     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91720354     66.79%     66.79% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          112817      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
@@ -818,36 +817,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc         8579      0.01%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24904127     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20590807     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24903571     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20590535     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137338737                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1071950                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389122780                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292297911                       # The number of ROB writes
-system.cpu.timesIdled                          890833                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7858742                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387304193                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113102806                       # Number of Instructions Simulated
-system.cpu.committedOps                     137183832                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.461673                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.461673                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.406228                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.406228                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155527774                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88490353                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9528                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137335856                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1072344                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389119867                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292294903                       # The number of ROB writes
+system.cpu.timesIdled                          890799                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7863332                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387302003                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113100501                       # Number of Instructions Simulated
+system.cpu.committedOps                     137180951                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.461739                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.461739                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.406217                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.406217                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155524958                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88488761                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9529                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502164450                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53130606                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               347857043                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521711                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            838824                       # number of replacements
+system.cpu.cc_regfile_reads                 502156058                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53129749                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               347863698                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521708                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            838747                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.925928                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40057266                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            839336                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.724947                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            40056709                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839259                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.728662                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.925928                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
@@ -857,268 +856,259 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          131
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179127418                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179127418                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23264892                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23264892                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15542105                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15542105                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345700                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345700                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441341                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441341                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         179125101                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179125101                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23264147                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23264147                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15542285                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15542285                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345698                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345698                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441334                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441334                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       460350                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       460350                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38806997                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38806997                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39152697                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39152697                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       704654                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        704654                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3607879                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3607879                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177723                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177723                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27366                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27366                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_hits::cpu.data      38806432                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38806432                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39152130                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39152130                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       705134                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        705134                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3607427                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3607427                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177712                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177712                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        27363                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        27363                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4312533                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4312533                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4490256                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4490256                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11719889500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11719889500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232482188697                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232482188697                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376930500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    376930500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      4312561                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4312561                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4490273                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4490273                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11711380000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11711380000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 232487777697                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 232487777697                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376699000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    376699000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       276000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       276000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244202078197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244202078197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244202078197                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244202078197                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23969546                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23969546                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19149984                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19149984                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523423                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523423                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468707                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468707                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 244199157697                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 244199157697                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 244199157697                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 244199157697                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23969281                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23969281                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19149712                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19149712                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523410                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523410                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468697                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468697                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       460355                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       460355                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43119530                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43119530                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43642953                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43642953                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029398                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029398                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188401                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188401                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339540                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339540                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058386                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058386                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     43118993                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43118993                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43642403                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43642403                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029418                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029418                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188380                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188380                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339527                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339527                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058381                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058381                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102886                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102886                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16632.119452                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16632.119452                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64437.357433                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64437.357433                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13773.679018                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13773.679018                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100015                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100015                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102888                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102888                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16608.729688                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16608.729688                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64446.980548                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.728794                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.728794                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55200                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55200                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56626.135544                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56626.135544                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.889903                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54384.889903                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       869086                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56625.090682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56625.090682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.033598                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54384.033598                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       871366                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6856                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   126.615093                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.095391                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       696811                       # number of writebacks
-system.cpu.dcache.writebacks::total            696811                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       290488                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       290488                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307970                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3307970                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18888                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18888                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3598458                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3598458                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3598458                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3598458                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414166                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414166                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       696773                       # number of writebacks
+system.cpu.dcache.writebacks::total            696773                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       291027                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       291027                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307518                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3307518                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18885                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18885                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3598545                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3598545                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3598545                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3598545                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414107                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414107                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299909                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       299909                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119577                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119577                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119568                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119568                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8478                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total         8478                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       714075                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       714075                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       833652                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       833652                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       714016                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       714016                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       833584                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       833584                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6390908000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6390908000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19966536471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19966536471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1698802000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1698802000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    127413000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    127413000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6386388500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6386388500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19974009472                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19974009472                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1699913000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1699913000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    127031000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    127031000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       271000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       271000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26357444471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26357444471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28056246471                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28056246471                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276240500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276240500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075717451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075717451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11351957951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11351957951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017279                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017279                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26360397972                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26360397972                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28060310972                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28060310972                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276272000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276272000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6276272000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6276272000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017277                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017277                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015661                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015661                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228452                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228452                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228440                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228440                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018088                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018088                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016560                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016560                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019102                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019102                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15430.788621                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15430.788621                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66575.316083                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66575.316083                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14206.762170                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14206.762170                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15028.662420                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.662420                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016559                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016559                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019100                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019100                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15422.073281                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15422.073281                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66600.233644                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66600.233644                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.123311                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.123311                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14983.604624                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14983.604624                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54200                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54200                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36911.311096                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36911.311096                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33654.626236                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33654.626236                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.370073                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.370073                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.807722                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.807722                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193343.290374                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193343.290374                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1886159                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64010374                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1886671                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.927682                       # Average number of references to valid blocks.
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.replacements           1886245                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154077                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64013417                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1886757                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.927749                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       16319051500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154077                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          67874994                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         67874994                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64010374                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64010374                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64010374                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64010374                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64010374                       # number of overall hits
-system.cpu.icache.overall_hits::total        64010374                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1977910                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1977910                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1977910                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1977910                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1977910                       # number of overall misses
-system.cpu.icache.overall_misses::total       1977910                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28157815494                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28157815494                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28157815494                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28157815494                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28157815494                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28157815494                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     65988284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     65988284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     65988284                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     65988284                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     65988284                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     65988284                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029974                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029974                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029974                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029974                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029974                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029974                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.145979                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14236.145979                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14236.145979                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14236.145979                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5784                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          67878198                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         67878198                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64013417                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64013417                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64013417                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64013417                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64013417                       # number of overall hits
+system.cpu.icache.overall_hits::total        64013417                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1977977                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1977977                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1977977                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1977977                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1977977                       # number of overall misses
+system.cpu.icache.overall_misses::total       1977977                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28160163493                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28160163493                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28160163493                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28160163493                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28160163493                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28160163493                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     65991394                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total     65991394                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029973                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029973                       # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.850829                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14236.850829                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.850829                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14236.850829                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.850829                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14236.850829                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         6440                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               186                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               190                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    31.096774                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    33.894737                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1886159                       # number of writebacks
-system.cpu.icache.writebacks::total           1886159                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91199                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91199                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91199                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91199                       # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total        91199                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1886711                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1886711                       # number of ReadReq MSHR misses
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-system.cpu.icache.demand_mshr_misses::total      1886711                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1886711                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1886711                       # number of overall MSHR misses
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+system.cpu.icache.writebacks::total           1886245                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91172                       # number of ReadReq MSHR hits
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25184628997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25184628997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25184628997                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377605500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377605500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377605500                       # number of overall MSHR uncacheable cycles
@@ -1129,235 +1119,232 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028592
 system.cpu.icache.demand_mshr_miss_rate::total     0.028592                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028592                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.028592                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13348.429620                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13348.429620                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13348.429620                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.248861                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.248861                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96795                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65029.426786                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5006508                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162120                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.881495                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96776                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65028.780058                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5006507                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162101                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.885109                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49617.960434                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.737497                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.672901                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10365.912312                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5032.143644                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.757110                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.672900                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10369.952431                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5025.112172                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6695                       # Occupied blocks per task id
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
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 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2632000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       796000                       # number of demand (read+write) miss cycles
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 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2632000                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total        70222                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       696811                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       696811                       # number of WritebackDirty accesses(hits+misses)
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-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.979437                       # miss rate for UpgradeReq accesses
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        54000                       # average SCUpgradeReq miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
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-system.cpu.l2cache.writebacks::writebacks        89238                       # number of writebacks
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::total           25                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19886                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       148752                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168663                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19885                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       148734                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168644                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34132                       # number of ReadReq MSHR uncacheable
@@ -1367,145 +1354,140 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3003
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61717                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       736000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3178000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    184658000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    184658000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       735500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3177500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    184950500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    184950500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       211500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       211500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16248351500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16248351500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2434936503                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2434936503                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1655244000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1655244000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16255528500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16255528500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2436802003                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2436802003                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1652257000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1652257000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       736000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2434936503                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17903595500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20341710003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       735500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2436802003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17907785500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20347765003                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       736000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2434936503                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17903595500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20341710003                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       735500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2436802003                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17907785500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20347765003                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340067500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887116000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227183500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756897000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756897000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887147000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227214500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340067500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644013000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10984080500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5887147000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6227214500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000497                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000356                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.979437                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.979437                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.977706                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.977706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455860                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455860                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010540                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024422                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024422                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010539                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010539                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024401                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024401                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177221                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060318                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000497                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010539                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177216                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060313                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177221                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060318                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000497                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010539                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177216                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060313                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total       127120                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.996317                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.996317                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122583.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total       127100                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68021.515263                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68021.515263                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119902.529647                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119902.529647                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122444.760284                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125027.872196                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125027.872196                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119959.917496                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122544.732361                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122583.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122544.732361                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120655.137467                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.984580                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.143326                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172445.060721                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172445.060721                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181285.775113                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177974.958277                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5483816                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757778                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5483921                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757867                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44951                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops          378                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          378                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq         128774                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2557705                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557731                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       822252                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1886159                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       149793                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2772                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       822205                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1886245                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       149751                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2781                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2777                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1886711                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       542312                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2786                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297260                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297260                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1886805                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542244                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5665508                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2640654                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30972                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133892                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8471026                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241506672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98506345                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48452                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       232436                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          340293905                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      194298                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3054873                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.024677                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.155138                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5665772                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2640441                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30896                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133904                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8471013                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241517552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98498985                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       232368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          340297169                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      194360                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3054889                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.024700                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.155211                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2979489     97.53%     97.53% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              75384      2.47%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2979432     97.53%     97.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              75457      2.47%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3054873                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5401857499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3054889                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5401923998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       258877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834033066                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834168078                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1305567557                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1305452066                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      18867982                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18839481                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75841383                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75872379                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
@@ -1557,7 +1539,7 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43093000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             43093500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1567,9 +1549,9 @@ system.iobus.reqLayer3.occupancy                27500                       # La
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                93500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               649500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               652000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1591,11 +1573,11 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6154500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6160000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33075500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33076500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187134993                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187162988                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
@@ -1619,26 +1601,26 @@ system.iocache.ReadReq_misses::realview.ide          223                       #
 system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          223                       # number of overall misses
-system.iocache.overall_misses::total              223                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28155877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28155877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4550151116                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4550151116                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28155877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28155877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28155877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28155877                       # number of overall miss cycles
+system.iocache.demand_misses::realview.ide        36447                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36447                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36447                       # number of overall misses
+system.iocache.overall_misses::total            36447                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28153877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28153877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4551268111                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4551268111                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4579421988                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4579421988                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4579421988                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4579421988                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36447                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36447                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36447                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36447                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1647,40 +1629,38 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126259.538117                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126259.538117                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125611.503865                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125611.503865                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126259.538117                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126259.538117                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             4                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126250.569507                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126250.569507                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125642.339637                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125642.339637                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125646.061075                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125646.061075                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125646.061075                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125646.061075                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17005877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17005877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737535612                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2737535612                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17005877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17005877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17005877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17005877                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36447                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36447                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36447                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36447                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17003877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17003877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2738656099                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2738656099                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2755659976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2755659976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2755659976                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2755659976                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1689,65 +1669,64 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76259.538117                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76259.538117                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75572.427451                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75572.427451                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75607.319560                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75607.319560                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67504                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67490                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       125428                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7780                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4584                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       125412                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7777                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4588                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133644                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133644                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33373                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133639                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133639                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33359                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450558                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558073                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 631001                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 630948                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16435996                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16599385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16433756                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16597145                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18916505                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18914265                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              487                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402766                       # Request fanout histogram
+system.membus.snoop_fanout::samples            402739                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402766    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402739    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402766                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83667000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402739                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83678000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1740000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1737499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           876048370                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           875953366                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          978678250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          978576250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index a5289b78c..53535ebf9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.824845                       # Number of seconds simulated
-sim_ticks                                2824844934500                       # Number of ticks simulated
-final_tick                               2824844934500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                2824844935500                       # Number of ticks simulated
+final_tick                               2824844935500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 301884                       # Simulator instruction rate (inst/s)
-host_op_rate                                   366207                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6935241973                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 301818                       # Simulator instruction rate (inst/s)
+host_op_rate                                   366127                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6933711439                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 588164                       # Number of bytes of host memory used
-host_seconds                                   407.32                       # Real time elapsed on the host
-sim_insts                                   122962642                       # Number of instructions simulated
-sim_ops                                     149162643                       # Number of ops (including micro ops) simulated
+host_seconds                                   407.41                       # Real time elapsed on the host
+sim_insts                                   122962678                       # Number of instructions simulated
+sim_ops                                     149162687                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          192                       # Number of bytes read from this memory
@@ -139,7 +139,7 @@ system.physmem.perBankWrBursts::14               4129                       # Pe
 system.physmem.perBankWrBursts::15               3560                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2823278666500                       # Total gap between requests
+system.physmem.totGap                    2823278667500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -154,8 +154,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  68732                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     76464                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     20945                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     76462                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     20947                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                      2008                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                       532                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
@@ -202,13 +202,13 @@ system.physmem.wrQLenPdf::12                       65                       # Wh
 system.physmem.wrQLenPdf::13                       66                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       65                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::15                     1166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3770                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3831                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     3816                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     3963                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     3852                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                     4123                       # What write queue length does an incoming req see
@@ -232,38 +232,38 @@ system.physmem.wrQLenPdf::42                       60                       # Wh
 system.physmem.wrQLenPdf::43                       41                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                       42                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39182                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      275.494666                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.171776                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     307.907235                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16210     41.37%     41.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9497     24.24%     65.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3855      9.84%     75.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2019      5.15%     80.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        39183                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      275.487635                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     163.171837                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     307.896605                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16209     41.37%     41.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9498     24.24%     65.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3856      9.84%     75.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2020      5.16%     80.60% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639         1646      4.20%     84.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1042      2.66%     87.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1041      2.66%     87.46% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::768-895          570      1.45%     88.92% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023          566      1.44%     90.36% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151         3777      9.64%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39182                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39183                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          3537                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        28.251343                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::stdev      474.824507                       # Reads before turning the bus around for writes
@@ -301,12 +301,12 @@ system.physmem.wrPerTurnAround::112-115             1      0.03%     99.89% # Wr
 system.physmem.wrPerTurnAround::128-131             1      0.03%     99.92% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::144-147             3      0.08%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            3537                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1310108250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3184227000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     1310437500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3184556250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    499765000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13107.24                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       13110.54                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31857.24                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31860.54                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.26                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.27                       # Average system read bandwidth in MiByte/s
@@ -318,38 +318,38 @@ system.physmem.busUtilWrite                      0.01                       # Da
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        28.41                       # Average write queue length when enqueuing
 system.physmem.readRowHits                      80619                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     48864                       # Number of row buffer hits during writes
+system.physmem.writeRowHits                     48863                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   80.66                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  71.09                       # Row buffer hit rate for writes
 system.physmem.avgGap                     16727764.68                       # Average gap between requests
 system.physmem.pageHitRate                      76.76                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  156212280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   85094625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  156219840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   85098750                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                 402051000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                227525760                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           179782062720                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            73198076175                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1622869382250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1876720404810                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.445189                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2640467902750                       # Time in different power states
+system.physmem_0.actBackEnergy            73199813535                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1622867858250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1876720629855                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.445270                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2640465319000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     91913120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     20211500000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     20214084000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                  140003640                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                   76213500                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 377559000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                217734480                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           179782062720                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            72424788525                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1619952843000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1872971204865                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.534203                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2641599878750                       # Time in different power states
+system.physmem_1.actBackEnergy            72425693970                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1619952048750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1872971316060                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.534243                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2641598541500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     91913120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     19067953250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     19069290500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -404,11 +404,11 @@ system.cpu0.dtb.walker.walksShort                4956                       # Ta
 system.cpu0.dtb.walker.walkWaitTime::samples         4956                       # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::0           4956    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::total         4956                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples  57378110626                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.254713                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -14614977624    -25.47%    -25.47% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    71993088250    125.47%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  57378110626                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::samples  57378111376                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.254714                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -14615003624    -25.47%    -25.47% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    71993115000    125.47%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  57378111376                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walkPageSizes::4K         2714     66.86%     66.86% # Table walker page sizes translated
 system.cpu0.dtb.walker.walkPageSizes::1M         1345     33.14%    100.00% # Table walker page sizes translated
 system.cpu0.dtb.walker.walkPageSizes::total         4059                       # Table walker page sizes translated
@@ -421,9 +421,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4059
 system.cpu0.dtb.walker.walkRequestOrigin::total         9015                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12035285                       # DTB read hits
+system.cpu0.dtb.read_hits                    12035291                       # DTB read hits
 system.cpu0.dtb.read_misses                      4159                       # DTB read misses
-system.cpu0.dtb.write_hits                    9387276                       # DTB write hits
+system.cpu0.dtb.write_hits                    9387286                       # DTB write hits
 system.cpu0.dtb.write_misses                      797                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         170                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     344                       # Number of times TLB was flushed by MVA
@@ -434,12 +434,12 @@ system.cpu0.dtb.align_faults                        0                       # Nu
 system.cpu0.dtb.prefetch_faults                   725                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      165                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12039444                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9388073                       # DTB write accesses
+system.cpu0.dtb.read_accesses                12039450                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9388083                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         21422561                       # DTB hits
+system.cpu0.dtb.hits                         21422577                       # DTB hits
 system.cpu0.dtb.misses                           4956                       # DTB misses
-system.cpu0.dtb.accesses                     21427517                       # DTB accesses
+system.cpu0.dtb.accesses                     21427533                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -474,11 +474,11 @@ system.cpu0.itb.walker.walksShort                2296                       # Ta
 system.cpu0.itb.walker.walkWaitTime::samples         2296                       # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::0           2296    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::total         2296                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples  57378110626                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::samples  57378111376                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::mean     1.254717                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0   -14615152624    -25.47%    -25.47% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    71993263250    125.47%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  57378110626                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    71993264000    125.47%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  57378111376                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walkPageSizes::4K         1260     74.03%     74.03% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::1M          442     25.97%    100.00% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::total         1702                       # Table walker page sizes translated
@@ -489,7 +489,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1702                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1702                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin::total         3998                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    57357207                       # ITB inst hits
+system.cpu0.itb.inst_hits                    57357196                       # ITB inst hits
 system.cpu0.itb.inst_misses                      2296                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -506,39 +506,39 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                57359503                       # ITB inst accesses
-system.cpu0.itb.hits                         57357207                       # DTB hits
+system.cpu0.itb.inst_accesses                57359492                       # ITB inst accesses
+system.cpu0.itb.hits                         57357196                       # DTB hits
 system.cpu0.itb.misses                           2296                       # DTB misses
-system.cpu0.itb.accesses                     57359503                       # DTB accesses
-system.cpu0.numCycles                        69413199                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     57359492                       # DTB accesses
+system.cpu0.numCycles                        69413201                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3088                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   55950811                       # Number of instructions committed
-system.cpu0.committedOps                     67895775                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             59559074                       # Number of integer alu accesses
+system.cpu0.committedInsts                   55950800                       # Number of instructions committed
+system.cpu0.committedOps                     67895777                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             59559088                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  4429                       # Number of float alu accesses
-system.cpu0.num_func_calls                    5748533                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7418510                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    59559074                       # number of integer instructions
+system.cpu0.num_func_calls                    5748539                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7418498                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    59559088                       # number of integer instructions
 system.cpu0.num_fp_insts                         4429                       # number of float instructions
-system.cpu0.num_int_register_reads          109971244                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          41296090                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          109971177                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          41296104                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3323                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1108                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           206667111                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           25287842                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     21990124                       # number of memory refs
-system.cpu0.num_load_insts                   12179885                       # Number of load instructions
-system.cpu0.num_store_insts                   9810239                       # Number of store instructions
-system.cpu0.num_idle_cycles              65532351.821320                       # Number of idle cycles
-system.cpu0.num_busy_cycles              3880847.178680                       # Number of busy cycles
+system.cpu0.num_cc_register_reads           206667117                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           25287808                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     21990141                       # number of memory refs
+system.cpu0.num_load_insts                   12179891                       # Number of load instructions
+system.cpu0.num_store_insts                   9810250                       # Number of store instructions
+system.cpu0.num_idle_cycles              65532353.686303                       # Number of idle cycles
+system.cpu0.num_busy_cycles              3880847.313697                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.055909                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.944091                       # Percentage of idle cycles
-system.cpu0.Branches                         13556627                       # Number of branches fetched
+system.cpu0.Branches                         13556608                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2177      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 46939683     68.04%     68.05% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 46939668     68.04%     68.05% # Class of executed instruction
 system.cpu0.op_class::IntMult                   49866      0.07%     68.12% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     68.12% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     68.12% # Class of executed instruction
@@ -567,21 +567,21 @@ system.cpu0.op_class::SimdFloatMisc              3817      0.01%     68.12% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.12% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.12% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.12% # Class of executed instruction
-system.cpu0.op_class::MemRead                12179885     17.66%     85.78% # Class of executed instruction
-system.cpu0.op_class::MemWrite                9810239     14.22%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                12179891     17.66%     85.78% # Class of executed instruction
+system.cpu0.op_class::MemWrite                9810250     14.22%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  68985667                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           833417                       # number of replacements
+system.cpu0.op_class::total                  68985669                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           833415                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.996599                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           46053699                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           833929                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            55.224964                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           46053704                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           833927                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.225102                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.718134                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.522877                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.743087                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data    15.012501                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.718128                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.522887                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.743086                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data    15.012497                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.936949                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.022506                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011217                       # Average percentage of cache occupancy
@@ -592,53 +592,53 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0           91
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        193158098                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       193158098                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11428917                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      3665384                       # number of ReadReq hits
+system.cpu0.dcache.tags.tag_accesses        193158108                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       193158108                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     11428921                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      3665380                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu2.data      4294725                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data      6439390                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25828416                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      9038916                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      2620667                       # number of WriteReq hits
+system.cpu0.dcache.ReadReq_hits::cpu3.data      6439389                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25828415                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      9038925                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      2620658                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::cpu2.data      3331215                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data      3935723                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18926521                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       169434                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteReq_hits::cpu3.data      3935728                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18926526                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       169435                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu1.data        54580                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu2.data        74986                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu3.data        86424                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       385424                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210126                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74902                       # number of LoadLockedReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       385425                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210127                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74901                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        77543                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        87725                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       450296                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       211417                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        76882                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       211418                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        76881                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu2.data        80173                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu3.data        91598                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       460070                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20467833                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      6286051                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data     20467846                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      6286038                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::cpu2.data      7625940                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     10375113                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        44754937                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20637267                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      6340631                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu3.data     10375117                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        44754941                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20637281                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      6340618                       # number of overall hits
 system.cpu0.dcache.overall_hits::cpu2.data      7700926                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     10461537                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       45140361                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data     10461541                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       45140366                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data       163054                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::cpu1.data        56550                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::cpu2.data        94465                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data       206058                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       520127                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data       206057                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       520126                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data       128070                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::cpu1.data        30037                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::cpu2.data        97212                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      1098175                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1353494                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data      1098174                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1353493                       # number of WriteReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu0.data        50296                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu1.data        17954                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu2.data        32256                       # number of SoftPFReq misses
@@ -655,70 +655,70 @@ system.cpu0.dcache.StoreCondReq_misses::total           27
 system.cpu0.dcache.demand_misses::cpu0.data       291124                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::cpu1.data        86587                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::cpu2.data       191677                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      1304233                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1873621                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      1304231                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1873619                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data       341420                       # number of overall misses
 system.cpu0.dcache.overall_misses::cpu1.data       104541                       # number of overall misses
 system.cpu0.dcache.overall_misses::cpu2.data       223933                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      1342364                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2012258                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      1342362                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2012256                       # number of overall misses
 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   1025638000                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1410367000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3710226000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6146231000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1809303500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6517751997                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  77696262478                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  86023317975                       # number of WriteReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3709040500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6145045500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1809360000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6517744997                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  77695281478                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  86022386475                       # number of WriteReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     36347500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49512000                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    113107500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::total    198967000                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       883000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total       883000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   2834941500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data   7928118997                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data  81406488478                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  92169548975                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   2834941500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data   7928118997                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data  81406488478                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  92169548975                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     11591971                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      3721934                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu1.data   2834998000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data   7928111997                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data  81404321978                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  92167431975                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   2834998000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data   7928111997                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data  81404321978                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  92167431975                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11591975                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      3721930                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu2.data      4389190                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data      6645448                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26348543                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9166986                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      2650704                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data      6645446                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26348541                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9166995                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      2650695                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu2.data      3428427                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data      5033898                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     20280015                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       219730                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data      5033902                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     20280019                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       219731                       # number of SoftPFReq accesses(hits+misses)
 system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        72534                       # number of SoftPFReq accesses(hits+misses)
 system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       107242                       # number of SoftPFReq accesses(hits+misses)
 system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       124555                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       524061                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       214028                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77519                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       524062                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       214029                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77518                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        81128                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        95645                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       468320                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       211419                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        76882                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       211420                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        76881                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        80173                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        91623                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       460097                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     20758957                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      6372638                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     20758970                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      6372625                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::cpu2.data      7817617                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     11679346                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     46628558                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     20978687                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      6445172                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     11679348                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     46628560                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     20978701                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      6445159                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::cpu2.data      7924859                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     11803901                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     47152619                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     11803903                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     47152622                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.014066                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.015194                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.021522                       # miss rate for ReadReq accesses
@@ -729,13 +729,13 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.011332
 system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.028355                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.218156                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.066740                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.228899                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.228898                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.247525                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.300778                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.306138                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.264544                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.264543                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018231                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.033759                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.033760                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.044189                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.082806                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038487                       # miss rate for LoadLockedReq accesses
@@ -754,36 +754,34 @@ system.cpu0.dcache.overall_miss_rate::cpu3.data     0.113722
 system.cpu0.dcache.overall_miss_rate::total     0.042675                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18136.834660                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14930.048166                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18005.736249                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11816.788977                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60235.825815                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67046.784317                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70750.347147                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 63556.482685                       # average WriteReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18000.070369                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11814.532440                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60237.706828                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67046.712309                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70749.518271                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 63555.841423                       # average WriteReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13888.995032                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13810.878661                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14281.250000                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.003551                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        35320                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32703.703704                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32740.959959                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41361.869171                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62417.135955                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 49193.272799                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27117.987201                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35403.977962                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60644.123709                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 45804.041517                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       501932                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        35431                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            12377                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32741.612482                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41361.832651                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62415.570538                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 49192.195412                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27118.527659                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35403.946703                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60642.600117                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 45803.034989                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       501934                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        34859                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            12379                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets            549                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.553607                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    64.537341                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       692124                       # number of writebacks
-system.cpu0.dcache.writebacks::total           692124                       # number of writebacks
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.547217                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    63.495446                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       692123                       # number of writebacks
+system.cpu0.dcache.writebacks::total           692123                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           75                       # number of ReadReq MSHR hits
 system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        15084                       # number of ReadReq MSHR hits
 system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data        94480                       # number of ReadReq MSHR hits
@@ -805,12 +803,12 @@ system.cpu0.dcache.overall_mshr_hits::cpu3.data      1104529
 system.cpu0.dcache.overall_mshr_hits::total      1163930                       # number of overall MSHR hits
 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        56475                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        79381                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       111578                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       247434                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       111577                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       247433                       # number of ReadReq MSHR misses
 system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        30037                       # number of WriteReq MSHR misses
 system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        52970                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88126                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       171133                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88125                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       171132                       # number of WriteReq MSHR misses
 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        17691                       # number of SoftPFReq MSHR misses
 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        22463                       # number of SoftPFReq MSHR misses
 system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        28075                       # number of SoftPFReq MSHR misses
@@ -823,12 +821,12 @@ system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           25
 system.cpu0.dcache.StoreCondReq_mshr_misses::total           25                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.demand_mshr_misses::cpu1.data        86512                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.demand_mshr_misses::cpu2.data       132351                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data       199704                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       418567                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data       199702                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       418565                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu1.data       104203                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu2.data       154814                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data       227779                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       486796                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data       227777                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       486794                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3539                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         5604                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         8403                       # number of ReadReq MSHR uncacheable
@@ -843,12 +841,12 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        15034
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31407                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    967480000                       # number of ReadReq MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1154731000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1737713500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3859924500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1779266500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3530686500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6386365938                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11696318938                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1737821000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3860032000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1779323000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3530687000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6386469938                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11696479938                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    234355500                       # number of SoftPFReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    312434500                       # number of SoftPFReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    488593000                       # number of SoftPFReq MSHR miss cycles
@@ -859,34 +857,30 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     38674500
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76261000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       858000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       858000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2746746500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4685417500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8124079438                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15556243438                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2981102000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   4997852000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8612672438                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16591626438                       # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2746803000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4685418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8124290938                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  15556511938                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2981158500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   4997852500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8612883938                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16591894938                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    629109500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1118645000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1808845000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3556599500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    517115500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    860105000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1408279452                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2785499952                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1146225000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1978750000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   3217124452                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6342099452                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1808848000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3556602500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    629109500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1118645000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1808848000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3556602500                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015174                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018086                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016790                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009391                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011332                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015450                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017507                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008439                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017506                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008438                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.243899                       # mshr miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.209461                       # mshr miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.225402                       # mshr miss rate for SoftPFReq accesses
@@ -907,12 +901,12 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019297
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.010324                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17131.119965                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14546.692533                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15573.979638                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15599.814496                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59235.825815                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.455352                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72468.578376                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68346.367667                       # average WriteReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15575.082678                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15600.312004                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59237.706828                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.464791                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72470.580857                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68347.707840                       # average WriteReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13247.159573                       # average SoftPFReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13908.850109                       # average SoftPFReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17403.134461                       # average SoftPFReq mshr miss latency
@@ -923,40 +917,35 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16001.034340
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16260.341151                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        34320                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        34320                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31749.890189                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.451444                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40680.604485                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37165.479930                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28608.600520                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.945987                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37811.529763                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34083.325331                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31750.543277                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.455221                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40682.070976                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37166.298993                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28609.142731                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.949216                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37812.790308                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.016931                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177764.764058                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199615.453248                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215261.811258                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.441924                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179304.958391                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197907.271054                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 212378.140854                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200959.523267                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178456.328818                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198869.346734                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 213989.919649                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201932.672716                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215262.168273                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.612903                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97946.364627                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 112426.633166                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 120317.147798                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 113242.350431                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements          1977299                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.446080                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           94017526                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.tagsinuse          511.446081                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           94017501                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs          1977811                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            47.536153                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            47.536140                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      12783647500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   433.555546                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.959606                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    24.981249                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst    41.949679                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   433.555541                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.959616                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    24.981248                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst    41.949675                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.846788                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021405                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.048792                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021406                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.048791                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::cpu3.inst     0.081933                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998918                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -965,65 +954,65 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1          220
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         98016445                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        98016445                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     56629058                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     17886575                       # number of ReadReq hits
+system.cpu0.icache.tags.tag_accesses         98016418                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        98016418                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     56629047                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     17886534                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu2.inst     10324474                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst      9177419                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       94017526                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     56629058                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     17886575                       # number of demand (read+write) hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst      9177446                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       94017501                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     56629047                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     17886534                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::cpu2.inst     10324474                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst      9177419                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        94017526                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     56629058                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     17886575                       # number of overall hits
+system.cpu0.icache.demand_hits::cpu3.inst      9177446                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        94017501                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     56629047                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     17886534                       # number of overall hits
 system.cpu0.icache.overall_hits::cpu2.inst     10324474                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst      9177419                       # number of overall hits
-system.cpu0.icache.overall_hits::total       94017526                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst      9177446                       # number of overall hits
+system.cpu0.icache.overall_hits::total       94017501                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst       729851                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::cpu1.inst       205937                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::cpu2.inst       497244                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst       588040                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2021072                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst       588038                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2021070                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst       729851                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::cpu1.inst       205937                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::cpu2.inst       497244                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst       588040                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2021072                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu3.inst       588038                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2021070                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst       729851                       # number of overall misses
 system.cpu0.icache.overall_misses::cpu1.inst       205937                       # number of overall misses
 system.cpu0.icache.overall_misses::cpu2.inst       497244                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst       588040                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2021072                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu3.inst       588038                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2021070                       # number of overall misses
 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2906684000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7063506500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   8485451487                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  18455641987                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7063507000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   8486116487                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  18456307487                       # number of ReadReq miss cycles
 system.cpu0.icache.demand_miss_latency::cpu1.inst   2906684000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   7063506500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst   8485451487                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  18455641987                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   7063507000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst   8486116487                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  18456307487                       # number of demand (read+write) miss cycles
 system.cpu0.icache.overall_miss_latency::cpu1.inst   2906684000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   7063506500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst   8485451487                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  18455641987                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     57358909                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     18092512                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.overall_miss_latency::cpu2.inst   7063507000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst   8486116487                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  18456307487                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     57358898                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     18092471                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::cpu2.inst     10821718                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst      9765459                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     96038598                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     57358909                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     18092512                       # number of demand (read+write) accesses
+system.cpu0.icache.ReadReq_accesses::cpu3.inst      9765484                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     96038571                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     57358898                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     18092471                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::cpu2.inst     10821718                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst      9765459                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     96038598                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     57358909                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     18092512                       # number of overall (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst      9765484                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     96038571                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     57358898                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     18092471                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::cpu2.inst     10821718                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst      9765459                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     96038598                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst      9765484                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     96038571                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012724                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011382                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045949                       # miss rate for ReadReq accesses
@@ -1040,33 +1029,31 @@ system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045949
 system.cpu0.icache.overall_miss_rate::cpu3.inst     0.060216                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     0.021044                       # miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14114.433055                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14205.312684                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14430.058307                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9131.610347                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14205.313689                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14431.238265                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9131.948664                       # average ReadReq miss latency
 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14114.433055                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14205.312684                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14430.058307                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9131.610347                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14205.313689                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14431.238265                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9131.948664                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14114.433055                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14205.312684                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14430.058307                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9131.610347                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14205.313689                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14431.238265                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9131.948664                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs         7577                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs              331                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.891239                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      1977299                       # number of writebacks
 system.cpu0.icache.writebacks::total          1977299                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        43224                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        43224                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst        43224                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        43224                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst        43224                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        43224                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        43222                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        43222                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst        43222                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        43222                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst        43222                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        43222                       # number of overall MSHR hits
 system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       205937                       # number of ReadReq MSHR misses
 system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       497244                       # number of ReadReq MSHR misses
 system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       544816                       # number of ReadReq MSHR misses
@@ -1080,17 +1067,17 @@ system.cpu0.icache.overall_mshr_misses::cpu2.inst       497244
 system.cpu0.icache.overall_mshr_misses::cpu3.inst       544816                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total      1247997                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2700747000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6566263500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7404631489                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  16671641989                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6566264000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7404656989                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  16671667989                       # number of ReadReq MSHR miss cycles
 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2700747000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6566263500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7404631489                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  16671641989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6566264000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7404656989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  16671667989                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2700747000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6566263500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7404631489                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  16671641989                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6566264000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7404656989                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  16671667989                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011382                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045949                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for ReadReq accesses
@@ -1104,18 +1091,17 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045949
 system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.012995                       # mshr miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13205.314695                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13591.068341                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.719603                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13205.315700                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13591.115145                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.740437                       # average ReadReq mshr miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.314695                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.068341                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.719603                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.315700                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.115145                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.740437                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.314695                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.068341                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.719603                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.315700                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.115145                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.740437                       # average overall mshr miss latency
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1175,9 +1161,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1607
 system.cpu1.dtb.walker.walkRequestOrigin::total         3505                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3875526                       # DTB read hits
+system.cpu1.dtb.read_hits                     3875521                       # DTB read hits
 system.cpu1.dtb.read_misses                      1673                       # DTB read misses
-system.cpu1.dtb.write_hits                    2730535                       # DTB write hits
+system.cpu1.dtb.write_hits                    2730525                       # DTB write hits
 system.cpu1.dtb.write_misses                      225                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         151                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     137                       # Number of times TLB was flushed by MVA
@@ -1185,15 +1171,15 @@ system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Nu
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
 system.cpu1.dtb.flush_entries                    1104                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   239                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   238                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                       65                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3877199                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2730760                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3877194                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2730750                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6606061                       # DTB hits
+system.cpu1.dtb.hits                          6606046                       # DTB hits
 system.cpu1.dtb.misses                           1898                       # DTB misses
-system.cpu1.dtb.accesses                      6607959                       # DTB accesses
+system.cpu1.dtb.accesses                      6607944                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1255,7 +1241,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          679                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::total          679                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin::total         1616                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    18092512                       # ITB inst hits
+system.cpu1.itb.inst_hits                    18092471                       # ITB inst hits
 system.cpu1.itb.inst_misses                       937                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -1272,39 +1258,39 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                18093449                       # ITB inst accesses
-system.cpu1.itb.hits                         18092512                       # DTB hits
+system.cpu1.itb.inst_accesses                18093408                       # ITB inst accesses
+system.cpu1.itb.hits                         18092471                       # DTB hits
 system.cpu1.itb.misses                            937                       # DTB misses
-system.cpu1.itb.accesses                     18093449                       # DTB accesses
+system.cpu1.itb.accesses                     18093408                       # DTB accesses
 system.cpu1.numCycles                       144009903                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   17421496                       # Number of instructions committed
-system.cpu1.committedOps                     20899704                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             18577797                       # Number of integer alu accesses
+system.cpu1.committedInsts                   17421457                       # Number of instructions committed
+system.cpu1.committedOps                     20899652                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             18577744                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  1420                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1993621                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2230861                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    18577797                       # number of integer instructions
+system.cpu1.num_func_calls                    1993615                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2230860                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    18577744                       # number of integer instructions
 system.cpu1.num_fp_insts                         1420                       # number of float instructions
-system.cpu1.num_int_register_reads           34369600                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          13035963                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           34369524                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          13035923                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1160                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                260                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            76091586                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            7577345                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      6800182                       # number of memory refs
-system.cpu1.num_load_insts                    3918123                       # Number of load instructions
-system.cpu1.num_store_insts                   2882059                       # Number of store instructions
-system.cpu1.num_idle_cycles              136636530.852378                       # Number of idle cycles
-system.cpu1.num_busy_cycles              7373372.147622                       # Number of busy cycles
+system.cpu1.num_cc_register_reads            76091406                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            7577340                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      6800165                       # number of memory refs
+system.cpu1.num_load_insts                    3918117                       # Number of load instructions
+system.cpu1.num_store_insts                   2882048                       # Number of store instructions
+system.cpu1.num_idle_cycles              136636530.804008                       # Number of idle cycles
+system.cpu1.num_busy_cycles              7373372.195992                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.051200                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.948800                       # Percentage of idle cycles
-system.cpu1.Branches                          4337148                       # Number of branches fetched
+system.cpu1.Branches                          4337141                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   23      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 14686036     68.30%     68.30% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 14685999     68.30%     68.30% # Class of executed instruction
 system.cpu1.op_class::IntMult                   16352      0.08%     68.37% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     68.37% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     68.37% # Class of executed instruction
@@ -1333,11 +1319,11 @@ system.cpu1.op_class::SimdFloatMisc               955      0.00%     68.38% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.38% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.38% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.38% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3918123     18.22%     86.60% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2882059     13.40%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3918117     18.22%     86.60% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2882048     13.40%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  21503548                       # Class of executed instruction
+system.cpu1.op_class::total                  21503494                       # Class of executed instruction
 system.cpu2.branchPred.lookups                5770264                       # Number of BP lookups
 system.cpu2.branchPred.condPredicted          2970192                       # Number of conditional branches predicted
 system.cpu2.branchPred.condIncorrect           504477                       # Number of conditional branches incorrect
@@ -1517,7 +1503,7 @@ system.cpu2.itb.inst_accesses                10824992                       # IT
 system.cpu2.itb.hits                         10823576                       # DTB hits
 system.cpu2.itb.misses                           1416                       # DTB misses
 system.cpu2.itb.accesses                     10824992                       # DTB accesses
-system.cpu2.numCycles                      1395003779                       # number of cpu cycles simulated
+system.cpu2.numCycles                      1395003781                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu2.committedInsts                   20361751                       # Number of instructions committed
@@ -1564,20 +1550,20 @@ system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Cl
 system.cpu2.op_class_0::total                24653563                       # Class of committed instruction
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                       42378112                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     1352625667                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               13251998                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted          7208175                       # Number of conditional branches predicted
+system.cpu2.tickCycles                       42378126                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     1352625655                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               13252062                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted          7208218                       # Number of conditional branches predicted
 system.cpu3.branchPred.condIncorrect           300007                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups             8273745                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                4241517                       # Number of BTB hits
+system.cpu3.branchPred.BTBLookups             8273793                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                4241536                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            51.264778                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                3096619                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct            51.264710                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                3096631                       # Number of times the RAS was used to get a target.
 system.cpu3.branchPred.RASInCorrect             16788                       # Number of incorrect RAS predictions.
-system.cpu3.branchPred.indirectLookups        2038227                       # Number of indirect predictor lookups.
-system.cpu3.branchPred.indirectHits           1978271                       # Number of indirect target hits.
-system.cpu3.branchPred.indirectMisses           59956                       # Number of indirect misses.
+system.cpu3.branchPred.indirectLookups        2038250                       # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits           1978281                       # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses           59969                       # Number of indirect misses.
 system.cpu3.branchPredindirectMispredicted        18256                       # Number of mispredicted indirect branches.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1608,15 +1594,15 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                    33988                       # Table walker walks requested
-system.cpu3.dtb.walker.walksShort               33988                       # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11189                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walks                    33989                       # Table walker walks requested
+system.cpu3.dtb.walker.walksShort               33989                       # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11190                       # Level at which table walker walks with short descriptors terminate
 system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         8109                       # Level at which table walker walks with short descriptors terminate
 system.cpu3.dtb.walker.walksSquashedBefore        14690                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples        19298                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean   517.203855                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev  3689.785170                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-16383        19110     99.03%     99.03% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::samples        19299                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean   517.177056                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev  3689.691447                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-16383        19111     99.03%     99.03% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::16384-32767          146      0.76%     99.78% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::32768-49151           30      0.16%     99.94% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::49152-65535            4      0.02%     99.96% # Table walker wait (enqueue to first request) latency
@@ -1625,7 +1611,7 @@ system.cpu3.dtb.walker.walkWaitTime::81920-98303            2      0.01%     99.
 system.cpu3.dtb.walker.walkWaitTime::98304-114687            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::114688-131071            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::147456-163839            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total        19298                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total        19299                       # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkCompletionTime::samples         6381                       # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::mean 13105.939508                       # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::gmean 10791.784480                       # Table walker service (enqueue to completion) latency
@@ -1636,9 +1622,9 @@ system.cpu3.dtb.walker.walkCompletionTime::65536-98303            1      0.02%
 system.cpu3.dtb.walker.walkCompletionTime::131072-163839            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::360448-393215            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::total         6381                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples  -8047267064                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     0.135073                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1  -8095966564    100.61%    100.61% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::samples  -8047359064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.134723                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1  -8096058564    100.61%    100.61% # Table walker pending requests distribution
 system.cpu3.dtb.walker.walksPending::2-3     33943000     -0.42%    100.18% # Table walker pending requests distribution
 system.cpu3.dtb.walker.walksPending::4-5      7702500     -0.10%    100.09% # Table walker pending requests distribution
 system.cpu3.dtb.walker.walksPending::6-7      2846000     -0.04%    100.05% # Table walker pending requests distribution
@@ -1654,22 +1640,22 @@ system.cpu3.dtb.walker.walksPending::24-25        64500     -0.00%    100.00% #
 system.cpu3.dtb.walker.walksPending::26-27        35000     -0.00%    100.00% # Table walker pending requests distribution
 system.cpu3.dtb.walker.walksPending::28-29        17500     -0.00%    100.00% # Table walker pending requests distribution
 system.cpu3.dtb.walker.walksPending::30-31        59500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total  -8047267064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total  -8047359064                       # Table walker pending requests distribution
 system.cpu3.dtb.walker.walkPageSizes::4K         1874     70.21%     70.21% # Table walker page sizes translated
 system.cpu3.dtb.walker.walkPageSizes::1M          795     29.79%    100.00% # Table walker page sizes translated
 system.cpu3.dtb.walker.walkPageSizes::total         2669                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        33988                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        33989                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        33988                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        33989                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2669                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2669                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total        36657                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total        36658                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                     7187515                       # DTB read hits
-system.cpu3.dtb.read_misses                     29422                       # DTB read misses
-system.cpu3.dtb.write_hits                    5346412                       # DTB write hits
+system.cpu3.dtb.read_hits                     7187448                       # DTB read hits
+system.cpu3.dtb.read_misses                     29423                       # DTB read misses
+system.cpu3.dtb.write_hits                    5346423                       # DTB write hits
 system.cpu3.dtb.write_misses                     4566                       # DTB write misses
 system.cpu3.dtb.flush_tlb                         162                       # Number of times complete TLB was flushed
 system.cpu3.dtb.flush_tlb_mva                     274                       # Number of times TLB was flushed by MVA
@@ -1680,12 +1666,12 @@ system.cpu3.dtb.align_faults                      451                       # Nu
 system.cpu3.dtb.prefetch_faults                   735                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu3.dtb.perms_faults                      408                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                 7216937                       # DTB read accesses
-system.cpu3.dtb.write_accesses                5350978                       # DTB write accesses
+system.cpu3.dtb.read_accesses                 7216871                       # DTB read accesses
+system.cpu3.dtb.write_accesses                5350989                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                         12533927                       # DTB hits
-system.cpu3.dtb.misses                          33988                       # DTB misses
-system.cpu3.dtb.accesses                     12567915                       # DTB accesses
+system.cpu3.dtb.hits                         12533871                       # DTB hits
+system.cpu3.dtb.misses                          33989                       # DTB misses
+system.cpu3.dtb.accesses                     12567860                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1755,16 +1741,16 @@ system.cpu3.itb.walker.walkCompletionTime::40960-45055            1      0.06%
 system.cpu3.itb.walker.walkCompletionTime::45056-49151            1      0.06%     99.89% # Table walker service (enqueue to completion) latency
 system.cpu3.itb.walker.walkCompletionTime::49152-53247            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu3.itb.walker.walkCompletionTime::total         1793                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples  -8048536564                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     0.273748                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev     0.444975                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::samples  -8048628564                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.273756                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.444979                       # Table walker pending requests distribution
 system.cpu3.itb.walker.walksPending::0    -5842963052     72.60%     72.60% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1    -2207207512     27.42%    100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1    -2207299512     27.42%    100.02% # Table walker pending requests distribution
 system.cpu3.itb.walker.walksPending::2        1197000     -0.01%    100.01% # Table walker pending requests distribution
 system.cpu3.itb.walker.walksPending::3         240000     -0.00%    100.00% # Table walker pending requests distribution
 system.cpu3.itb.walker.walksPending::4         159500     -0.00%    100.00% # Table walker pending requests distribution
 system.cpu3.itb.walker.walksPending::5          37500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total  -8048536564                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total  -8048628564                       # Table walker pending requests distribution
 system.cpu3.itb.walker.walkPageSizes::4K          959     73.04%     73.04% # Table walker page sizes translated
 system.cpu3.itb.walker.walkPageSizes::1M          354     26.96%    100.00% # Table walker page sizes translated
 system.cpu3.itb.walker.walkPageSizes::total         1313                       # Table walker page sizes translated
@@ -1775,7 +1761,7 @@ system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1313                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1313                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin::total         5899                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                     9766961                       # ITB inst hits
+system.cpu3.itb.inst_hits                     9766986                       # ITB inst hits
 system.cpu3.itb.inst_misses                      4586                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
@@ -1792,106 +1778,106 @@ system.cpu3.itb.domain_faults                       0                       # Nu
 system.cpu3.itb.perms_faults                      793                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                 9771547                       # ITB inst accesses
-system.cpu3.itb.hits                          9766961                       # DTB hits
+system.cpu3.itb.inst_accesses                 9771572                       # ITB inst accesses
+system.cpu3.itb.hits                          9766986                       # DTB hits
 system.cpu3.itb.misses                           4586                       # DTB misses
-system.cpu3.itb.accesses                      9771547                       # DTB accesses
-system.cpu3.numCycles                        57688008                       # number of cpu cycles simulated
+system.cpu3.itb.accesses                      9771572                       # DTB accesses
+system.cpu3.numCycles                        57688006                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles          20811667                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                      52032939                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   13251998                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches           9316407                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                     33930226                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                1581195                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.icacheStallCycles          20811649                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                      52033022                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   13252062                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches           9316448                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                     33930227                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                1581201                       # Number of cycles fetch has spent squashing
 system.cpu3.fetch.TlbCycles                     68181                       # Number of cycles fetch has spent waiting for tlb
 system.cpu3.fetch.MiscStallCycles                 837                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu3.fetch.PendingDrainCycles              231                       # Number of cycles fetch has spent waiting on pipes to drain
 system.cpu3.fetch.PendingTrapStallCycles       120341                       # Number of stall cycles due to pending traps
 system.cpu3.fetch.PendingQuiesceStallCycles        80383                       # Number of stall cycles due to pending quiesce instructions
 system.cpu3.fetch.IcacheWaitRetryStallCycles          479                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                  9765461                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes               207701                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.CacheLines                  9765486                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes               207700                       # Number of outstanding Icache misses that were squashed
 system.cpu3.fetch.ItlbSquashes                   2399                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples          55802921                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.126478                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.271735                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::samples          55802907                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.126480                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.271736                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                41696635     74.72%     74.72% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                 1836227      3.29%     78.01% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                 1165179      2.09%     80.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 3688200      6.61%     86.71% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                  906119      1.62%     88.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                  549240      0.98%     89.32% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 2914414      5.22%     94.54% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                  602851      1.08%     95.62% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                 2444056      4.38%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                41696580     74.72%     74.72% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                 1836235      3.29%     78.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                 1165184      2.09%     80.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 3688211      6.61%     86.71% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                  906128      1.62%     88.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                  549241      0.98%     89.32% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 2914438      5.22%     94.54% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                  602830      1.08%     95.62% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                 2444060      4.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total            55802921                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.229718                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.901971                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                14568500                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles             31866419                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                  7772530                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles               890722                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                704491                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved              971896                       # Number of times decode resolved a branch
+system.cpu3.fetch.rateDist::total            55802907                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.229720                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.901973                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                14568551                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles             31866325                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                  7772560                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles               890718                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                704494                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved              971899                       # Number of times decode resolved a branch
 system.cpu3.decode.BranchMispred                87220                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts              44589995                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts               289462                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles                704491                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                15048240                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                3770694                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles      21829138                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                  8174722                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles              6275353                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts              42740341                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                 1149                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents                970338                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                 89122                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               4852694                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands           44469906                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            196241867                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups        47658111                       # Number of integer rename lookups
+system.cpu3.decode.DecodedInsts              44590073                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts               289455                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles                704494                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                15048291                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                3770246                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles      21829644                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                  8174749                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles              6275200                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts              42740400                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                 1148                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents                970300                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                 89126                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents               4852570                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands           44469975                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            196242063                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups        47658053                       # Number of integer rename lookups
 system.cpu3.rename.fp_rename_lookups             4195                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps             37088315                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                 7381591                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts            715058                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts        665415                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                  5054904                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads             7671721                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores            5900836                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          1096117                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         1546300                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                  41143792                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded             502169                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                 39136227                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued            53751                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined        5932360                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     13678384                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.rename.CommittedMaps             37088424                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                 7381551                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts            715073                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts        665430                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                  5054867                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads             7671703                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores            5900822                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          1096118                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         1546348                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                  41143800                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded             502182                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                 39136171                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued            53747                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined        5932287                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     13678209                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu3.iq.iqSquashedNonSpecRemoved         53132                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples     55802921                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::samples     55802907                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::mean        0.701329                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.406591                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.406589                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0           40242426     72.12%     72.12% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1            5178735      9.28%     81.40% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2            3976743      7.13%     88.52% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3            3203415      5.74%     94.26% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4            1255788      2.25%     96.51% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5             764372      1.37%     97.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6             832267      1.49%     99.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7             238253      0.43%     99.80% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8             110922      0.20%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0           40242389     72.12%     72.12% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1            5178782      9.28%     81.40% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2            3976738      7.13%     88.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3            3203416      5.74%     94.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4            1255770      2.25%     96.51% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5             764374      1.37%     97.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6             832269      1.49%     99.37% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7             238251      0.43%     99.80% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8             110918      0.20%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total       55802921                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total       55802907                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                  55579      9.37%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                  55578      9.37%      9.37% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.37% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.37% # attempts to use FU when none available
 system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.37% # attempts to use FU when none available
@@ -1920,12 +1906,12 @@ system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.37% # at
 system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.37% # attempts to use FU when none available
 system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.37% # attempts to use FU when none available
 system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.37% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                279420     47.11%     56.48% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite               258160     43.52%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                279414     47.11%     56.48% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite               258161     43.52%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass               84      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu             26095739     66.68%     66.68% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu             26095745     66.68%     66.68% # Type of FU issued
 system.cpu3.iq.FU_type_0::IntMult               29921      0.08%     66.76% # Type of FU issued
 system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.76% # Type of FU issued
 system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.76% # Type of FU issued
@@ -1954,94 +1940,94 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc          2385      0.01%     66.76% # Ty
 system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.76% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     66.76% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead             7397588     18.90%     85.66% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite            5610508     14.34%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead             7397516     18.90%     85.66% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite            5610518     14.34%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total              39136227                       # Type of FU issued
-system.cpu3.iq.rate                          0.678412                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                     593159                       # FU busy when requested
+system.cpu3.iq.FU_type_0::total              39136171                       # Type of FU issued
+system.cpu3.iq.rate                          0.678411                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                     593153                       # FU busy when requested
 system.cpu3.iq.fu_busy_rate                  0.015156                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads         134713506                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes         47601839                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses     37987745                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.int_inst_queue_reads         134713370                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes         47601786                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses     37987762                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads               8779                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes              5136                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses         3873                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses              39724596                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses              39724534                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                   4706                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads          167565                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads          167566                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      1160512                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses         1106                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation        29283                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores       565980                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      1160486                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses         1105                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation        29281                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores       565962                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads       108566                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked        42617                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads       108568                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked        42515                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                704491                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                3164370                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles               480380                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts           41688366                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts            67674                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts              7671721                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts             5900836                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts            259515                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                 22770                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents               451545                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents         29283                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect        127479                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect       130166                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts              257645                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts             38819065                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts              7269277                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts           283258                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles                704494                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                3163832                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles               480485                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts           41688387                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts            67679                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts              7671703                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts             5900822                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts            259528                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                 22774                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents               451647                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents         29281                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect        127480                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect       130164                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts              257644                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts             38819012                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts              7269209                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts           283254                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu3.iew.exec_nop                        42405                       # number of nop insts executed
-system.cpu3.iew.exec_refs                    12824699                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                 7229147                       # Number of branches executed
-system.cpu3.iew.exec_stores                   5555422                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.672914                       # Inst execution rate
-system.cpu3.iew.wb_sent                      38534574                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                     37991618                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                 19895902                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                 34654427                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      0.658570                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.574123                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts        5941681                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls         449037                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.iew.exec_refs                    12824644                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                 7229166                       # Number of branches executed
+system.cpu3.iew.exec_stores                   5555435                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.672913                       # Inst execution rate
+system.cpu3.iew.wb_sent                      38534594                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                     37991635                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                 19895864                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                 34654258                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      0.658571                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.574125                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts        5941608                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls         449050                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu3.commit.branchMispredicts           213879                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples     54520381                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.655520                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::samples     54520380                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.655522                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::stdev     1.547792                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0     40723522     74.69%     74.69% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1      6130634     11.24%     85.94% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2      3105134      5.70%     91.63% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      1318169      2.42%     94.05% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4       725183      1.33%     95.38% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5       499193      0.92%     96.30% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6       937316      1.72%     98.02% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7       226626      0.42%     98.43% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8       854604      1.57%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0     40723432     74.69%     74.69% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1      6130706     11.24%     85.94% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2      3105147      5.70%     91.63% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      1318175      2.42%     94.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4       725189      1.33%     95.38% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5       499185      0.92%     96.30% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6       937323      1.72%     98.02% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7       226618      0.42%     98.43% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8       854605      1.57%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total     54520381                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts            29254199                       # Number of instructions committed
-system.cpu3.commit.committedOps              35739216                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total     54520380                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts            29254285                       # Number of instructions committed
+system.cpu3.commit.committedOps              35739310                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      11846065                       # Number of memory references committed
-system.cpu3.commit.loads                      6511209                       # Number of loads committed
+system.cpu3.commit.refs                      11846077                       # Number of memory references committed
+system.cpu3.commit.loads                      6511217                       # Number of loads committed
 system.cpu3.commit.membars                     174051                       # Number of memory barriers committed
-system.cpu3.commit.branches                   6823805                       # Number of branches committed
+system.cpu3.commit.branches                   6823843                       # Number of branches committed
 system.cpu3.commit.fp_insts                      3728                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                 31222090                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             1239495                       # Number of function calls committed.
+system.cpu3.commit.int_insts                 31222167                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             1239499                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu        23861802     66.77%     66.77% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu        23861884     66.77%     66.77% # Class of committed instruction
 system.cpu3.commit.op_class_0::IntMult          28964      0.08%     66.85% # Class of committed instruction
 system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.85% # Class of committed instruction
 system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.85% # Class of committed instruction
@@ -2070,31 +2056,31 @@ system.cpu3.commit.op_class_0::SimdFloatMisc         2385      0.01%     66.85%
 system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
 system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
 system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead        6511209     18.22%     85.07% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite       5334856     14.93%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead        6511217     18.22%     85.07% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite       5334860     14.93%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total         35739216                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events               854604                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                    89694984                       # The number of ROB reads
-system.cpu3.rob.rob_writes                   84644228                       # The number of ROB writes
-system.cpu3.timesIdled                         227110                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                        1885087                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.commit.op_class_0::total         35739310                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events               854605                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                    89694977                       # The number of ROB reads
+system.cpu3.rob.rob_writes                   84644260                       # The number of ROB writes
+system.cpu3.timesIdled                         227108                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                        1885099                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu3.quiesceCycles                  5160958859                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                   29228584                       # Number of Instructions Simulated
-system.cpu3.committedOps                     35713601                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.973685                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.973685                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.506667                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.506667                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                42269804                       # number of integer regfile reads
-system.cpu3.int_regfile_writes               24060507                       # number of integer regfile writes
+system.cpu3.committedInsts                   29228670                       # Number of Instructions Simulated
+system.cpu3.committedOps                     35713695                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.973679                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.973679                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.506668                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.506668                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                42269766                       # number of integer regfile reads
+system.cpu3.int_regfile_writes               24060528                       # number of integer regfile writes
 system.cpu3.fp_regfile_reads                    14520                       # number of floating regfile reads
 system.cpu3.fp_regfile_writes                   12259                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                137213750                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                14769664                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads               75722045                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                336113                       # number of misc regfile writes
+system.cpu3.cc_regfile_reads                137213612                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                14769581                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads               75722157                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes                336126                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
@@ -2163,7 +2149,7 @@ system.iobus.reqLayer19.occupancy                3000                       # La
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             3863000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             3864000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            22351500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -2189,109 +2175,110 @@ system.iocache.tags.tag_accesses               328227                       # Nu
 system.iocache.tags.data_accesses              328227                       # Number of data accesses
 system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
 system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
+system.iocache.demand_hits::realview.ide           29                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                  29                       # number of demand (read+write) hits
+system.iocache.overall_hits::realview.ide           29                       # number of overall hits
+system.iocache.overall_hits::total                 29                       # number of overall hits
 system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          249                       # number of overall misses
-system.iocache.overall_misses::total              249                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36444                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
+system.iocache.overall_misses::total            36444                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     17512919                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     17512919                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::realview.ide   1907451098                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   1907451098                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     17512919                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     17512919                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     17512919                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     17512919                       # number of overall miss cycles
+system.iocache.demand_miss_latency::realview.ide   1924964017                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1924964017                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   1924964017                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1924964017                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36473                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36473                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36473                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36473                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
 system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.demand_miss_rate::realview.ide     0.999205                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       0.999205                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ide     0.999205                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      0.999205                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 70333.008032                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52699.298190                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 52699.298190                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 70333.008032                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 70333.008032                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 70333.008032                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 70333.008032                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 52819.778756                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 52819.778756                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 52819.778756                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 52819.778756                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36160                       # number of writebacks
 system.iocache.writebacks::total                36160                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          148                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          148                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        15187                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        15187                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          148                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          148                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          148                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        15335                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        15335                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        15335                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        15335                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     10112919                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     10112919                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   1147424968                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   1147424968                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     10112919                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     10112919                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     10112919                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     10112919                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1157537887                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1157537887                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1157537887                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1157537887                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.594378                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.594378                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.419252                       # mshr miss rate for WriteLineReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::total     0.419252                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.594378                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.594378                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.594378                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.594378                       # mshr miss rate for overall accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.420448                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.420448                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.420448                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.420448                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75553.102522                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.102522                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68330.533784                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68330.533784                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68330.533784                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68330.533784                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75483.396609                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75483.396609                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75483.396609                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75483.396609                       # average overall mshr miss latency
 system.l2c.tags.replacements                   103654                       # number of replacements
-system.l2c.tags.tagsinuse                65094.562586                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5149242                       # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse                65094.562604                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5149240                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                   168905                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.486025                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                    30.486013                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle              80133862000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   49018.245054                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   49018.245060                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.971846                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.inst     4276.002230                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.data     2253.870491                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.966972                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.inst      903.622290                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      882.214682                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      882.214681                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu2.dtb.walker    22.046662                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu2.inst     1923.753709                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu2.data      720.306234                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu3.dtb.walker    49.949258                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     3365.651455                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     1676.961608                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst     3365.651463                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data     1676.961612                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.747959                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000015                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
@@ -2317,19 +2304,19 @@ system.l2c.tags.age_task_id_blocks_1024::3         7607                       #
 system.l2c.tags.age_task_id_blocks_1024::4        55305                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000977                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994675                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 45502420                       # Number of tag accesses
-system.l2c.tags.data_accesses                45502420                       # Number of data accesses
+system.l2c.tags.tag_accesses                 45502395                       # Number of tag accesses
+system.l2c.tags.data_accesses                45502395                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker         4144                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         2033                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.dtb.walker         1722                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.itb.walker          868                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2.dtb.walker        13393                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2.itb.walker         1189                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker        21090                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.dtb.walker        21091                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.itb.walker         4127                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  48566                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks       692124                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          692124                       # number of WritebackDirty hits
+system.l2c.ReadReq_hits::total                  48567                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks       692123                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          692123                       # number of WritebackDirty hits
 system.l2c.WritebackClean_hits::writebacks      1939703                       # number of WritebackClean hits
 system.l2c.WritebackClean_hits::total         1939703                       # number of WritebackClean hits
 system.l2c.UpgradeReq_hits::cpu0.data              12                       # number of UpgradeReq hits
@@ -2343,8 +2330,8 @@ system.l2c.SCUpgradeReq_hits::total                19                       # nu
 system.l2c.ReadExReq_hits::cpu0.data            66572                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::cpu1.data            17866                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::cpu2.data            28004                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data            44211                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               156653                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3.data            44210                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               156652                       # number of ReadExReq hits
 system.l2c.ReadCleanReq_hits::cpu0.inst        721971                       # number of ReadCleanReq hits
 system.l2c.ReadCleanReq_hits::cpu1.inst        204101                       # number of ReadCleanReq hits
 system.l2c.ReadCleanReq_hits::cpu2.inst        492422                       # number of ReadCleanReq hits
@@ -2353,8 +2340,8 @@ system.l2c.ReadCleanReq_hits::total           1956655                       # nu
 system.l2c.ReadSharedReq_hits::cpu0.data       211223                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu1.data        72596                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu2.data       101112                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data       137862                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           522793                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data       137861                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           522792                       # number of ReadSharedReq hits
 system.l2c.demand_hits::cpu0.dtb.walker          4144                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.itb.walker          2033                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.inst              721971                       # number of demand (read+write) hits
@@ -2367,11 +2354,11 @@ system.l2c.demand_hits::cpu2.dtb.walker         13393                       # nu
 system.l2c.demand_hits::cpu2.itb.walker          1189                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.inst              492422                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data              129116                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker         21090                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.dtb.walker         21091                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.itb.walker          4127                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.inst              538161                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data              182073                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2684667                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data              182071                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2684666                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.dtb.walker         4144                       # number of overall hits
 system.l2c.overall_hits::cpu0.itb.walker         2033                       # number of overall hits
 system.l2c.overall_hits::cpu0.inst             721971                       # number of overall hits
@@ -2384,11 +2371,11 @@ system.l2c.overall_hits::cpu2.dtb.walker        13393                       # nu
 system.l2c.overall_hits::cpu2.itb.walker         1189                       # number of overall hits
 system.l2c.overall_hits::cpu2.inst             492422                       # number of overall hits
 system.l2c.overall_hits::cpu2.data             129116                       # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker        21090                       # number of overall hits
+system.l2c.overall_hits::cpu3.dtb.walker        21091                       # number of overall hits
 system.l2c.overall_hits::cpu3.itb.walker         4127                       # number of overall hits
 system.l2c.overall_hits::cpu3.inst             538161                       # number of overall hits
-system.l2c.overall_hits::cpu3.data             182073                       # number of overall hits
-system.l2c.overall_hits::total                2684667                       # number of overall hits
+system.l2c.overall_hits::cpu3.data             182071                       # number of overall hits
+system.l2c.overall_hits::total                2684666                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            3                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
@@ -2455,49 +2442,49 @@ system.l2c.UpgradeReq_miss_latency::cpu3.data      1012500
 system.l2c.UpgradeReq_miss_latency::total      1325500                       # number of UpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu3.data       317500                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::total       317500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1517069500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   3110086000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data   5724333000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10351488500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1517126000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   3110079500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data   5724450000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  10351655500                       # number of ReadExReq miss cycles
 system.l2c.ReadCleanReq_miss_latency::cpu1.inst    241264500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    638292000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst    866799499                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1746355999                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst    638292500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst    866843998                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   1746400998                       # number of ReadCleanReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu1.data    341211500                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu2.data    263338500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data    578560500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   1183110500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data    578680000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total   1183230000                       # number of ReadSharedReq miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker       132500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.inst    241264500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1858281000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1858337500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu2.dtb.walker      3451000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    638292000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3373424500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    638292500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   3373418000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu3.dtb.walker      9023500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst    866799499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data   6302893500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     13293561999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst    866843998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data   6303130000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     13293893498                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker       132500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.inst    241264500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1858281000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1858337500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu2.dtb.walker      3451000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    638292000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3373424500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    638292500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   3373418000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu3.dtb.walker      9023500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst    866799499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data   6302893500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    13293561999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst    866843998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data   6303130000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    13293893498                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.dtb.walker         4147                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker         2034                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.dtb.walker         1723                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.itb.walker          868                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu2.dtb.walker        13419                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu2.itb.walker         1189                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.dtb.walker        21156                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker        21157                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu3.itb.walker         4127                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              48663                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks       692124                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       692124                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              48664                       # number of ReadReq accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks       692123                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       692123                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackClean_accesses::writebacks      1939703                       # number of WritebackClean accesses(hits+misses)
 system.l2c.WritebackClean_accesses::total      1939703                       # number of WritebackClean accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data         1127                       # number of UpgradeReq accesses(hits+misses)
@@ -2511,8 +2498,8 @@ system.l2c.SCUpgradeReq_accesses::total            27                       # nu
 system.l2c.ReadExReq_accesses::cpu0.data       126943                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data        29662                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data        52385                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data        87366                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           296356                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data        87365                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           296355                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadCleanReq_accesses::cpu0.inst       729845                       # number of ReadCleanReq accesses(hits+misses)
 system.l2c.ReadCleanReq_accesses::cpu1.inst       205934                       # number of ReadCleanReq accesses(hits+misses)
 system.l2c.ReadCleanReq_accesses::cpu2.inst       497236                       # number of ReadCleanReq accesses(hits+misses)
@@ -2521,8 +2508,8 @@ system.l2c.ReadCleanReq_accesses::total       1977715                       # nu
 system.l2c.ReadSharedReq_accesses::cpu0.data       217252                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu1.data        75187                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu2.data       103095                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data       142064                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       537598                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data       142063                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       537597                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.demand_accesses::cpu0.dtb.walker         4147                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.itb.walker         2034                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.inst          729845                       # number of demand (read+write) accesses
@@ -2535,11 +2522,11 @@ system.l2c.demand_accesses::cpu2.dtb.walker        13419                       #
 system.l2c.demand_accesses::cpu2.itb.walker         1189                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.inst          497236                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.data          155480                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker        21156                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker        21157                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.itb.walker         4127                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.inst          544700                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data          229430                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2860332                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data          229428                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2860331                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu0.dtb.walker         4147                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.itb.walker         2034                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.inst         729845                       # number of overall (read+write) accesses
@@ -2552,11 +2539,11 @@ system.l2c.overall_accesses::cpu2.dtb.walker        13419
 system.l2c.overall_accesses::cpu2.itb.walker         1189                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.inst         497236                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.data         155480                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker        21156                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker        21157                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.itb.walker         4127                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.inst         544700                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data         229430                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2860332                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data         229428                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2860331                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000580                       # miss rate for ReadReq accesses
@@ -2573,8 +2560,8 @@ system.l2c.SCUpgradeReq_miss_rate::total     0.296296                       # mi
 system.l2c.ReadExReq_miss_rate::cpu0.data     0.475576                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data     0.397681                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data     0.465419                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.493956                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.471403                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.493962                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.471404                       # miss rate for ReadExReq accesses
 system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010789                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008901                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.009682                       # miss rate for ReadCleanReq accesses
@@ -2597,7 +2584,7 @@ system.l2c.demand_miss_rate::cpu2.inst       0.009682                       # mi
 system.l2c.demand_miss_rate::cpu2.data       0.169565                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.inst       0.012005                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.206412                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.206413                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           0.061414                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for overall accesses
@@ -2611,7 +2598,7 @@ system.l2c.overall_miss_rate::cpu2.inst      0.009682                       # mi
 system.l2c.overall_miss_rate::cpu2.data      0.169565                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.inst      0.012005                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.206412                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.206413                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          0.061414                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker       132500                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average ReadReq miss latency
@@ -2623,46 +2610,44 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu3.data  1398.480663
 system.l2c.UpgradeReq_avg_miss_latency::total   475.601005                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 39687.500000                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total 39687.500000                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128608.808071                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127561.871949                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132645.881126                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74096.393778                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128613.597830                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127561.605348                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132648.592284                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74097.589171                       # average ReadExReq miss latency
 system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131622.749591                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132590.776901                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 132558.418566                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 82922.886942                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132590.880764                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 132565.223735                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 82925.023647                       # average ReadCleanReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131691.045928                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 132798.033283                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 137686.934793                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 79912.901047                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 137715.373632                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 79920.972644                       # average ReadSharedReq miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.inst 131622.749591                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 129163.897963                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 129167.825120                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 132590.776901                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 127955.716128                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 132590.880764                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 127955.469580                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 132558.418566                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 133093.175243                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 75675.643976                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 132565.223735                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 133098.169225                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 75677.531085                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 131622.749591                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 129163.897963                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 129167.825120                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 132590.776901                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 127955.716128                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 132590.880764                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 127955.469580                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 132558.418566                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 133093.175243                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 75675.643976                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 132565.223735                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 133098.169225                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 75677.531085                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               94985                       # number of writebacks
 system.l2c.writebacks::total                    94985                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            3                       # number of ReadCleanReq MSHR hits
@@ -2740,55 +2725,51 @@ system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3191000
 system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::total     11677000                       # number of ReadReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     25361500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     39106500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     39113500                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     49225500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    113693500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    113700500                       # number of UpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       550500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total       550500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1399109500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2866276000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   5292783000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   9558168500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1399166000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2866269500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   5292900000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   9558335500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    222934500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    590021500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    800941503                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1613897503                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    590022000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    800986002                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1613942502                       # number of ReadCleanReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    315301500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    241631500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    531706501                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   1088639501                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    531826001                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   1088759001                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.inst    222934500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1714411000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1714467500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    590021500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3107907500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    590022000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3107901000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst    800941503                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data   5824489501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  12272382504                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst    800986002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data   5824726001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  12272714003                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst    222934500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1714411000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1714467500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    590021500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3107907500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    590022000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3107901000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst    800941503                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data   5824489501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  12272382504                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst    800986002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data   5824726001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  12272714003                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    584851500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1048585500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1703786000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3337223000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    483931000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    810126000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1331950000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2626007000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1068782500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1858711500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   3035736000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5963230000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1703789000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3337226000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    584851500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1048585500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1703789000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3337226000                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.001938                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for ReadReq accesses
@@ -2801,7 +2782,7 @@ system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.320000
 system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.296296                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.397681                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.465419                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.493956                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.493962                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total     0.267692                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.009675                       # mshr miss rate for ReadCleanReq accesses
@@ -2819,7 +2800,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst     0.009675                       #
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.169449                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.206228                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.206230                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total      0.035422                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for overall accesses
@@ -2829,63 +2810,58 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst     0.009675
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.169449                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.206228                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.206230                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     0.035422                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::total 125559.139785                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67993.297587                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68011.304348                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68023.478261                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67991.022099                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67998.504785                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68002.691388                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68812.500000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68812.500000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118608.808071                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117561.871949                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122645.881126                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 120483.140473                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118613.597830                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117561.605348                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122648.592284                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 120485.245550                       # average ReadExReq mshr miss latency
 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122640.095614                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 122580.578972                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122469.077478                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122640.199543                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 122587.389348                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122472.492184                       # average ReadCleanReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121691.045928                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122967.684478                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127814.062740                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124901.273635                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127842.788702                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124914.984052                       # average ReadSharedReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119163.897963                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119167.825120                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122640.095614                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117965.061110                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122640.199543                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117964.814393                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 122580.578972                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123100.274775                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 121126.170847                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 122587.389348                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123105.273190                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121129.442681                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119163.897963                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119167.825120                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122640.095614                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117965.061110                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122640.199543                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117964.814393                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 122580.578972                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123100.274775                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 121126.170847                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 122587.389348                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123105.273190                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121129.442681                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165258.971461                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 187113.758030                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202759.252648                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.506782                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167798.543689                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186407.271054                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200867.139195                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.925474                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166399.268255                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186805.175879                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 201924.704004                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 189869.455854                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202759.609663                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.677761                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91055.815040                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 105385.477387                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 113329.054144                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 106257.394848                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               40114                       # Transaction distribution
 system.membus.trans_dist::ReadResp              76256                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27565                       # Transaction distribution
@@ -2928,13 +2904,13 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total              422579                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            54357000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            54358000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              681000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              678498                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           480576517                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           480577516                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          576477250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          576478500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer3.occupancy             796581                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
@@ -2979,60 +2955,60 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5652845                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2841067                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5652843                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2841066                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_requests        44935                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops            620                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops          620                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             111946                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             111947                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp           2627538                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27565                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27565                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       760858                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       760857                       # Transaction distribution
 system.toL2Bus.trans_dist::WritebackClean      1977299                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          146343                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          146342                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq            2855                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq            27                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           2881                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296356                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296356                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296355                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296355                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadCleanReq       1977848                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       537746                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       537745                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        15186                       # Transaction distribution
 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5950911                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2624548                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2624542                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        25489                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       101523                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8702471                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       101525                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8702467                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    253157304                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97861305                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97861113                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41336                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       179384                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              351239329                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       179388                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              351239141                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                          193521                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          4203870                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples          4203916                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            0.021594                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.145354                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.145353                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4113091     97.84%     97.84% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4113137     97.84%     97.84% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                  90779      2.16%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4203870                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3441050999                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4203916                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3441095952                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           260919                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
 system.toL2Bus.respLayer0.occupancy        1872616750                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         760136706                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         760133706                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.toL2Bus.respLayer2.occupancy          11021467                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          48272206                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          48273206                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 653375199..c3b5f0f58 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.822600                       # Number of seconds simulated
-sim_ticks                                2822599892000                       # Number of ticks simulated
-final_tick                               2822599892000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.817566                       # Number of seconds simulated
+sim_ticks                                2817566302500                       # Number of ticks simulated
+final_tick                               2817566302500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133046                       # Simulator instruction rate (inst/s)
-host_op_rate                                   161483                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3211959283                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 588416                       # Number of bytes of host memory used
-host_seconds                                   878.78                       # Real time elapsed on the host
-sim_insts                                   116918246                       # Number of instructions simulated
-sim_ops                                     141908177                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 130714                       # Simulator instruction rate (inst/s)
+host_op_rate                                   158652                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3149885183                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 588664                       # Number of bytes of host memory used
+host_seconds                                   894.50                       # Real time elapsed on the host
+sim_insts                                   116922977                       # Number of instructions simulated
+sim_ops                                     141913965                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         3520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         3776                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           680320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5169248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           692096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4617224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           681792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5202336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           690880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4586120                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11168360                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       680320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       692096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1372416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8444928                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11170792                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       681792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       690880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1372672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8446592                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8462452                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           55                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8464116                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           59                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10630                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             81288                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           77                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10814                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             72146                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10653                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             81805                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           76                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10795                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             71660                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175026                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131952                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175064                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131978                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136333                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1247                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136359                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1340                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              241026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1831378                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              245198                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1635805                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3956763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         241026                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         245198                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             486224                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2991897                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6206                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              241979                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1846393                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1726                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              245205                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1627688                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3964695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         241979                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         245205                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             487184                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2997833                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6217                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2998105                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2991897                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1247                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3004052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2997833                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1340                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             241026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1837584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1746                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             245198                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1635808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6954869                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175027                       # Number of read requests accepted
-system.physmem.writeReqs                       136333                       # Number of write requests accepted
-system.physmem.readBursts                      175027                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     136333                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11191872                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9856                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8475200                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11168424                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8462452                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      154                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::cpu0.inst             241979                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1852610                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             245205                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1627691                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6968747                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175065                       # Number of read requests accepted
+system.physmem.writeReqs                       136359                       # Number of write requests accepted
+system.physmem.readBursts                      175065                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     136359                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11195328                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8832                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8476864                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11170856                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8464116                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      138                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12029                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11047                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10999                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11203                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11530                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11229                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11724                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11678                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10819                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12026                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11043                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11014                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11213                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11525                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11226                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11723                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11697                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10818                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               11281                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              10383                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9840                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10191                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10806                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10203                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9911                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8929                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8449                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8574                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8748                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8391                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8421                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8483                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8696                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9838                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10204                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10800                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10202                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9934                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8926                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8447                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8579                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8754                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8390                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8423                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8479                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8702                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                8251                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8705                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8031                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7697                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7872                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8288                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7672                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7218                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8712                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8030                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7698                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7882                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8282                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7677                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7219                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2822599715500                       # Total gap between requests
+system.physmem.numWrRetry                          24                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2817566126000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  174471                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  174509                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 131952                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    103905                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     62755                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6452                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131978                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    104121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     62577                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      6503                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1707                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -161,137 +161,138 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       111                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                        88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       89                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                       86                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::13                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1923                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2980                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::19                     7424                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21                     6762                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::23                     7693                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::25                     8086                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9038                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7937                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::33                     1191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      247                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::51                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       90                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::54                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       35                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65893                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      298.468851                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     176.439020                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     322.218127                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          25043     38.01%     38.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15993     24.27%     62.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6828     10.36%     72.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3804      5.77%     78.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2929      4.45%     82.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1589      2.41%     85.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1152      1.75%     87.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1015      1.54%     88.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7540     11.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65893                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6529                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.779139                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      488.211156                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6527     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::12                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       84                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                       54                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65817                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      298.891289                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     176.511638                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     322.918519                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24962     37.93%     37.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        16108     24.47%     62.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6699     10.18%     72.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3770      5.73%     78.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2952      4.49%     82.79% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-1023         1102      1.67%     88.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7566     11.50%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65817                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6524                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.807940                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-2047           6522     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6529                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6529                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.282585                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.331559                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.915612                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                13      0.20%      0.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 5      0.08%      0.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                7      0.11%      0.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              17      0.26%      0.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5686     87.09%     87.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             170      2.60%     90.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              40      0.61%     90.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              72      1.10%     92.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              34      0.52%     92.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.31%     92.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              58      0.89%     93.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.18%     93.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             145      2.22%     96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               7      0.11%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              12      0.18%     96.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              68      1.04%     97.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.08%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              23      0.35%     98.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             100      1.53%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.11%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             4      0.06%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.03%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.05%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6529                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2732692250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                6011561000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    874365000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15626.72                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6524                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6524                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.302115                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.296217                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.183093                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                18      0.28%      0.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 6      0.09%      0.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                6      0.09%      0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               9      0.14%      0.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5697     87.32%     87.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             177      2.71%     90.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              43      0.66%     91.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              57      0.87%     92.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              27      0.41%     92.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              20      0.31%     92.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              60      0.92%     93.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.15%     93.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             144      2.21%     96.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              12      0.18%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.08%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              10      0.15%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              63      0.97%     97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               9      0.14%     97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.03%     97.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.40%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              90      1.38%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             3      0.05%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             5      0.08%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.14%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6524                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2763863500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                6043744750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    874635000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15800.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34376.72                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  34550.10                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.01                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
@@ -299,40 +300,40 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.74                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.39                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     143838                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97566                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.66                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9065389.63                       # Average gap between requests
-system.physmem.pageHitRate                      78.55                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  262589040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  143277750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 713224200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                445117680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184358085600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80173196100                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1623228875250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1889324365620                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.357529                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2700270963250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94252600000                       # Time in different power states
+system.physmem.avgWrQLen                        12.81                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     143943                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97617                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.69                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9047363.49                       # Average gap between requests
+system.physmem.pageHitRate                      78.58                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  262097640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  143009625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 713442600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                445176000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184029555840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80250373530                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1620143225250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1885986880485                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.367938                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2695137554500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94084640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     28070184250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28341635500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  235562040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  128530875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 650777400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                412996320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184358085600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79158702690                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1624118781750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1889063436675                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.265086                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2701767276500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94252600000                       # Time in different power states
+system.physmem_1.actEnergy                  235478880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  128485500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 650980200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                413106480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184029555840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            79085591640                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1621164963750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1885708162290                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.269016                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2696848801250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94084640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     26580005000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     26632850750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
@@ -340,31 +341,31 @@ system.realview.nvmem.bytes_inst_read::cpu0.inst          768
 system.realview.nvmem.bytes_inst_read::total          768                       # Number of instructions bytes read from this memory
 system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          272                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              272                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          272                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          272                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          272                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             272                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst          273                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              273                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          273                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          273                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          273                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             273                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               26616996                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13742017                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           493041                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            15603811                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                8045769                       # Number of BTB hits
+system.cpu0.branchPred.lookups               26582301                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13715885                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           494954                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            15490869                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                8022372                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            51.562846                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6633595                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             28274                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        4499378                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           4391333                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses          108045                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted        31802                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            51.787747                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6629975                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             28839                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4497397                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           4389117                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          108280                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        31787                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -395,86 +396,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    58233                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               58233                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17222                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14806                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        26205                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        32028                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   716.310728                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  4455.738407                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383        31643     98.80%     98.80% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767          285      0.89%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151           60      0.19%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    58814                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               58814                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17346                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14926                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        26542                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        32272                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   726.791026                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  4755.027696                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383        31886     98.80%     98.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767          277      0.86%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151           61      0.19%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535           23      0.07%     99.92% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::65536-81919           11      0.03%     99.96% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::98304-114687            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-131071            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::147456-163839            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        32028                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        12683                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13005.479776                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10522.110524                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  9554.054292                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        12456     98.21%     98.21% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535          198      1.56%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-98303            4      0.03%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071           15      0.12%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839            9      0.07%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-131071            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::147456-163839            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::163840-180223            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::180224-196607            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        32272                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12665                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13014.923016                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10587.989224                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  9127.008729                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        12438     98.21%     98.21% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535          206      1.63%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303            5      0.04%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071            9      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            6      0.05%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        12683                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  95295475040                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.626262                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.503838                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  95214863040     99.92%     99.92% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     54562500      0.06%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5     11789500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      5218000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      3107500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11      1725500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       925000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15      2340500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       429500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19       156000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21       103500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23        23000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25       167000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27         8500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29        11000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31        45000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  95295475040                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3556     69.39%     69.39% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1569     30.61%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5125                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58233                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total        12665                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  90261197040                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.667138                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.493122                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  90178529040     99.91%     99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     56487500      0.06%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5     11942500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      4980500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      3127500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1706500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13      1155500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      2289000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       484000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       141500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21        89500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        39000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25       163500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27        25500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29        11500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31        24500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  90261197040                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3551     69.31%     69.31% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1572     30.69%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5123                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58814                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58233                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5125                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58814                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5123                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5125                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        63358                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5123                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        63937                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    14003627                       # DTB read hits
-system.cpu0.dtb.read_misses                     49308                       # DTB read misses
-system.cpu0.dtb.write_hits                   10435159                       # DTB write hits
-system.cpu0.dtb.write_misses                     8925                       # DTB write misses
+system.cpu0.dtb.read_hits                    13996599                       # DTB read hits
+system.cpu0.dtb.read_misses                     49814                       # DTB read misses
+system.cpu0.dtb.write_hits                   10431599                       # DTB write hits
+system.cpu0.dtb.write_misses                     9000                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     465                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3323                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      748                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1266                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3299                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      781                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1241                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      726                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14052935                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10444084                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      730                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14046413                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10440599                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24438786                       # DTB hits
-system.cpu0.dtb.misses                          58233                       # DTB misses
-system.cpu0.dtb.accesses                     24497019                       # DTB accesses
+system.cpu0.dtb.hits                         24428198                       # DTB hits
+system.cpu0.dtb.misses                          58814                       # DTB misses
+system.cpu0.dtb.accesses                     24487012                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -504,807 +507,798 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     7841                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                7841                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2269                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4662                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          910                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         6931                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1597.099986                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  6530.842043                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-8191         6483     93.54%     93.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-16383          245      3.53%     97.07% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-24575          100      1.44%     98.51% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-32767           38      0.55%     99.06% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-40959           21      0.30%     99.37% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-49151           16      0.23%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-57343            8      0.12%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::57344-65535            6      0.09%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-73727            6      0.09%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::73728-81919            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-106495            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         6931                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         3149                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12098.126389                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  9906.288908                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  7800.353471                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2504     79.52%     79.52% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          621     19.72%     99.24% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     7918                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                7918                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2364                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4650                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          904                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         7014                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1709.295694                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  7049.166862                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191         6549     93.37%     93.37% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383          244      3.48%     96.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575          111      1.58%     98.43% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767           40      0.57%     99.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959           16      0.23%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151           20      0.29%     99.52% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-57343            6      0.09%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535           11      0.16%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-73727            6      0.09%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::73728-81919            2      0.03%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::81920-90111            4      0.06%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::90112-98303            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-106495            3      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::114688-122879            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         7014                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         3153                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12090.865842                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9887.284211                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7911.936320                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2500     79.29%     79.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          629     19.95%     99.24% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::32768-49151           19      0.60%     99.84% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::49152-65535            3      0.10%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-114687            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::114688-131071            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         3149                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  35165227396                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.607117                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.488806                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    13821063428     39.30%     39.30% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    21340361468     60.69%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        2726000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         763000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         254500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          59000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  35165227396                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1680     75.03%     75.03% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          559     24.97%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2239                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         3153                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  43016532284                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.690427                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.462733                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    13322631928     30.97%     30.97% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    29689752356     69.02%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        2941500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         833500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         255500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          93500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6          24000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  43016532284                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1677     74.57%     74.57% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          572     25.43%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2249                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7841                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7841                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7918                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7918                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2239                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2239                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        10080                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    20129466                       # ITB inst hits
-system.cpu0.itb.inst_misses                      7841                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2249                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2249                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        10167                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    20135553                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7918                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     465                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     456                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2157                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2166                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1367                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1314                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20137307                       # ITB inst accesses
-system.cpu0.itb.hits                         20129466                       # DTB hits
-system.cpu0.itb.misses                           7841                       # DTB misses
-system.cpu0.itb.accesses                     20137307                       # DTB accesses
-system.cpu0.numCycles                       111772551                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20143471                       # ITB inst accesses
+system.cpu0.itb.hits                         20135553                       # DTB hits
+system.cpu0.itb.misses                           7918                       # DTB misses
+system.cpu0.itb.accesses                     20143471                       # DTB accesses
+system.cpu0.numCycles                       111793147                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          39602252                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     104018130                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   26616996                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19070697                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     66981465                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3101347                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    109391                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                4554                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              495                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       137372                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       131975                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          607                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20127570                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               345492                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   4051                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         108518747                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.151083                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.270431                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          39618267                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     104005693                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   26582301                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19041464                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     66973533                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3106371                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    109142                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                4323                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              492                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       147946                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       134023                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          629                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20133698                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               348335                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   4138                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         108541503                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.150586                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.270795                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                79947267     73.67%     73.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3818944      3.52%     77.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2390633      2.20%     79.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 8016162      7.39%     86.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1540680      1.42%     88.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1082847      1.00%     89.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6027122      5.55%     94.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1035069      0.95%     95.71% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4660023      4.29%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                79990694     73.70%     73.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3816909      3.52%     77.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2386840      2.20%     79.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 8006128      7.38%     86.79% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1535692      1.41%     88.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1070295      0.99%     89.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6024989      5.55%     94.74% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1046446      0.96%     95.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4663510      4.30%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           108518747                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.238135                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.930623                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                27080846                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             63086875                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15439246                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1499474                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1411975                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1879709                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               140548                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              86265439                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               466335                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1411975                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                27919581                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6708694                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      45822380                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16094749                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10561036                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              82571629                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 1978                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1083684                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                247104                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               8473675                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           84960464                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            381127577                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        92351519                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             6511                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             72285025                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                12675423                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1561908                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1463600                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8728047                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            14766139                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11575214                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          2006179                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2797578                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  79563534                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1113915                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 76525093                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            91014                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10394891                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23261666                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        100529                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    108518747                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.705179                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.408066                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           108541503                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.237781                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.930341                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                27078357                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             63118683                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15442618                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1487824                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1413697                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1876108                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               141386                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              86216951                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               468944                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1413697                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27917312                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6737317                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      45777609                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16085983                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10609270                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              82519213                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 1975                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1079762                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                279653                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8498365                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           84889546                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            380829987                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        92265906                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             6437                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             72096231                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                12793299                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1560839                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1462535                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8709532                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            14755108                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11569793                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          2006584                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2797109                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  79506629                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1117012                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 76470203                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            91035                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10513087                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     23255127                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        107098                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    108541503                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.704525                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.408140                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           77980499     71.86%     71.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10237558      9.43%     81.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7702853      7.10%     88.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6507672      6.00%     94.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2342197      2.16%     96.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1521714      1.40%     97.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1465392      1.35%     99.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             497793      0.46%     99.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             263069      0.24%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           78039194     71.90%     71.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10217369      9.41%     81.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7697876      7.09%     88.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6506516      5.99%     94.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2324489      2.14%     96.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1523922      1.40%     97.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1470166      1.35%     99.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             496796      0.46%     99.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             265175      0.24%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      108518747                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      108541503                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 115286     10.03%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     2      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                533290     46.39%     56.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               501036     43.58%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 114394     10.01%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                533468     46.67%     56.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               495163     43.32%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass              257      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             51005106     66.65%     66.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57020      0.07%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4013      0.01%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14388531     18.80%     85.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           11070162     14.47%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             1057      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             50961896     66.64%     66.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57056      0.07%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4042      0.01%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14381965     18.81%     85.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           11064184     14.47%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              76525093                       # Type of FU issued
-system.cpu0.iq.rate                          0.684650                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1149614                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.015023                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         262795692                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         91116693                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     74267630                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              13869                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              8272                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         6120                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              77667016                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   7434                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          356348                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              76470203                       # Type of FU issued
+system.cpu0.iq.rate                          0.684033                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1143026                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.014947                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         262701898                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         91181243                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     74205181                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              14072                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              8084                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         6077                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              77604626                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7546                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          356476                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2003014                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2146                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        53724                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1008418                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2025396                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2046                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        53693                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1019422                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       205247                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       123541                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       206190                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       120975                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1411975                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5317808                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1170288                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           80797143                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           102579                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             14766139                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11575214                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            569653                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 44979                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1113707                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         53724                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        203717                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       217691                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              421408                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             75980075                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14169520                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           486959                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1413697                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5422271                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1092121                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           80743722                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           103923                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             14755108                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11569793                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            575298                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 45368                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1034932                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         53693                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        203963                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       218205                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              422168                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             75920997                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14162652                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           490566                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       119694                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    25144307                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14085484                       # Number of branches executed
-system.cpu0.iew.exec_stores                  10974787                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.679774                       # Inst execution rate
-system.cpu0.iew.wb_sent                      75414321                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     74273750                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 38951887                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 68092338                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.664508                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.572045                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10417951                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1013386                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           354305                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    106111246                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.663072                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.565077                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       120081                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    25131819                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14053120                       # Number of branches executed
+system.cpu0.iew.exec_stores                  10969167                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.679120                       # Inst execution rate
+system.cpu0.iew.wb_sent                      75353130                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     74211258                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 38909862                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 67987561                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.663827                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.572309                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10505736                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1009914                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           355428                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    106122323                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.661384                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.563144                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     78913412     74.37%     74.37% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12236512     11.53%     85.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6105044      5.75%     91.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2654450      2.50%     94.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1291559      1.22%     95.37% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       838114      0.79%     96.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1777849      1.68%     97.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       428900      0.40%     98.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1865406      1.76%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     78982453     74.43%     74.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12211696     11.51%     85.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6095376      5.74%     91.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2654698      2.50%     94.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1273985      1.20%     95.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       842007      0.79%     96.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1777365      1.67%     97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       427049      0.40%     98.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1857694      1.75%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    106111246                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            58013653                       # Number of instructions committed
-system.cpu0.commit.committedOps              70359398                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    106122323                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            57860770                       # Number of instructions committed
+system.cpu0.commit.committedOps              70187602                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      23329921                       # Number of memory references committed
-system.cpu0.commit.loads                     12763125                       # Number of loads committed
-system.cpu0.commit.membars                     416120                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13382810                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5642                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 61776783                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2631243                       # Number of function calls committed.
+system.cpu0.commit.refs                      23280083                       # Number of memory references committed
+system.cpu0.commit.loads                     12729712                       # Number of loads committed
+system.cpu0.commit.membars                     412824                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13343572                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5690                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 61639242                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2627168                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        46969916     66.76%     66.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55548      0.08%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4013      0.01%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12763125     18.14%     84.98% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10566796     15.02%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        46847826     66.75%     66.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55651      0.08%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4042      0.01%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12729712     18.14%     84.97% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10550371     15.03%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         70359398                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1865406                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   172653686                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  163961445                       # The number of ROB writes
-system.cpu0.timesIdled                         387576                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3253804                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2105668651                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   57936809                       # Number of Instructions Simulated
-system.cpu0.committedOps                     70282554                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.929215                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.929215                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.518346                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.518346                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                82848883                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               47347730                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    16917                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13431                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                268451571                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                27744432                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              149385288                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                777097                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           854224                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.968814                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42339027                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           854736                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.534625                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        186719500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   247.066049                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   264.902765                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.482551                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.517388                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total         70187602                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1857694                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   172582589                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  163805074                       # The number of ROB writes
+system.cpu0.timesIdled                         387475                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3251644                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2095657765                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   57783718                       # Number of Instructions Simulated
+system.cpu0.committedOps                     70110550                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.934682                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.934682                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.516881                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.516881                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                82769836                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               47340037                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16967                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13430                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                268235222                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                27675650                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              149360983                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                774294                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           854223                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.975115                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42339802                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           854735                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.535589                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        151893500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   245.630516                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   266.344600                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.479747                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.520204                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999951                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189179253                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189179253                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12336272                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12826656                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25162928                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7919461                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      7984444                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15903905                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       182552                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180556                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       363108                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       229758                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       216608                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446366                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236004                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       223300                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459304                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20255733                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     20811100                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41066833                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20438285                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     20991656                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41429941                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       442915                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       396796                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       839711                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1873310                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1821129                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3694439                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117650                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        65870                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       183520                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13470                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        189188933                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189188933                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12328240                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     12835653                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25163893                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      7920383                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total      15903947                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       182811                       # number of SoftPFReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total       363076                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       228283                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       217996                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       446279                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       234405                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       224906                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       459311                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20248623                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     20819217                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41067840                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20431434                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     20999482                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       41430916                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       442900                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       840558                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1859287                       # number of WriteReq misses
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+system.cpu0.dcache.WriteReq_misses::total      3695168                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       116986                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        66485                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       183471                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13472                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14295                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27765                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           38                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           41                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           79                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2316225                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2217925                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4534150                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2433875                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2283795                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4717670                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7322202500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7290660500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14612863000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133766411504                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 118455634259                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 252222045763                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    214289000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    197755000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    412044000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      1125000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1641500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      2766500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 141088614004                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 125746294759                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 266834908763                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 141088614004                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 125746294759                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 266834908763                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     12779187                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13223452                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26002639                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9792771                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9805573                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19598344                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       300202                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       246426                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       546628                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       243228                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230903                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       474131                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236042                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223341                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459383                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22571958                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23029025                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45600983                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22872160                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23275451                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46147611                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034659                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030007                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032293                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191295                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185724                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188508                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.391903                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.267301                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335731                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055380                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061909                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058560                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000161                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000184                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000172                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102615                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096310                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.099431                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106412                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098120                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.102230                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16531.845839                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18373.825593                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17402.252680                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71406.447146                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 65045.163884                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 68270.729538                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15908.611730                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13833.857992                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14840.410589                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 29605.263158                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 40036.585366                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 35018.987342                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 60913.172945                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 56695.467502                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 58850.039977                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 57968.718198                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 55060.237350                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 56560.740527                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1654202                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       345656                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            52729                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           2989                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.371769                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   115.642690                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       704118                       # number of writebacks
-system.cpu0.dcache.writebacks::total           704118                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       232529                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       180764                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       413293                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1722359                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1672656                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3395015                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9004                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9776                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18780                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1954888                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1853420                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3808308                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1954888                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1853420                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3808308                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210386                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       216032                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       426418                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       150951                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       148473                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299424                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74802                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48133                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       122935                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4466                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4519                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8985                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           38                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           41                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           79                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       361337                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       364505                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       725842                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       436139                       # number of overall MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total       848777                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14870                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16259                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.LoadLockedReq_misses::total        27767                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           32                       # number of StoreCondReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total           75                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2302187                       # number of demand (read+write) misses
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+system.cpu0.dcache.demand_misses::total       4535726                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2419173                       # number of overall misses
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+system.cpu0.dcache.overall_misses::total      4719197                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7358360000                       # number of ReadReq miss cycles
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+system.cpu0.dcache.ReadReq_miss_latency::total  14580767500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 134221650085                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 118315842261                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 252537492346                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    214336000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    197120000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    411456000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       910500                       # number of StoreCondReq miss cycles
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+system.cpu0.dcache.StoreCondReq_miss_latency::total      2784500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 141580010085                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 125538249761                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 267118259846                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 141580010085                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 125538249761                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 267118259846                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     12771140                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13233311                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9779670                       # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       299797                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       246750                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       546547                       # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       232291                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       474046                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::total     45603566                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     22850607                       # number of overall (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total     46150113                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034680                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030050                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032324                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.190118                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.186964                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188537                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.390217                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.269443                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335691                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055726                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061539                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058574                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000136                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000191                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000163                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102089                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096888                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.099460                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.105869                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098716                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.102258                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16614.043802                       # average ReadReq miss latency
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+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17346.533493                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 72189.850241                       # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15909.738717                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13789.436866                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14818.165448                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28453.125000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 43581.395349                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 37126.666667                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61498.049500                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 56205.980626                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 58892.062670                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 58524.136176                       # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 56602.481279                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1652801                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       341100                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            53373                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           2981                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    30.966987                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   114.424690                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       704221                       # number of writebacks
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+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1941716                       # number of demand (read+write) MSHR hits
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 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15297                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12291                       # number of WriteReq MSHR uncacheable
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+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12235                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30167                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28550                       # number of overall MSHR uncacheable misses
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 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3362092000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3357394000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6719486000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10934577332                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  10063021934                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  20997599266                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1126321500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    742845500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1869167000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     90886000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61004000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    151890000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1087000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1600500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2687500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14296669332                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13420415934                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  27717085266                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15422990832                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14163261434                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  29586252266                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2991260000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3309772500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301032500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2610677924                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2474267452                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084945376                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5601937924                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5784039952                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11385977876                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016463                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016337                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016399                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015415                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015142                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015278                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.249172                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.195324                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224897                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018361                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019571                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018950                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000161                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000184                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000172                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016008                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015828                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015917                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019069                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017728                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3376686000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3344381500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6721067500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10980513336                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  10043251436                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21023764772                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1117542000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    750771500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1868313500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     92062500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     58470500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    150533000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       878500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1831000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2709500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14357199336                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13387632936                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  27744832272                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15474741336                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14138404436                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  29613145772                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3016953500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3284093000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301046500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3016953500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3284093000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6301046500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016480                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016324                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016401                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015338                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015221                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015279                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.247628                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.197224                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224872                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018887                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.018623                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018758                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000136                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000191                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000163                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015985                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015854                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015919                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019024                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017775                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.018393                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15980.588062                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15541.188342                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15757.979260                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 72437.925764                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 67776.780519                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70126.640703                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15057.371461                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15433.185133                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15204.514581                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20350.649351                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13499.446780                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16904.841402                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 28605.263158                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 39036.585366                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34018.987342                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39566.026540                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36818.194357                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38186.113873                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35362.558340                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34323.696397                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34857.509412                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201160.726295                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203565.563688                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202416.797841                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170666.007975                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201307.253437                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184317.289256                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185697.547784                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202593.343327                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193912.799973                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1939563                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.473934                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           38722182                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1940075                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            19.959116                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      11152079500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   204.334938                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   307.138996                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.399092                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.599881                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998973                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16043.550150                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15481.814184                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.027175                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73202.934220                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 67196.019296                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70204.882647                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15053.503597                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15427.339977                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15201.528848                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20162.614980                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13516.065650                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16929.037337                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27453.125000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 42581.395349                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36126.666667                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39828.999659                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36630.074630                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38218.496613                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35597.931803                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34138.613671                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34885.947407                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201452.557425                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203311.644896                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202417.247583                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 99474.216097                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115685.958856                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107312.132772                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.replacements          1940234                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.477808                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           38724516                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1940746                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            19.953418                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      11116168500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   198.827128                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   312.650680                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.388334                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.610646                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998980                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          165                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42750946                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42750946                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19115401                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19606781                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       38722182                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19115401                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19606781                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        38722182                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19115401                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19606781                       # number of overall hits
-system.cpu0.icache.overall_hits::total       38722182                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1011498                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1077049                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2088547                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1011498                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1077049                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2088547                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1011498                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1077049                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2088547                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14396633977                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15378251986                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  29774885963                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14396633977                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  15378251986                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  29774885963                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14396633977                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  15378251986                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  29774885963                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20126899                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20683830                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     40810729                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20126899                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20683830                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     40810729                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     20126899                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20683830                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     40810729                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050256                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.052072                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.051176                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050256                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.052072                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.051176                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050256                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.052072                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.051176                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14232.983137                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14278.135894                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14256.268096                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14232.983137                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14278.135894                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14256.268096                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14232.983137                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14278.135894                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14256.268096                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        20294                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         42755477                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42755477                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19119275                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19605241                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       38724516                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     19119275                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     19605241                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        38724516                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     19119275                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19605241                       # number of overall hits
+system.cpu0.icache.overall_hits::total       38724516                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1013751                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1076327                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2090078                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1013751                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1076327                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2090078                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1013751                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1076327                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2090078                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14430104978                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15364755477                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  29794860455                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14430104978                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  15364755477                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  29794860455                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14430104978                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  15364755477                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  29794860455                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     20133026                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     20681568                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     40814594                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     20133026                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     20681568                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     40814594                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     20133026                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     20681568                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     40814594                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050353                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.052043                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.051209                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050353                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.052043                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.051209                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050353                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.052043                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.051209                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14234.368181                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14275.174252                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14255.382074                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14234.368181                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14275.174252                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14255.382074                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14234.368181                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14275.174252                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14255.382074                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        21109                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              818                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              839                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.809291                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.159714                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1939563                       # number of writebacks
-system.cpu0.icache.writebacks::total          1939563                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71879                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76450                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       148329                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        71879                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        76450                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       148329                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        71879                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        76450                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       148329                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       939619                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1000599                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1940218                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       939619                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1000599                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1940218                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       939619                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1000599                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1940218                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1940234                       # number of writebacks
+system.cpu0.icache.writebacks::total          1940234                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        72829                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76365                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       149194                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        72829                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        76365                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       149194                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        72829                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        76365                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       149194                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       940922                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       999962                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1940884                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       940922                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       999962                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1940884                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       940922                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       999962                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1940884                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12628351483                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13458642491                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  26086993974                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12628351483                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13458642491                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  26086993974                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12628351483                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13458642491                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  26086993974                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86307500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86307500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86307500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total     86307500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047542                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047542                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047542                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13445.393236                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13445.393236                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13445.393236                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129396.551724                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129396.551724                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27771206                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14500509                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           522402                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17226329                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                8535757                       # Number of BTB hits
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12649517983                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13451239983                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  26100757966                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12649517983                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13451239983                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  26100757966                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12649517983                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13451239983                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  26100757966                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     85612500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     85612500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     85612500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total     85612500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046735                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048350                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047554                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046735                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048350                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047554                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046735                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048350                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047554                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13443.747710                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13451.751150                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13447.871159                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13443.747710                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13451.751150                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13447.871159                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13443.747710                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13451.751150                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13447.871159                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 128354.572714                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 128354.572714                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 128354.572714                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 128354.572714                       # average overall mshr uncacheable latency
+system.cpu1.branchPred.lookups               27807268                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14522614                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           521884                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17250489                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                8558251                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            49.550644                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6833635                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             30645                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        4632770                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           4521609                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses          111161                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        32231                       # Number of mispredicted indirect branches.
+system.cpu1.branchPred.BTBHitPct            49.611643                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6837595                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             30253                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4638011                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           4524834                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses          113177                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        32246                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1334,85 +1328,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    59668                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               59668                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19466                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14180                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore        26022                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        33646                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   657.210367                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  4292.478693                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383        33233     98.77%     98.77% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767          307      0.91%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151           64      0.19%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535           23      0.07%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    59403                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               59403                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19503                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14179                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        25721                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        33682                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   625.541832                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  4121.027251                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383        33293     98.85%     98.85% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767          302      0.90%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151           51      0.15%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.94% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::98304-114687            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::114688-131071            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::147456-163839            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        33646                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        13510                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14754.441155                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12483.879781                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8047.547321                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         9092     67.30%     67.30% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767         4121     30.50%     97.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151          269      1.99%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535           27      0.20%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::total        33682                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        13282                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 14572.202981                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12211.597102                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  8282.780589                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         9027     67.96%     67.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767         3941     29.67%     97.64% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151          289      2.18%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535           20      0.15%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-98303            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-114687            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        13510                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  94672983040                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.774011                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.442469                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  94586502540     99.91%     99.91% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     59948000      0.06%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5     13676000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      4818000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9      2374500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11      1378000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       809000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15      2250500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       491500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19       205500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21       133000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23        51500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25       144500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27        33000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29        26000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31       141500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  94672983040                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3789     68.70%     68.70% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1726     31.30%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5515                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59668                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total        13282                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  93940791836                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.786357                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.432735                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  93856164336     99.91%     99.91% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     59118500      0.06%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5     13540500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      4598500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9      2377500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11      1150500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       641500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15      2158000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       464500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19       154000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21       113500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23        32000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25       104000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27        24000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29        20500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31       130000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  93940791836                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3783     68.79%     68.79% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1716     31.21%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5499                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59403                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59668                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5515                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59403                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5499                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5515                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        65183                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5499                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        64902                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14351950                       # DTB read hits
-system.cpu1.dtb.read_misses                     51492                       # DTB read misses
-system.cpu1.dtb.write_hits                   10462781                       # DTB write hits
-system.cpu1.dtb.write_misses                     8176                       # DTB write misses
+system.cpu1.dtb.read_hits                    14363291                       # DTB read hits
+system.cpu1.dtb.read_misses                     51304                       # DTB read misses
+system.cpu1.dtb.write_hits                   10466548                       # DTB write hits
+system.cpu1.dtb.write_misses                     8099                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     452                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3688                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      817                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1295                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3703                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      789                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1302                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      676                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14403442                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10470957                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      692                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14414595                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10474647                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         24814731                       # DTB hits
-system.cpu1.dtb.misses                          59668                       # DTB misses
-system.cpu1.dtb.accesses                     24874399                       # DTB accesses
+system.cpu1.dtb.hits                         24829839                       # DTB hits
+system.cpu1.dtb.misses                          59403                       # DTB misses
+system.cpu1.dtb.accesses                     24889242                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1442,214 +1439,217 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     8103                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                8103                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2668                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4534                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walks                     8176                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                8176                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2725                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4550                       # Level at which table walker walks with short descriptors terminate
 system.cpu1.itb.walker.walksSquashedBefore          901                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         7202                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1511.663427                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  6714.706424                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191         6781     94.15%     94.15% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383          223      3.10%     97.25% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575           95      1.32%     98.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767           31      0.43%     99.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959           22      0.31%     99.31% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151           21      0.29%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343            6      0.08%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535            5      0.07%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727            5      0.07%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::73728-81919            4      0.06%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::90112-98303            3      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-106495            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::106496-114687            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         7202                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         3356                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13427.145411                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11321.856073                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  7351.367505                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          969     28.87%     28.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383         1595     47.53%     76.40% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575          704     20.98%     97.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           60      1.79%     99.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959           15      0.45%     99.61% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151           10      0.30%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.06%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-106495            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         3356                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  30238902600                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.763443                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.425547                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     7158457500     23.67%     23.67% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    23076737600     76.31%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2        2728500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         531500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         338000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5         109500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  30238902600                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1852     75.44%     75.44% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          603     24.56%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2455                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkWaitTime::samples         7275                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1291.065292                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  5441.618044                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         6876     94.52%     94.52% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          235      3.23%     97.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575           98      1.35%     99.09% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           22      0.30%     99.40% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959           16      0.22%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151           13      0.18%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343            4      0.05%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            4      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::73728-81919            3      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::90112-98303            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         7275                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         3329                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13317.062181                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11226.218881                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  7219.287794                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095           33      0.99%      0.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          951     28.57%     29.56% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          591     17.75%     47.31% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          974     29.26%     76.57% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           56      1.68%     78.25% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575          639     19.19%     97.45% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           50      1.50%     98.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            7      0.21%     99.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            8      0.24%     99.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            9      0.27%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            7      0.21%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            2      0.06%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         3329                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  16626242508                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.560807                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.496851                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     7305801500     43.94%     43.94% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1     9317469508     56.04%     99.98% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        2523000      0.02%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         191000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         257500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  16626242508                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1825     75.16%     75.16% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          603     24.84%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2428                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8103                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8103                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8176                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8176                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2455                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2455                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        10558                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    20686520                       # ITB inst hits
-system.cpu1.itb.inst_misses                      8103                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2428                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2428                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        10604                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20684254                       # ITB inst hits
+system.cpu1.itb.inst_misses                      8176                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     452                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     461                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2423                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2403                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1387                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1403                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20694623                       # ITB inst accesses
-system.cpu1.itb.hits                         20686520                       # DTB hits
-system.cpu1.itb.misses                           8103                       # DTB misses
-system.cpu1.itb.accesses                     20694623                       # DTB accesses
-system.cpu1.numCycles                       114249642                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20692430                       # ITB inst accesses
+system.cpu1.itb.hits                         20684254                       # DTB hits
+system.cpu1.itb.misses                           8176                       # DTB misses
+system.cpu1.itb.accesses                     20692430                       # DTB accesses
+system.cpu1.numCycles                       114171883                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          41315815                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     106868458                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27771206                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19891001                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     67522618                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3218365                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    120489                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                7203                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              373                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       155077                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       135282                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          428                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20683839                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               366531                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   4147                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         110866430                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.159053                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.270352                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          41307055                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     106903297                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27807268                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19920680                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     67458241                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3216021                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    121509                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                7142                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              400                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       160606                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       131997                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          578                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20681575                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               364929                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   4168                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         110795501                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.160287                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.270583                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                81385669     73.41%     73.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3966024      3.58%     76.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2458990      2.22%     79.20% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8216379      7.41%     86.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1659206      1.50%     88.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1099479      0.99%     89.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6321498      5.70%     94.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1169763      1.06%     95.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4589422      4.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                81287702     73.37%     73.37% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3968445      3.58%     76.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2465737      2.23%     79.17% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8227247      7.43%     86.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1665467      1.50%     88.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1110283      1.00%     89.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6325144      5.71%     94.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1155008      1.04%     95.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4590468      4.14%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           110866430                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.243075                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.935394                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                28349810                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             63611088                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15737668                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1707179                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1460344                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1943796                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               150726                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              88547543                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               497407                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1460344                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                29270752                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                6941234                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      46643920                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16512645                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             10037169                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              84769560                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 3293                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1700452                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                295960                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               7294084                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           88006736                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            389941348                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        94160116                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             6639                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             74402972                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13603764                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1570437                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1473591                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  9835455                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15202584                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11508546                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2153155                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2847808                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  81703406                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1095595                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 78289936                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            93469                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       11173378                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     24596663                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        114922                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    110866430                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.706164                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.396793                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           110795501                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.243556                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.936336                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                28346426                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             63534954                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15742282                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1712283                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1459261                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1949115                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               150539                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              88605226                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               497888                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1459261                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                29272328                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                6824679                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      46697941                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16517482                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             10023500                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              84831585                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 5826                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1700956                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                268416                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               7295598                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           88095005                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            390290446                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        94261831                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             6556                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             74597964                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13497041                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1571787                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1475121                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  9868182                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15213702                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11513965                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2143340                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2824110                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  81772790                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1092881                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 78357937                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            92895                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       11062256                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     24614502                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        108703                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    110795501                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.707230                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.397571                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           79351505     71.57%     71.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10562137      9.53%     81.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8130695      7.33%     88.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6659293      6.01%     94.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2446771      2.21%     96.65% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1483581      1.34%     97.99% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1548529      1.40%     99.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             478985      0.43%     99.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             204934      0.18%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           79253115     71.53%     71.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10577284      9.55%     81.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8128095      7.34%     88.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6656902      6.01%     94.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2466913      2.23%     96.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1485866      1.34%     97.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1541530      1.39%     99.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             478773      0.43%     99.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             207023      0.19%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      110866430                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      110795501                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  95398      8.54%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     6      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                529553     47.39%     55.93% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               492367     44.07%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  96333      8.58%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     5      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                530832     47.29%     55.88% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               495255     44.12%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             2080      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             52483936     67.04%     67.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               59147      0.08%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             1280      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             52536411     67.05%     67.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59049      0.08%     67.12% # Type of FU issued
 system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.12% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.12% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.12% # Type of FU issued
@@ -1672,152 +1672,152 @@ system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.12% # Ty
 system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.12% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.12% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4561      0.01%     67.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     67.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14738514     18.83%     85.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11001690     14.05%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4537      0.01%     67.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14749265     18.82%     85.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11007390     14.05%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              78289936                       # Type of FU issued
-system.cpu1.iq.rate                          0.685253                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1117324                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014272                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         268642821                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         94014634                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     76000311                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              14274                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              8222                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6128                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              79397497                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7683                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          354386                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              78357937                       # Type of FU issued
+system.cpu1.iq.rate                          0.686316                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1122425                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014324                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         268712676                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         93970035                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     76074139                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              14019                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              8104                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6058                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              79471535                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7547                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          353893                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2162238                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2091                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        51645                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1037860                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2138712                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2178                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        51387                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1026051                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       208157                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        79710                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       208095                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        80598                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1460344                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5576526                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1063680                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           82916416                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           111836                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15202584                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11508546                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            564987                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 44159                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1006496                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         51645                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        224871                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       227319                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              452190                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             77723399                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14509905                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           506997                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1459261                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                5474450                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1047007                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           82982431                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           112348                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15213702                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11513965                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            559325                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 44311                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               989592                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         51387                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        224281                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       227429                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              451710                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             77795994                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14521150                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           502664                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       117415                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25415143                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14757344                       # Number of branches executed
-system.cpu1.iew.exec_stores                  10905238                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.680294                       # Inst execution rate
-system.cpu1.iew.wb_sent                      77189704                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     76006439                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 39824876                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 69384097                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.665266                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.573977                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       11134037                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         980673                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           373526                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    108332250                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.661887                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.544752                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       116760                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25431924                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14791580                       # Number of branches executed
+system.cpu1.iew.exec_stores                  10910774                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.681394                       # Inst execution rate
+system.cpu1.iew.wb_sent                      77262283                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     76080197                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 39863669                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 69476168                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.666365                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.573775                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       11052926                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         984178                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           373097                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    108271763                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.663897                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.547392                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     80307491     74.13%     74.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12497635     11.54%     85.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6520784      6.02%     91.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2657688      2.45%     94.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1393058      1.29%     95.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       929919      0.86%     96.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1912801      1.77%     98.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       410208      0.38%     98.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1702666      1.57%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     80200179     74.07%     74.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12516978     11.56%     85.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6520368      6.02%     91.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2652401      2.45%     94.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1417496      1.31%     95.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       923552      0.85%     96.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1918077      1.77%     98.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       411551      0.38%     98.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1711161      1.58%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    108332250                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            59059498                       # Number of instructions committed
-system.cpu1.commit.committedOps              71703684                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    108271763                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            59217112                       # Number of instructions committed
+system.cpu1.commit.committedOps              71881268                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23511032                       # Number of memory references committed
-system.cpu1.commit.loads                     13040346                       # Number of loads committed
-system.cpu1.commit.membars                     397932                       # Number of memory barriers committed
-system.cpu1.commit.branches                  13998335                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5786                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 62664719                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2706612                       # Number of function calls committed.
+system.cpu1.commit.refs                      23562904                       # Number of memory references committed
+system.cpu1.commit.loads                     13074990                       # Number of loads committed
+system.cpu1.commit.membars                     401228                       # Number of memory barriers committed
+system.cpu1.commit.branches                  14038691                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5738                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 62807538                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2710976                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        48130630     67.12%     67.12% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57462      0.08%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4560      0.01%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       13040346     18.19%     85.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10470686     14.60%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        48256450     67.13%     67.13% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57377      0.08%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4537      0.01%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       13074990     18.19%     85.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10487914     14.59%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         71703684                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1702666                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   176703276                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  168209083                       # The number of ROB writes
-system.cpu1.timesIdled                         415823                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        3383212                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3313474839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   58981437                       # Number of Instructions Simulated
-system.cpu1.committedOps                     71625623                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.937044                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.937044                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.516251                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.516251                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                84346535                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               48387599                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    17183                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   13302                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                274779775                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29204766                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              152559581                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                742832                       # number of misc regfile writes
+system.cpu1.commit.op_class_0::total         71881268                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1711161                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   176735150                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  168391360                       # The number of ROB writes
+system.cpu1.timesIdled                         416029                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        3376382                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3313480178                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   59139259                       # Number of Instructions Simulated
+system.cpu1.committedOps                     71803415                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.930560                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.930560                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.517984                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.517984                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                84439414                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               48406893                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    17104                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13298                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                275043982                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                29275058                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              152546731                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                745677                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
@@ -1868,33 +1868,33 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             49488500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             49489000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               334000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               335500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                87000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               605000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               612500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
@@ -1902,25 +1902,25 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6450500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6433500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38437500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38433500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187145990                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187130237                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36423                       # number of replacements
-system.iocache.tags.tagsinuse                1.065406                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.038891                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         236452882000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.065406                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.066588                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.066588                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         236424190000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.038891                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064931                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064931                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1930,26 +1930,26 @@ system.iocache.ReadReq_misses::realview.ide          233                       #
 system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          233                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               233                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          233                       # number of overall misses
-system.iocache.overall_misses::total              233                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28955877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28955877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4552500113                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4552500113                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28955877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28955877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28955877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28955877                       # number of overall miss cycles
+system.iocache.demand_misses::realview.ide        36457                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36457                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36457                       # number of overall misses
+system.iocache.overall_misses::total            36457                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     30201377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     30201377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4553154860                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4553154860                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4583356237                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4583356237                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4583356237                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4583356237                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          233                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             233                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          233                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            233                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36457                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36457                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36457                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36457                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1958,40 +1958,38 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124274.150215                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124274.150215                       # average ReadReq miss latency
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+system.iocache.overall_avg_miss_latency::total 125719.511671                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
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 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
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 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
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 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
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 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2000,526 +1998,516 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
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+system.l2c.ReadReq_miss_rate::total          0.001574                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.962629                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.950104                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.956594                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.218750                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.441860                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.346667                       # miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_miss_rate::total        0.471386                       # miss rate for ReadExReq accesses
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+system.l2c.ReadCleanReq_miss_rate::total     0.010723                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029261                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.025658                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.027525                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136461.038961                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   825.827815                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1266.764923                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1034.530869                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 25944.444444                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 48968.750000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        40680                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 133180.606630                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133781.955397                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 133465.997810                       # average ReadExReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::total 133346.512474                       # average ReadCleanReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::total  1034.554974                       # average UpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95762                       # number of writebacks
-system.l2c.writebacks::total                    95762                       # number of writebacks
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 system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
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-system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1357                       # number of UpgradeReq MSHR misses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.947626                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.952808                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010810                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010719                       # mshr miss rate for ReadCleanReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::total     0.956594                       # mshr miss rate for UpgradeReq accesses
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 system.l2c.demand_mshr_miss_rate::total      0.061048                       # mshr miss rate for demand accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636                       # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67994.841562                       # average UpgradeReq mshr miss latency
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 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124177.716751                       # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124190.331467                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123606.554411                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126822.368421                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123110.977304                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124418.025167                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 123949.059578                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131813.559322                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123510.775255                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122830.035232                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124177.716751                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 123776.078495                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188657.262946                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191062.303955                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188314.253271                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159027.717853                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189801.073957                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172737.857039                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173632.794113                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190519.334501                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 181077.933400                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124190.331467                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123606.554411                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126822.368421                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123110.977304                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124418.025167                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 123949.059578                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112802.098951                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188949.185363                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190808.178047                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188296.216505                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112802.098951                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 93300.240694                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 108571.385797                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 100819.522093                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               31796                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68170                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68183                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       131952                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8761                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4667                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq             25                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131978                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8769                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4666                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq             26                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137941                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137941                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36375                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137965                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137965                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36388                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468049                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       575633                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468158                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       575742                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72895                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72895                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 648528                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 648637                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17313692                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17477749                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17317788                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17481845                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19794869                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              502                       # Total snoops (count)
-system.membus.snoop_fanout::samples            415341                       # Request fanout histogram
+system.membus.pkt_size::total                19798965                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              501                       # Total snoops (count)
+system.membus.snoop_fanout::samples            415426                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  415341    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  415426    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              415341                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95676000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              415426                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95665000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1708000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1698498                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           923138375                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           923038607                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1006417999                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1006596250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1266123                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1263123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2562,60 +2550,60 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5630525                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2835578                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        46774                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            561                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          561                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5631885                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2836272                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        46849                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            558                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          558                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             149785                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2648524                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             150344                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2649691                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       836080                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1939563                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          158867                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            3009                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            79                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           3088                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296443                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296443                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1940218                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       558543                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       836223                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1940234                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          158771                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2995                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            75                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           3070                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296500                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296500                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1940884                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       558486                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5820932                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2687552                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37507                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       166977                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8712968                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    248323008                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99964405                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        56712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       289268                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              348633393                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          209286                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3152616                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.027333                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.163051                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5822943                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2687514                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37786                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       167187                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8715430                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    248409088                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99970933                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        57188                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       288512                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              348725721                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          209954                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3153965                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.027355                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.163116                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                3066446     97.27%     97.27% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  86170      2.73%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                3067688     97.26%     97.26% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  86277      2.74%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3152616                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         5542088496                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3153965                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5543895402                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           378877                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           377377                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2913039562                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2914118404                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1329029128                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1329027112                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          23370914                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          23521931                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          95118571                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          95501099                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 3367a33d1..7463dd4c7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.535940                       # Nu
 sim_ticks                                47535940136000                       # Number of ticks simulated
 final_tick                               47535940136000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 225035                       # Simulator instruction rate (inst/s)
-host_op_rate                                   264677                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            11911388135                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 769700                       # Number of bytes of host memory used
-host_seconds                                  3990.80                       # Real time elapsed on the host
+host_inst_rate                                 200561                       # Simulator instruction rate (inst/s)
+host_op_rate                                   235891                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            10615931561                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 769436                       # Number of bytes of host memory used
+host_seconds                                  4477.79                       # Real time elapsed on the host
 sim_insts                                   898069628                       # Number of instructions simulated
 sim_ops                                    1056270581                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -647,10 +647,10 @@ system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1877481
 system.cpu0.dcache.LoadLockedReq_hits::total      1877481                       # number of LoadLockedReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1849167                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      1849167                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    164286110                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       164286110                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    164591140                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      164591140                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data    164573170                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       164573170                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    164878200                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      164878200                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      3693348                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      3693348                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data      2460225                       # number of WriteReq misses
@@ -663,10 +663,10 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       173543
 system.cpu0.dcache.LoadLockedReq_misses::total       173543                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data       200600                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total       200600                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      6153573                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6153573                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6815315                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6815315                       # number of overall misses
+system.cpu0.dcache.demand_misses::cpu0.data      7001465                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       7001465                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      7663207                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      7663207                       # number of overall misses
 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  64125292500                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::total  64125292500                       # number of ReadReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  62047058000                       # number of WriteReq miss cycles
@@ -679,10 +679,10 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5699610500
 system.cpu0.dcache.StoreCondReq_miss_latency::total   5699610500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5746000                       # number of StoreCondFailReq miss cycles
 system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5746000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 126172350500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 126172350500                       # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 177339794500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 177339794500                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     90736709                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     90736709                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data     79702974                       # number of WriteReq accesses(hits+misses)
@@ -695,10 +695,10 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2051024
 system.cpu0.dcache.LoadLockedReq_accesses::total      2051024                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2049767                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total      2049767                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    170439683                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    170439683                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    171406455                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    171406455                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data    171574635                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    171574635                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    172541407                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    172541407                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040704                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.040704                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.030867                       # miss rate for WriteReq accesses
@@ -711,10 +711,10 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.084613
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.084613                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097865                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097865                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036104                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.036104                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.039761                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.039761                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.040807                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.040807                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.044414                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.044414                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870                       # average ReadReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587                       # average WriteReq miss latency
@@ -727,18 +727,16 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      5972043                       # number of writebacks
 system.cpu0.dcache.writebacks::total          5972043                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       444932                       # number of ReadReq MSHR hits
@@ -751,10 +749,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        46565
 system.cpu0.dcache.LoadLockedReq_mshr_hits::total        46565                       # number of LoadLockedReq MSHR hits
 system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           65                       # number of StoreCondReq MSHR hits
 system.cpu0.dcache.StoreCondReq_mshr_hits::total           65                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1457263                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1457263                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1457263                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1457263                       # number of overall MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1457353                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1457353                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1457353                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1457353                       # number of overall MSHR hits
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3248416                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::total      3248416                       # number of ReadReq MSHR misses
 system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1447894                       # number of WriteReq MSHR misses
@@ -767,10 +765,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       126978
 system.cpu0.dcache.LoadLockedReq_mshr_misses::total       126978                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       200535                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total       200535                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4696310                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4696310                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5356480                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5356480                       # number of overall MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5544112                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5544112                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      6204282                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      6204282                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31552                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31552                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31148                       # number of WriteReq MSHR uncacheable
@@ -791,16 +789,14 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5494928000
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5494928000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5416500                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5416500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  87107602500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  87107602500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6041391000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6041391000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5837295500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5837295500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11878686500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11878686500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6041391000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6041391000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035800                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035800                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018166                       # mshr miss rate for WriteReq accesses
@@ -813,10 +809,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061910
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061910                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097833                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097833                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027554                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027554                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031250                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031250                       # mshr miss rate for overall accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.032313                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032313                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.035958                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.035958                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427                       # average ReadReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292                       # average WriteReq mshr miss latency
@@ -831,17 +827,14 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements         10516028                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.897153                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          249911266                       # Total number of references to valid blocks.
@@ -900,8 +893,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks     10516028                       # number of writebacks
 system.cpu0.icache.writebacks::total         10516028                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst     10516550                       # number of ReadReq MSHR misses
@@ -940,7 +931,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued      8036343                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified      8037705                       # number of prefetch candidates identified
 system.cpu0.l2cache.prefetcher.pfBufferHit         1205                       # number of redundant prefetches already in prefetch queue
@@ -1158,8 +1148,6 @@ system.cpu0.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu0.l2cache.unused_prefetches           49728                       # number of HardPF blocks evicted w/o reference
 system.cpu0.l2cache.writebacks::writebacks      1630983                       # number of writebacks
 system.cpu0.l2cache.writebacks::total         1630983                       # number of writebacks
@@ -1255,11 +1243,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 124548471241
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5788797000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  12784952000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5603650500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5603650500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11392447500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  18388602500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5788797000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12784952000                       # number of overall MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.020389                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045776                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.026408                       # mshr miss rate for ReadReq accesses
@@ -1325,12 +1311,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799                       # average overall mshr uncacheable latency
 system.cpu0.toL2Bus.snoop_filter.tot_requests     33857668                       # Total number of requests made to the snoop filter.
 system.cpu0.toL2Bus.snoop_filter.hit_single_requests     17264460                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         3128                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1653,10 +1636,10 @@ system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1678906
 system.cpu1.dcache.LoadLockedReq_hits::total      1678906                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1638259                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total      1638259                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    139703423                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       139703423                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    139904287                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      139904287                       # number of overall hits
+system.cpu1.dcache.demand_hits::cpu1.data    139737373                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       139737373                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    139938237                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      139938237                       # number of overall hits
 system.cpu1.dcache.ReadReq_misses::cpu1.data      3193197                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total      3193197                       # number of ReadReq misses
 system.cpu1.dcache.WriteReq_misses::cpu1.data      2277873                       # number of WriteReq misses
@@ -1669,10 +1652,10 @@ system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       159945
 system.cpu1.dcache.LoadLockedReq_misses::total       159945                       # number of LoadLockedReq misses
 system.cpu1.dcache.StoreCondReq_misses::cpu1.data       199493                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total       199493                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5471070                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5471070                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6120062                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6120062                       # number of overall misses
+system.cpu1.dcache.demand_misses::cpu1.data      5881027                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5881027                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6530019                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6530019                       # number of overall misses
 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  52208022500                       # number of ReadReq miss cycles
 system.cpu1.dcache.ReadReq_miss_latency::total  52208022500                       # number of ReadReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  51224639500                       # number of WriteReq miss cycles
@@ -1685,10 +1668,10 @@ system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5532212500
 system.cpu1.dcache.StoreCondReq_miss_latency::total   5532212500                       # number of StoreCondReq miss cycles
 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5344000                       # number of StoreCondFailReq miss cycles
 system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5344000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 103432662000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 103432662000                       # number of overall miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 118332403000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 118332403000                       # number of overall miss cycles
 system.cpu1.dcache.ReadReq_accesses::cpu1.data     76856004                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     76856004                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data     68318489                       # number of WriteReq accesses(hits+misses)
@@ -1701,10 +1684,10 @@ system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1838851
 system.cpu1.dcache.LoadLockedReq_accesses::total      1838851                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1837752                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total      1837752                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    145174493                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    145174493                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    146024349                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    146024349                       # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data    145618400                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    145618400                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    146468256                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    146468256                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041548                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.041548                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.033342                       # miss rate for WriteReq accesses
@@ -1717,10 +1700,10 @@ system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.086981
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.086981                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108553                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108553                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.037686                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.037686                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041911                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.041911                       # miss rate for overall accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040387                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.040387                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044583                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044583                       # miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611                       # average ReadReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017                       # average WriteReq miss latency
@@ -1733,18 +1716,16 @@ system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks      5011891                       # number of writebacks
 system.cpu1.dcache.writebacks::total          5011891                       # number of writebacks
 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       367321                       # number of ReadReq MSHR hits
@@ -1757,10 +1738,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        40165
 system.cpu1.dcache.LoadLockedReq_mshr_hits::total        40165                       # number of LoadLockedReq MSHR hits
 system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           85                       # number of StoreCondReq MSHR hits
 system.cpu1.dcache.StoreCondReq_mshr_hits::total           85                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1310532                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1310532                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1310532                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1310532                       # number of overall MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1310590                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1310590                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1310590                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1310590                       # number of overall MSHR hits
 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2825876                       # number of ReadReq MSHR misses
 system.cpu1.dcache.ReadReq_mshr_misses::total      2825876                       # number of ReadReq MSHR misses
 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1334662                       # number of WriteReq MSHR misses
@@ -1773,10 +1754,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       119780
 system.cpu1.dcache.LoadLockedReq_mshr_misses::total       119780                       # number of LoadLockedReq MSHR misses
 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       199408                       # number of StoreCondReq MSHR misses
 system.cpu1.dcache.StoreCondReq_mshr_misses::total       199408                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4160538                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4160538                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4809167                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4809167                       # number of overall MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4570437                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4570437                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5219066                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5219066                       # number of overall MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7337                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7337                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7641                       # number of WriteReq MSHR uncacheable
@@ -1797,16 +1778,14 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5327664500
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5327664500                       # number of StoreCondReq MSHR miss cycles
 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      4914500                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      4914500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  71363385000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  71363385000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  87278174000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  87278174000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  85847670500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  85847670500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    919733500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    919733500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1094820000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1094820000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2014553500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2014553500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    919733500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    919733500                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036768                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036768                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019536                       # mshr miss rate for WriteReq accesses
@@ -1819,10 +1798,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065139
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065139                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108506                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108506                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028659                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028659                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032934                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032934                       # mshr miss rate for overall accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031386                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031386                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035633                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035633                       # mshr miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685                       # average ReadReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682                       # average WriteReq mshr miss latency
@@ -1837,17 +1816,14 @@ system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255                       # average overall mshr uncacheable latency
 system.cpu1.icache.tags.replacements          8449872                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          506.781387                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs          217357255                       # Total number of references to valid blocks.
@@ -1906,8 +1882,6 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks      8449872                       # number of writebacks
 system.cpu1.icache.writebacks::total          8449872                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8450384                       # number of ReadReq MSHR misses
@@ -1946,7 +1920,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624                       # average overall mshr uncacheable latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued      7137751                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified      7137894                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit          127                       # number of redundant prefetches already in prefetch queue
@@ -2162,8 +2135,6 @@ system.cpu1.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu1.l2cache.unused_prefetches           46108                       # number of HardPF blocks evicted w/o reference
 system.cpu1.l2cache.writebacks::writebacks      1173247                       # number of writebacks
 system.cpu1.l2cache.writebacks::total         1173247                       # number of writebacks
@@ -2256,11 +2227,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12274000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    860931500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    873205500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1037437000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1037437000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12274000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1898368500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1910642500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    860931500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    873205500                       # number of overall MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024289                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.052372                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.031430                       # mshr miss rate for ReadReq accesses
@@ -2324,12 +2293,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255                       # average overall mshr uncacheable latency
 system.cpu1.toL2Bus.snoop_filter.tot_requests     27757324                       # Total number of requests made to the snoop filter.
 system.cpu1.toL2Bus.snoop_filter.hit_single_requests     14199775                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1809                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -2491,11 +2457,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8877                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8917                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115861                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115901                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8877                       # number of overall misses
-system.iocache.overall_misses::total             8917                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115861                       # number of overall misses
+system.iocache.overall_misses::total           115901                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5199500                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1651659585                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1656859085                       # number of ReadReq miss cycles
@@ -2504,11 +2470,11 @@ system.iocache.WriteReq_miss_latency::total       369000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13563940301                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13563940301                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5568500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1651659585                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1657228085                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15215599886                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15221168386                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5568500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1651659585                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1657228085                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15215599886                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15221168386                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8877                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8914                       # number of ReadReq accesses(hits+misses)
@@ -2517,11 +2483,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8877                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8917                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115861                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115901                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8877                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8917                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115861                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115901                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2543,19 +2509,17 @@ system.iocache.WriteReq_avg_miss_latency::total       123000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 186060.559311                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 185850.407648                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 131326.329705                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 131329.051397                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 186060.559311                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 185850.407648                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 131326.329705                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 131329.051397                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         32764                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3385                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.679173                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106951                       # number of writebacks
 system.iocache.writebacks::total               106951                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -2566,11 +2530,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8877                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8917                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115861                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115901                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8877                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8917                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115861                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115901                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3349500                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1207809585                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1211159085                       # number of ReadReq MSHR miss cycles
@@ -2579,11 +2543,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       219000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8208491858                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8208491858                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3568500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1207809585                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1211378085                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9416301443                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9419869943                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3568500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1207809585                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1211378085                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9416301443                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9419869943                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2605,12 +2569,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        73000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 135850.407648                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 81275.139498                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 135850.407648                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 81275.139498                       # average overall mshr miss latency
 system.l2c.tags.replacements                  1387428                       # number of replacements
 system.l2c.tags.tagsinuse                63551.257518                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    6641936                       # Total number of references to valid blocks.
@@ -2939,8 +2902,6 @@ system.l2c.blocked::no_mshrs                       13                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs     74.692308                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks             1075915                       # number of writebacks
 system.l2c.writebacks::total                  1075915                       # number of writebacks
 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          164                       # number of ReadSharedReq MSHR hits
@@ -3071,14 +3032,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5220688053
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10320500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    728734017                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total  11857408570                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   5073884538                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    907395547                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5981280085                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   5897666000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10294572591                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5220688053                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10320500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1636129564                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  17838688655                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    728734017                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11857408570                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.275862                       # mshr miss rate for UpgradeReq accesses
@@ -3176,15 +3134,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               91289                       # Transaction distribution
 system.membus.trans_dist::ReadResp             902614                       # Transaction distribution
 system.membus.trans_dist::WriteReq              38789                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index d628e39f4..0e56e5404 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.660653                       # Nu
 sim_ticks                                51660652947000                       # Number of ticks simulated
 final_tick                               51660652947000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 204210                       # Simulator instruction rate (inst/s)
-host_op_rate                                   239956                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            11350998190                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 682908                       # Number of bytes of host memory used
-host_seconds                                  4551.20                       # Real time elapsed on the host
+host_inst_rate                                 286668                       # Simulator instruction rate (inst/s)
+host_op_rate                                   336848                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15934426663                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 682904                       # Number of bytes of host memory used
+host_seconds                                  3242.08                       # Real time elapsed on the host
 sim_insts                                   929398934                       # Number of instructions simulated
 sim_ops                                    1092086880                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -604,10 +604,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      3899601
 system.cpu.dcache.LoadLockedReq_hits::total      3899601                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      4208890                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      4208890                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     313786004                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        313786004                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    314301494                       # number of overall hits
-system.cpu.dcache.overall_hits::total       314301494                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     314122591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        314122591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    314638081                       # number of overall hits
+system.cpu.dcache.overall_hits::total       314638081                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      6423881                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       6423881                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      4177328                       # number of WriteReq misses
@@ -620,10 +620,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data       311002
 system.cpu.dcache.LoadLockedReq_misses::total       311002                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     10601209                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       10601209                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     12022090                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12022090                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data     11841309                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       11841309                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     13262190                       # number of overall misses
+system.cpu.dcache.overall_misses::total      13262190                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total 119203222500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500                       # number of WriteReq miss cycles
@@ -634,10 +634,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5200645500
 system.cpu.dcache.LoadLockedReq_miss_latency::total   5200645500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 325526040000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 325526040000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 325526040000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 325526040000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 378997815500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 378997815500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 378997815500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 378997815500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    171555549                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    171555549                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    152831664                       # number of WriteReq accesses(hits+misses)
@@ -650,10 +650,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4210603
 system.cpu.dcache.LoadLockedReq_accesses::total      4210603                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      4208892                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      4208892                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    324387213                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    324387213                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    326323584                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    326323584                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    325963900                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    325963900                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    327900271                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    327900271                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037445                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.037445                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027333                       # miss rate for WriteReq accesses
@@ -666,10 +666,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073862
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073862                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032681                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032681                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036841                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036841                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036327                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036327                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.040446                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.040446                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209                       # average WriteReq miss latency
@@ -680,18 +680,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30706.501494                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27077.325157                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32006.412087                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28577.317585                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      8312311                       # number of writebacks
 system.cpu.dcache.writebacks::total           8312311                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       778551                       # number of ReadReq MSHR hits
@@ -702,10 +700,10 @@ system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          166
 system.cpu.dcache.WriteLineReq_mshr_hits::total          166                       # number of WriteLineReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69564                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total        69564                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2620111                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2620111                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2620111                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2620111                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2620277                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2620277                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2620277                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2620277                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5645330                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      5645330                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2335768                       # number of WriteReq MSHR misses
@@ -718,10 +716,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       241438
 system.cpu.dcache.LoadLockedReq_mshr_misses::total       241438                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7981098                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7981098                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9394451                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9394451                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9221032                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9221032                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     10634385                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     10634385                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
@@ -740,16 +738,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3529658500
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3529658500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 206893714000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 233795004500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 259115478000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 286016768500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6197628500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6197628500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6191865500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6191865500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12389494000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12389494000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6197628500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6197628500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032907                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032907                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015283                       # mshr miss rate for WriteReq accesses
@@ -762,10 +758,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057340
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057340                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024604                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024604                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028789                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028789                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028289                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028289                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032432                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032432                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921                       # average WriteReq mshr miss latency
@@ -778,17 +774,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements          24339101                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.885333                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           418129059                       # Total number of references to valid blocks.
@@ -847,8 +840,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks     24339101                       # number of writebacks
 system.cpu.icache.writebacks::total          24339101                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24339623                       # number of ReadReq MSHR misses
@@ -887,7 +878,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1529682                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65330.827855                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           66339690                       # Total number of references to valid blocks.
@@ -1080,8 +1070,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1293856                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1293856                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
@@ -1157,11 +1145,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 133817968028
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5776326000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11712400000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5803513500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5803513500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11579839500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  17515913500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5776326000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11712400000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006391                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.017341                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008952                       # mshr miss rate for ReadReq accesses
@@ -1217,12 +1203,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests     71082854                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     35915919                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4125                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1379,11 +1362,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8839                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8879                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115503                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115543                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8839                       # number of overall misses
-system.iocache.overall_misses::total             8879                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115503                       # number of overall misses
+system.iocache.overall_misses::total           115543                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1644126101                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1649196101                       # number of ReadReq miss cycles
@@ -1392,11 +1375,11 @@ system.iocache.WriteReq_miss_latency::total       351000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13411893006                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13411893006                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1644126101                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1649547101                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15056019107                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15061440107                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1644126101                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1649547101                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15056019107                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15061440107                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8839                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8876                       # number of ReadReq accesses(hits+misses)
@@ -1405,11 +1388,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8839                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8879                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115503                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115543                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8839                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8879                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115503                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115543                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1431,19 +1414,17 @@ system.iocache.WriteReq_avg_miss_latency::total       117000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 186008.157144                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 185780.729925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130351.758024                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130353.548956                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 186008.157144                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 185780.729925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130351.758024                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130353.548956                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         32855                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3383                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.711794                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -1454,11 +1435,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8839                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8879                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115503                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115543                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8839                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8879                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115503                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115543                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1202176101                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1205396101                       # number of ReadReq MSHR miss cycles
@@ -1467,11 +1448,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       201000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8073547861                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8073547861                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1202176101                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1205597101                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9275723962                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9279144962                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1202176101                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1205597101                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9275723962                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9279144962                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1493,12 +1474,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        67000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 135780.729925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80309.018824                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 135780.729925                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80309.018824                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               86006                       # Transaction distribution
 system.membus.trans_dist::ReadResp             535040                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33706                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 43d314d14..005b587a4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.327140                       # Nu
 sim_ticks                                51327139864000                       # Number of ticks simulated
 final_tick                               51327139864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 122613                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144072                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7419967145                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 687012                       # Number of bytes of host memory used
-host_seconds                                  6917.44                       # Real time elapsed on the host
+host_inst_rate                                 109720                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128923                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6639754669                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 687008                       # Number of bytes of host memory used
+host_seconds                                  7730.28                       # Real time elapsed on the host
 sim_insts                                   848164321                       # Number of instructions simulated
 sim_ops                                     996610207                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -718,7 +718,7 @@ system.cpu.itb.accesses                     357169890                       # DT
 system.cpu.numCycles                       1631144067                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          646909214                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles          646909150                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                     1002667158                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                   225024609                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches          133765720                       # Number of branches that fetch has predicted taken
@@ -732,21 +732,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles          873                       #
 system.cpu.fetch.CacheLines                 356634442                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes               6247312                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                   47880                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples         1571640484                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::mean              0.747058                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::stdev             1.149321                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1013991405     64.52%     64.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1013991341     64.52%     64.52% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::1                214266060     13.63%     78.15% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                 70309362      4.47%     82.62% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::3                273073721     17.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1571640484                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.137955                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        0.614702                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                526349627                       # Number of cycles decode is idle
+system.cpu.decode.IdleCycles                526349563                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles             552086440                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                 434104674                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles              49724049                       # Number of cycles decode is unblocking
@@ -756,27 +756,27 @@ system.cpu.decode.BranchMispred               3814526                       # Nu
 system.cpu.decode.DecodedInsts             1085977369                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts              29430616                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                9375758                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                571292055                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                571291991                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                65924513                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles      371563835                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                 438965882                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles             114518505                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1065686030                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts             1065686033                       # Number of instructions processed by rename
 system.cpu.rename.SquashedInsts               6908876                       # Number of squashed instructions processed by rename
 system.cpu.rename.ROBFullEvents               5086020                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                 334343                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                 634469                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               63514971                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents               63514970                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.FullRegisterEvents            20439                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1013378726                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1640198292                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1259502846                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands          1013378727                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1640198295                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1259502849                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups           1473679                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             947186300                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 66192423                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 66192424                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts           26900223                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts       23242764                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101754926                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                 101754923                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads            173828486                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           150818351                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads           9879664                       # Number of conflicting loads.
@@ -788,11 +788,11 @@ system.cpu.iq.iqSquashedInstsIssued           3378731                       # Nu
 system.cpu.iq.iqSquashedInstsExamined        61252774                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined     34075299                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved         309098                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1571640548                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples    1571640484                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         0.665378                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::stdev        0.919633                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           924076981     58.80%     58.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           924076917     58.80%     58.80% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::1           334351644     21.27%     80.07% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::2           234725096     14.94%     95.01% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::3            72033056      4.58%     99.59% # Number of insts issued each cycle
@@ -804,7 +804,7 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1571640548                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1571640484                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                57663018     35.01%     35.01% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                 100158      0.06%     35.07% # attempts to use FU when none available
@@ -877,7 +877,7 @@ system.cpu.iq.FU_type_0::total             1045735608                       # Ty
 system.cpu.iq.rate                           0.641106                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                   164692672                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.157490                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3828710884                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads         3828710820                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes        1118319185                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses   1027391540                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads             2472282                       # Number of floating instruction queue reads
@@ -894,7 +894,7 @@ system.cpu.iew.lsq.thread0.squashedStores      6061186                       # N
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads      2527357                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1438792                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked       1438756                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                9375758                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                 6990377                       # Number of cycles IEW is blocking
@@ -928,11 +928,11 @@ system.cpu.iew.wb_fanout                     0.618086                       # av
 system.cpu.commit.commitSquashedInsts        51892888                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls        26891556                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           8548258                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples   1559580657                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::mean     0.639024                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     1.273898                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1047836838     67.19%     67.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1047836774     67.19%     67.19% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1    288037345     18.47%     85.66% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2    120098323      7.70%     93.36% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3     36644408      2.35%     95.71% # Number of insts commited each cycle
@@ -944,7 +944,7 @@ system.cpu.commit.committed_per_cycle::8     11706752      0.75%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1559580657                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            848164321                       # Number of instructions committed
 system.cpu.commit.committedOps              996610207                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -991,10 +991,10 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         996610207                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              11706752                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2588836198                       # The number of ROB reads
+system.cpu.rob.rob_reads                   2588836134                       # The number of ROB reads
 system.cpu.rob.rob_writes                  2108972650                       # The number of ROB writes
-system.cpu.timesIdled                         8176252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59503519                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                         8176249                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59503583                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.quiesceCycles                 101023135782                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu.committedInsts                   848164321                       # Number of Instructions Simulated
 system.cpu.committedOps                     996610207                       # Number of Ops (including micro ops) Simulated
@@ -1008,7 +1008,7 @@ system.cpu.fp_regfile_reads                   1462624                       # nu
 system.cpu.fp_regfile_writes                   780384                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                 225040074                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                225673032                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2558050181                       # number of misc regfile reads
+system.cpu.misc_regfile_reads              2558050117                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               26930699                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           9706309                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.972800                       # Cycle average of tags in use
@@ -1038,10 +1038,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      3295516
 system.cpu.dcache.LoadLockedReq_hits::total      3295516                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      3691142                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      3691142                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     275426405                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        275426405                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    275804158                       # number of overall hits
-system.cpu.dcache.overall_hits::total       275804158                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     275749871                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        275749871                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    276127624                       # number of overall hits
+system.cpu.dcache.overall_hits::total       276127624                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      9582006                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       9582006                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data     11252664                       # number of WriteReq misses
@@ -1054,10 +1054,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data       446459
 system.cpu.dcache.LoadLockedReq_misses::total       446459                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20834670                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20834670                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22005420                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22005420                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data     22068660                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       22068660                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     23239410                       # number of overall misses
+system.cpu.dcache.overall_misses::total      23239410                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total 168553352000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827                       # number of WriteReq miss cycles
@@ -1068,10 +1068,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6881905000
 system.cpu.dcache.LoadLockedReq_miss_latency::total   6881905000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       299500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       299500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 612836911827                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 612836911827                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 612836911827                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 612836911827                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 665180471800                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 665180471800                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 665180471800                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 665180471800                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    156764287                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    156764287                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    139496788                       # number of WriteReq accesses(hits+misses)
@@ -1084,10 +1084,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3741975
 system.cpu.dcache.LoadLockedReq_accesses::total      3741975                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691149                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      3691149                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    296261075                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    296261075                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    297809578                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    297809578                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    297818531                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    297818531                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    299367034                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    299367034                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061124                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.061124                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080666                       # miss rate for WriteReq accesses
@@ -1100,10 +1100,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119311
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119311                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070325                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070325                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073891                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073891                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074101                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074101                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.077628                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.077628                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523                       # average WriteReq miss latency
@@ -1114,18 +1114,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29414.284547                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27849.362195                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30141.407399                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28622.950058                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     32180640                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs           1601871                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.089408                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      7511281                       # number of writebacks
 system.cpu.dcache.writebacks::total           7511281                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4454269                       # number of ReadReq MSHR hits
@@ -1136,10 +1134,10 @@ system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7130
 system.cpu.dcache.WriteLineReq_mshr_hits::total         7130                       # number of WriteLineReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218050                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total       218050                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13703391                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13703391                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13703391                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13703391                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13710521                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13710521                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13710521                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13710521                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5127737                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      5127737                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2003542                       # number of WriteReq MSHR misses
@@ -1152,10 +1150,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       228409
 system.cpu.dcache.LoadLockedReq_mshr_misses::total       228409                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7131279                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7131279                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8295216                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8295216                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8358139                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8358139                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9522076                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9522076                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
@@ -1174,16 +1172,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3210622500
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3210622500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       292500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       292500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 162503876437                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 186189032937                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 213174289910                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 236859446410                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192022000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192022000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228178464                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228178464                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420200464                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420200464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6192022000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6192022000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032710                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032710                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014363                       # mshr miss rate for WriteReq accesses
@@ -1196,10 +1192,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061040
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061040                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024071                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024071                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027854                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027854                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028065                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028065                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031807                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031807                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577                       # average WriteReq mshr miss latency
@@ -1212,17 +1208,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements          15141033                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.928986                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           340718799                       # Total number of references to valid blocks.
@@ -1281,8 +1274,6 @@ system.cpu.icache.blocked::no_mshrs              1460                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    16.247260                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks     15141033                       # number of writebacks
 system.cpu.icache.writebacks::total          15141033                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst       752570                       # number of ReadReq MSHR hits
@@ -1327,7 +1318,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1146896                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65342.232394                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           46291207                       # Total number of references to valid blocks.
@@ -1522,8 +1512,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       961909                       # number of writebacks
 system.cpu.l2cache.writebacks::total           961909                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
@@ -1599,11 +1587,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total  95507463453
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770895500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189659000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836145500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836145500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607041000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025804500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5770895500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8189659000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006451                       # mshr miss rate for ReadReq accesses
@@ -1659,12 +1645,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests     50432401                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     25583822                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3563                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1821,11 +1804,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8814                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8854                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115478                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115518                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8814                       # number of overall misses
-system.iocache.overall_misses::total             8854                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115478                       # number of overall misses
+system.iocache.overall_misses::total           115518                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1678338975                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1683410975                       # number of ReadReq miss cycles
@@ -1834,11 +1817,11 @@ system.iocache.WriteReq_miss_latency::total       351000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13416126023                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13416126023                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5423000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1678338975                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1683761975                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15094464998                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15099887998                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5423000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1678338975                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1683761975                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15094464998                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15099887998                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8814                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8851                       # number of ReadReq accesses(hits+misses)
@@ -1847,11 +1830,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8814                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8854                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115478                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115518                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8814                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8854                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115478                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115518                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1873,19 +1856,17 @@ system.iocache.WriteReq_avg_miss_latency::total       117000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130712.906337                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130714.589917                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130712.906337                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130714.589917                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         34291                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3518                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.747300                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -1896,11 +1877,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8814                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8854                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115478                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115518                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8814                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8854                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115478                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115518                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3222000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1237638975                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1240860975                       # number of ReadReq MSHR miss cycles
@@ -1909,11 +1890,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       201000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8077839572                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8077839572                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3423000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1237638975                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1241061975                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9315478547                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9318901547                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3423000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1237638975                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1241061975                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9315478547                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9318901547                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1935,12 +1916,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        67000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80670.558242                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80670.558242                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
 system.membus.trans_dist::ReadResp             410008                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
@@ -1986,7 +1966,7 @@ system.membus.reqLayer0.occupancy           103925500                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5584000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5571500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer5.occupancy          7165123486                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index cec4ea48a..7762e55fa 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,168 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.389857                       # Number of seconds simulated
-sim_ticks                                47389857088000                       # Number of ticks simulated
-final_tick                               47389857088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.468752                       # Number of seconds simulated
+sim_ticks                                47468751978000                       # Number of ticks simulated
+final_tick                               47468751978000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 145229                       # Simulator instruction rate (inst/s)
-host_op_rate                                   170794                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7499087776                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 767912                       # Number of bytes of host memory used
-host_seconds                                  6319.42                       # Real time elapsed on the host
-sim_insts                                   917760909                       # Number of instructions simulated
-sim_ops                                    1079317478                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 133266                       # Simulator instruction rate (inst/s)
+host_op_rate                                   156717                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6699893970                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 769956                       # Number of bytes of host memory used
+host_seconds                                  7085.00                       # Real time elapsed on the host
+sim_insts                                   944191442                       # Number of instructions simulated
+sim_ops                                    1110340105                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       104896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        67648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3518240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         12875080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     14592448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       209856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       206272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3409696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         12665040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     18241216                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        447104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             66337496                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3518240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3409696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6927936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     83736832                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       171136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       120960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3861216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         14070216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     17654336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       218240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       209216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3621984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         13693456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     20748864                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        405504                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             74775128                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3861216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3621984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7483200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     90808384                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          83757416                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1639                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1057                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             70925                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            201186                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       228007                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3279                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         3223                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             53320                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            197904                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       285019                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6986                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1052545                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1308388                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          90828968                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2674                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1890                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             76284                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            219860                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       275849                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3410                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         3269                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             56637                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            213973                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       324201                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6336                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1184383                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1418881                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1310962                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2213                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1427                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               74240                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              271684                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       307923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          4428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          4353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               71950                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              267252                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       384918                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9435                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1399825                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          74240                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          71950                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             146190                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1766978                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1421455                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3605                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               81342                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              296410                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       371915                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4598                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          4407                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               76302                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              288473                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       437106                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8543                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1575250                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          81342                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          76302                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             157645                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1913014                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1767412                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1766978                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2213                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1427                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              74240                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             272119                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       307923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         4428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         4353                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              71950                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             267252                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       384918                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3167237                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1052545                       # Number of read requests accepted
-system.physmem.writeReqs                      1310962                       # Number of write requests accepted
-system.physmem.readBursts                     1052545                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1310962                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 67342528                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20352                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  83756608                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  66337496                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               83757416                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      318                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1913448                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1913014                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3605                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              81342                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             296844                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       371915                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4598                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         4407                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              76302                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             288473                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       437106                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3488697                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1184383                       # Number of read requests accepted
+system.physmem.writeReqs                      1421455                       # Number of write requests accepted
+system.physmem.readBursts                     1184383                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1421455                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 75776512                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     24000                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  90827456                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  74775128                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               90828968                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      375                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               66733                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               71928                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               60670                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               68962                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               64861                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               72347                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               66642                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               70254                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               57646                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               82139                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              57944                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              62634                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              58488                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              63067                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              63784                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              64128                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               82746                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               86394                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               79376                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               84859                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               81483                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               87954                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               81083                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               85604                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               78166                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               81607                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              78637                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              81487                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              76226                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              79682                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              80516                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              82877                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               72103                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               78803                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               72464                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               70552                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               69846                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               79143                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               69266                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               70722                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               68903                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               99020                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              71711                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              73604                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              71852                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              74765                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              70123                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              71131                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               89065                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               93300                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               85781                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               86502                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               86907                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               92159                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               86239                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               88123                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               85047                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               93098                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              87729                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              90867                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              86341                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              90891                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              88902                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              88228                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          67                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47389855480500                       # Total gap between requests
+system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47468750370500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1031187                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1163025                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1308388                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    475081                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    269839                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     74446                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     52901                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     38377                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     34235                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     31560                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     30053                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     26736                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      7334                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     3987                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2417                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1591                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1204                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      701                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      610                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      497                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      147                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1418881                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    512770                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    308725                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     87137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     63943                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     45149                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     40149                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     37001                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     34987                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     30693                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      8585                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     4718                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2994                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     2073                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1609                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1005                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      881                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      765                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      567                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      148                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -188,102 +188,101 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    30313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    42202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    46715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    53462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    56984                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    62681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    68834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    74158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    77826                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    82266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    87664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    86481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    90056                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   101873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    89446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    81226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    76109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                    12688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     9562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     8108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     6575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     5525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     4656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     3860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     3225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     2811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1382                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      369                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      151                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1063862                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      142.028406                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      96.908483                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     188.947681                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         721844     67.85%     67.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       204911     19.26%     87.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        49859      4.69%     91.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22222      2.09%     93.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18303      1.72%     95.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10788      1.01%     96.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         6944      0.65%     97.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4476      0.42%     97.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24515      2.30%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1063862                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61379                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.142980                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       72.283129                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           61375     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    26847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    31854                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    44695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    49676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    56919                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61698                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    67754                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    74407                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    81101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    85167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    89920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    95633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    94983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    99480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   111361                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    98562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    89368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    83432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                    13050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     9803                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     8425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     6741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     5561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     4626                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     3942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     3261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     2837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     2058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1909                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      919                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      105                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1159540                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      143.680535                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      97.586865                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     190.741453                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         783407     67.56%     67.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       222260     19.17%     86.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        55727      4.81%     91.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        24890      2.15%     93.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        21192      1.83%     95.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11987      1.03%     96.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8178      0.71%     97.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4967      0.43%     97.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        26932      2.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1159540                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         67946                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        17.425117                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       68.584486                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           67943    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61379                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61379                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.321576                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.114024                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       78.581580                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-127           61139     99.61%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-255           150      0.24%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-383            15      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-511            13      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-639            10      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-767             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::768-895             6      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           67946                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         67946                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.886866                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.982744                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       74.693624                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-127           67692     99.63%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-255           167      0.25%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-383            12      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-511            13      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-639            10      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-767             5      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::768-895             6      0.01%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::896-1023            2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1024-1151            3      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1024-1151            3      0.00%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::1152-1279            3      0.00%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::1280-1407            1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1408-1535            3      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1536-1663            1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1408-1535            3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1536-1663            1      0.00%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::1664-1791            2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1792-1919            3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1920-2047            1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1792-1919            3      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1920-2047            1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::2048-2175            1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::2176-2303            2      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::2432-2559            1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2560-2687            2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2560-2687            2      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::2688-2815            1      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::2944-3071            1      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::3072-3199            1      0.00%     99.98% # Writes before turning the bus around for reads
@@ -295,56 +294,56 @@ system.physmem.wrPerTurnAround::4224-4351            3      0.00%    100.00% # W
 system.physmem.wrPerTurnAround::4736-4863            1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::5760-5887            1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::6528-6655            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61379                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    45835808351                       # Total ticks spent queuing
-system.physmem.totMemAccLat               65565064601                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5261135000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       43560.76                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           67946                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    53444908202                       # Total ticks spent queuing
+system.physmem.totMemAccLat               75645058202                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5920040000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       45138.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  62310.76                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.42                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.77                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.40                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.77                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  63888.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.60                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.91                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.91                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.24                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     793650                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    503408                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  38.47                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20050651.63                       # Average gap between requests
-system.physmem.pageHitRate                      54.94                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4147801560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2263185375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4230649800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4338353520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3095274664560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1171144383615                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27406590797250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31687989835680                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.666167                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45593219352262                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582451260000                       # Time in different power states
+system.physmem.avgRdQLen                         2.06                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.70                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     894156                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    549489                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.52                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  38.72                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18216309.06                       # Average gap between requests
+system.physmem.pageHitRate                      55.46                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4374828360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2387059125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4546612200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4588332480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3100427903040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1181604436515                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27444754155000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31742683326720                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.706973                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45656629611476                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1585085840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    214185512238                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    227033353524                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3894995160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2125245375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3976658400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4142003040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3095274664560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1168941164895                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27408523445250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31686878176680                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.642709                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45596430811261                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582451260000                       # Time in different power states
+system.physmem_1.actEnergy                 4391294040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2396043375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4688572200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4607947440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3100427903040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1183305976290                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27443261584500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31743079320885                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.715315                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45654123959514                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1585085840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    210971448239                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    229539287986                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -378,19 +377,19 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              134064980                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         88919550                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6498041                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            94483455                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               58137091                       # Number of BTB hits
+system.cpu0.branchPred.lookups              132444225                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         87787955                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6400754                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            93524644                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               57612051                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            61.531504                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17960348                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            169436                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        4224209                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2670261                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         1553948                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       396228                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            61.600931                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17778768                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            168825                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4144770                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2586947                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         1557823                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       392899                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -421,86 +420,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   535513                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               535513                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11169                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        82857                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       246420                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       289093                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2351.355792                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 14312.568858                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       286889     99.24%     99.24% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1266      0.44%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          685      0.24%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          138      0.05%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           30      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           61      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           19      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       289093                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       272039                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 19613.296255                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17220.717357                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14703.962270                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       270425     99.41%     99.41% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          632      0.23%     99.64% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          733      0.27%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           61      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          123      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           32      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::720896-786431            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       272039                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 510275836160                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.563308                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.548439                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 509171724160     99.78%     99.78% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    565791000      0.11%     99.89% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    239447000      0.05%     99.94% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    119430500      0.02%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9     85504500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     55232500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     15487000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     22822000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       392500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19         5000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 510275836160                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        82857     88.12%     88.12% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11169     11.88%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        94026                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       535513                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   539802                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               539802                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11294                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        84152                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       248635                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       291167                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2569.659336                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 15605.583986                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       288567     99.11%     99.11% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1409      0.48%     99.59% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          865      0.30%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          174      0.06%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           52      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           75      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           18      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       291167                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       273980                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 20501.036572                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17496.757374                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 20192.590719                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       271123     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          705      0.26%     99.21% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1540      0.56%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          149      0.05%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          269      0.10%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           86      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           62      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            6      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       273980                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 529053057016                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.549473                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.550536                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 527876290016     99.78%     99.78% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    603631000      0.11%     99.89% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    259797000      0.05%     99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    123836500      0.02%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     92525500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     56948500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     16655000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     23145000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       228500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 529053057016                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        84152     88.17%     88.17% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        11294     11.83%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        95446                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       539802                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       535513                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        94026                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       539802                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        95446                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        94026                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       629539                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        95446                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       635248                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    97385635                       # DTB read hits
-system.cpu0.dtb.read_misses                    369085                       # DTB read misses
-system.cpu0.dtb.write_hits                   80705124                       # DTB write hits
-system.cpu0.dtb.write_misses                   166428                       # DTB write misses
-system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    96092667                       # DTB read hits
+system.cpu0.dtb.read_misses                    371231                       # DTB read misses
+system.cpu0.dtb.write_hits                   80108557                       # DTB write hits
+system.cpu0.dtb.write_misses                   168571                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   34685                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      254                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  6533                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   35125                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      346                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  6813                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    38231                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                97754720                       # DTB read accesses
-system.cpu0.dtb.write_accesses               80871552                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    38936                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                96463898                       # DTB read accesses
+system.cpu0.dtb.write_accesses               80277128                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        178090759                       # DTB hits
-system.cpu0.dtb.misses                         535513                       # DTB misses
-system.cpu0.dtb.accesses                    178626272                       # DTB accesses
+system.cpu0.dtb.hits                        176201224                       # DTB hits
+system.cpu0.dtb.misses                         539802                       # DTB misses
+system.cpu0.dtb.accesses                    176741026                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -530,1181 +528,1164 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    79425                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                79425                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          951                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        57153                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore         9771                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        69654                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1061.827031                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  8997.758844                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        69210     99.36%     99.36% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          270      0.39%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303            5      0.01%     99.76% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071           37      0.05%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839           88      0.13%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           29      0.04%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        69654                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        67875                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 24239.233886                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 22083.564087                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 17866.594665                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        67243     99.07%     99.07% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071           67      0.10%     99.17% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          462      0.68%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           35      0.05%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           34      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           16      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           11      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        67875                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 394215499668                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.849337                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.357871                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    59413822884     15.07%     15.07% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   334782784784     84.92%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       17900000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         873000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         119000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 394215499668                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        57153     98.36%     98.36% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          951      1.64%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        58104                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    79903                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                79903                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          950                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        57315                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         9653                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        70250                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1248.284698                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 10855.060811                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-65535        69985     99.62%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-131071           65      0.09%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-196607          177      0.25%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-262143           11      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-393215            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        70250                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        67918                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26250.242940                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 22828.736245                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 25780.781063                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        66522     97.94%     97.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          103      0.15%     98.10% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607         1066      1.57%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           71      0.10%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           86      0.13%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           28      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           25      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::917504-983039            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        67918                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 408740768228                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.873449                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.332683                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    51752271292     12.66%     12.66% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   356965086936     87.33%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       21879500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        1303500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4          81500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          52500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6          29500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::7           1000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::8          62500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 408740768228                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        57315     98.37%     98.37% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          950      1.63%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        58265                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        79425                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        79425                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        79903                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        79903                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        58104                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        58104                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       137529                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   209912640                       # ITB inst hits
-system.cpu0.itb.inst_misses                     79425                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        58265                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        58265                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       138168                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   207793696                       # ITB inst hits
+system.cpu0.itb.inst_misses                     79903                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24340                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24840                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   193348                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   191050                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               209992065                       # ITB inst accesses
-system.cpu0.itb.hits                        209912640                       # DTB hits
-system.cpu0.itb.misses                          79425                       # DTB misses
-system.cpu0.itb.accesses                    209992065                       # DTB accesses
-system.cpu0.numCycles                       756853118                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               207873599                       # ITB inst accesses
+system.cpu0.itb.hits                        207793696                       # DTB hits
+system.cpu0.itb.misses                          79903                       # DTB misses
+system.cpu0.itb.accesses                    207873599                       # DTB accesses
+system.cpu0.numCycles                       761315266                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          86258252                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     591637469                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  134064980                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          78767700                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    626674135                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13960220                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   1708629                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              309159                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      5578419                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       726023                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       793198                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                209720229                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1626111                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  25986                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         729027925                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.950211                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.213293                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          84074114                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     585063894                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  132444225                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          77977766                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    631770796                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13765762                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1785587                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              318737                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      5559321                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       752999                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       796339                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                207603742                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1586738                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  26136                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         731940774                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.936268                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.209570                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               397179270     54.48%     54.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               129433697     17.75%     72.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                43948284      6.03%     78.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               158466674     21.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               403543312     55.13%     55.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               128205713     17.52%     72.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                43488128      5.94%     78.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               156703621     21.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           729027925                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.177135                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.781707                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               101905293                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            364135087                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                222287988                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             35712800                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               4986757                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19110947                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2030964                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             613952929                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             22693715                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               4986757                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               135896080                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               55064795                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     234892830                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                223531264                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             74656199                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             597354053                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              5967968                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             10658303                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                242676                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                277310                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              41417072                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           10715                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          569274330                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            919727485                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       705445437                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           845170                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            513762865                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                55511456                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          14761622                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      12913765                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 71848393                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            97600013                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           83873039                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          8761707                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         7520310                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 575959343                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           14902678                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                580046321                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2619697                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       52147933                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     33732364                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        256005                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    729027925                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.795643                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.062696                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           731940774                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.173968                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.768491                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               100319911                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            372509653                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                217857253                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             36338079                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               4915878                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            18873695                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2004301                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             606758178                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             22350639                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               4915878                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               134368949                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               57393762                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     239367965                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                219640614                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             76253606                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             590337881                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              5891778                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10879657                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                272900                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                275104                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              42478331                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           10735                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          562575259                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            912365987                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       697390419                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           694396                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            507972674                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                54602579                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15164295                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13334098                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 72899123                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            96066209                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           83257958                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          8637114                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         7533431                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 568637659                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15304177                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                573527019                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2573483                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       51469570                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     33194366                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        252301                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    731940774                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.783570                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.057506                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          413752637     56.75%     56.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          130387752     17.89%     74.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          112730807     15.46%     90.10% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           64434367      8.84%     98.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            7717956      1.06%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               4406      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          419086912     57.26%     57.26% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          131041268     17.90%     75.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          110621862     15.11%     90.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           63525040      8.68%     98.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            7661553      1.05%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               4139      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      729027925                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      731940774                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               60438369     45.47%     45.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 47042      0.04%     45.50% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  17968      0.01%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              10      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              34488153     25.95%     71.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             37935532     28.54%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               59257381     45.13%     45.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 46667      0.04%     45.16% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  17941      0.01%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              17      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              34285997     26.11%     71.29% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             37701656     28.71%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               10      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            396224561     68.31%     68.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1355740      0.23%     68.54% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                69556      0.01%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  5      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt             26      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         78264      0.01%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           100394563     17.31%     85.88% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           81923573     14.12%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               17      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            391712029     68.30%     68.30% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1330798      0.23%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                69152      0.01%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  6      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         42956      0.01%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            99049842     17.27%     85.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           81322170     14.18%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             580046321                       # Type of FU issued
-system.cpu0.iq.rate                          0.766392                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  132927074                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.229166                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2023285471                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        642599747                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    563357563                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1381865                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            550084                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       513487                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             712117129                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 856256                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2617003                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             573527019                       # Type of FU issued
+system.cpu0.iq.rate                          0.753337                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  131309659                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.228951                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2011763518                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        635110276                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    556950573                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1114436                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            438215                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       411063                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             704141671                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 694990                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2575949                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     11923389                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        15941                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       140828                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      5327299                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     11750995                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        17228                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       138196                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      5318019                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2590097                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4396592                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2553185                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4584143                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               4986757                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                6158595                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              2729815                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          590987234                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               4915878                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                6708218                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              2698388                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          584066483                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             97600013                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            83873039                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          12685897                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 60837                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              2608142                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        140828                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       1838258                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2998999                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             4837257                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            572331002                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             97377740                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7191247                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             96066209                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            83257958                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13102761                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 64235                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              2566402                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        138196                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       1807441                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2958148                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4765589                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            565930325                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             96085763                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7069222                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       125213                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   178083928                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               107921948                       # Number of branches executed
-system.cpu0.iew.exec_stores                  80706188                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.756198                       # Inst execution rate
-system.cpu0.iew.wb_sent                     564585754                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    563871050                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                273627354                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                449179775                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.745020                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609171                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       45416795                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       14646672                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4504688                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    720395645                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.747803                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.555225                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       124647                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   176196325                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               106580080                       # Number of branches executed
+system.cpu0.iew.exec_stores                  80110562                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.743359                       # Inst execution rate
+system.cpu0.iew.wb_sent                     558072531                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    557361636                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                269759058                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                442874225                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.732104                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609110                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       44855365                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15051876                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4433751                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    723417587                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.736051                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.544488                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    485771326     67.43%     67.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    120512789     16.73%     84.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     52399936      7.27%     91.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     17702861      2.46%     93.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     12776683      1.77%     95.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      8497825      1.18%     96.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      5820958      0.81%     97.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3534904      0.49%     98.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     13378363      1.86%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    490442876     67.80%     67.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    120876307     16.71%     84.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     51465837      7.11%     91.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     17138323      2.37%     93.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     12635808      1.75%     95.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      8409902      1.16%     96.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5731195      0.79%     97.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3469312      0.48%     98.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     13248027      1.83%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    720395645                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           458462253                       # Number of instructions committed
-system.cpu0.commit.committedOps             538714081                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    723417587                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           452974919                       # Number of instructions committed
+system.cpu0.commit.committedOps             532472262                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     164222361                       # Number of memory references committed
-system.cpu0.commit.loads                     85676622                       # Number of loads committed
-system.cpu0.commit.membars                    3641024                       # Number of memory barriers committed
-system.cpu0.commit.branches                 102649552                       # Number of branches committed
-system.cpu0.commit.fp_insts                    504968                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                494164906                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13432281                       # Number of function calls committed.
+system.cpu0.commit.refs                     162255152                       # Number of memory references committed
+system.cpu0.commit.loads                     84315213                       # Number of loads committed
+system.cpu0.commit.membars                    3606698                       # Number of memory barriers committed
+system.cpu0.commit.branches                 101352780                       # Number of branches committed
+system.cpu0.commit.fp_insts                    403239                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                488332622                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13274605                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       373237846     69.28%     69.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1127454      0.21%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           54738      0.01%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        71640      0.01%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       85676622     15.90%     85.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      78545739     14.58%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       369012489     69.30%     69.30% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1112277      0.21%     69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           54460      0.01%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        37842      0.01%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.53% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       84315213     15.83%     85.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      77939939     14.64%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        538714081                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             13378363                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1287287379                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1176858570                       # The number of ROB writes
-system.cpu0.timesIdled                         934729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       27825193                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 94022861092                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  458462253                       # Number of Instructions Simulated
-system.cpu0.committedOps                    538714081                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.650852                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.650852                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.605748                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.605748                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               675960762                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              401183302                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   830771                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  428332                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                124727892                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               125481667                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1276105833                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              14867290                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          5765600                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          490.322435                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          152640999                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5766111                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            26.472088                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        532472262                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             13248027                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1283601950                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1163144719                       # The number of ROB writes
+system.cpu0.timesIdled                         940575                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       29374492                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 94176188727                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  452974919                       # Number of Instructions Simulated
+system.cpu0.committedOps                    532472262                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.680701                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.680701                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.594990                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.594990                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               668586496                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              395947855                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   683579                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  295852                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                123538962                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               124272565                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1278649841                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15273032                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          5802522                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          485.093904                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          150368529                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5803033                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            25.912058                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       2962390000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   490.322435                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.957661                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.957661                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.093904                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947449                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.947449                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        340447274                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       340447274                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     79408561                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       79408561                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     68334031                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      68334031                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200433                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       200433                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       174121                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       174121                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1831958                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1831958                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1849907                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1849907                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    147742592                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       147742592                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    147943025                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      147943025                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6387707                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      6387707                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7192656                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7192656                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       686822                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       686822                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       795953                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       795953                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       241297                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       241297                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189319                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       189319                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13580363                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      13580363                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     14267185                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     14267185                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102145338500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 102145338500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 163649518808                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 163649518808                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  49996037023                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  49996037023                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3671046500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3671046500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5304166500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   5304166500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5694500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5694500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 265794857308                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 265794857308                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 265794857308                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 265794857308                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     85796268                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     85796268                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     75526687                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     75526687                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       887255                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       887255                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       970074                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       970074                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2073255                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2073255                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2039226                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2039226                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    161322955                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    161322955                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    162210210                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    162210210                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074452                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.074452                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.095233                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.095233                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.774098                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.774098                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.820508                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.820508                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.116386                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.116386                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092839                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092839                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084181                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.084181                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087955                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.087955                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15990.924208                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15990.924208                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 22752.307188                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 22752.307188                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62812.800533                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62812.800533                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.809123                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.809123                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28017.084920                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28017.084920                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        336490622                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       336490622                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     77978502                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       77978502                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67507915                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      67507915                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       199394                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       199394                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       171803                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       171803                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1821693                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1821693                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1835435                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1835435                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    145658220                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       145658220                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    145857614                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      145857614                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6410027                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      6410027                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7429665                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7429665                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       719434                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       719434                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       793389                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       793389                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       238145                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       238145                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       190782                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       190782                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     14633081                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      14633081                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     15352515                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     15352515                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 109062490500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 109062490500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171373805000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 171373805000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  50210173040                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  50210173040                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3622154000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3622154000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5311494500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5311494500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5825000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5825000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 330646468540                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 330646468540                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 330646468540                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 330646468540                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     84388529                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     84388529                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     74937580                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     74937580                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       918828                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       918828                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       965192                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       965192                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2059838                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2059838                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2026217                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2026217                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    160291301                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    160291301                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    161210129                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    161210129                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075959                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.075959                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.099145                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.099145                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.782991                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.782991                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.822001                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.822001                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.115613                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.115613                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.094157                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.094157                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.091291                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.091291                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.095233                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.095233                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17014.357428                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17014.357428                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23066.155069                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 23066.155069                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 63285.693449                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 63285.693449                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15209.867938                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15209.867938                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27840.647965                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27840.647965                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19571.999460                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19571.999460                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18629.803799                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18629.803799                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     15450587                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     24201430                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           734789                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         699058                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.027243                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    34.620060                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      5765616                       # number of writebacks
-system.cpu0.dcache.writebacks::total          5765616                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3289806                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3289806                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5763001                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      5763001                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4255                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         4255                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       124637                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       124637                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9052807                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9052807                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9052807                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9052807                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3097901                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3097901                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1429655                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1429655                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       679876                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       679876                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       791698                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       791698                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       116660                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       116660                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189313                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       189313                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4527556                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4527556                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5207432                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5207432                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        19295                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19295                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        20724                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        20724                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40019                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40019                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47331591500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  47331591500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  38044472455                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  38044472455                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16657786000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16657786000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  48937488023                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  48937488023                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1685431500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1685431500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5114922500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5114922500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5625500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5625500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  85376063955                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  85376063955                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102033849955                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 102033849955                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3789852000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3789852000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3941977500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3941977500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7731829500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7731829500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036108                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036108                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018929                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018929                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.766269                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766269                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.816121                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.816121                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056269                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056269                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092836                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092836                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028065                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028065                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032103                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032103                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15278.600414                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15278.600414                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26610.946316                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26610.946316                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24501.211986                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24501.211986                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61813.327838                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61813.327838                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14447.381279                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14447.381279                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27018.337357                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27018.337357                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22595.820288                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 22595.820288                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.957856                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21536.957856                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     15517119                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     25638833                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           732854                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         730129                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.173548                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    35.115484                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks      5802538                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5802538                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3327729                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3327729                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5970882                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      5970882                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4398                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4398                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       123286                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       123286                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9303009                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9303009                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9303009                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9303009                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3082298                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3082298                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1458783                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1458783                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       712505                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       712505                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       788991                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       788991                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       114859                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       114859                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       190777                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       190777                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5330072                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5330072                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      6042577                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      6042577                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        19706                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19706                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        21266                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        21266                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40972                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40972                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48302897000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  48302897000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39166129612                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  39166129612                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  19342072500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  19342072500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  49145395540                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  49145395540                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1672767500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1672767500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5120787500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5120787500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5755000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5755000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 136614422152                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 136614422152                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 155956494652                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 155956494652                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3863694500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3863694500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3863694500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3863694500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036525                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036525                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019467                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019467                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.775450                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.775450                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.817445                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.817445                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055761                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.055761                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.094154                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.094154                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033252                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.033252                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037483                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.037483                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15671.066522                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15671.066522                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26848.496049                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26848.496049                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27146.577919                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27146.577919                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 62288.917795                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 62288.917795                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14563.660662                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14563.660662                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26841.744550                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26841.744550                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18856.986850                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18856.986850                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19593.890032                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19593.890032                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196416.273646                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196416.273646                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 190213.158657                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190213.158657                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193203.965616                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193203.965616                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          5849403                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.943926                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          203506939                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5849915                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            34.788016                       # Average number of references to valid blocks.
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25630.877435                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25630.877435                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25809.599886                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25809.599886                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196066.908556                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196066.908556                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94300.851801                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94300.851801                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.replacements          5681079                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.944679                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          201561746                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5681591                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.476286                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      18014203000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.943926                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999890                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999890                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.944679                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999892                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999892                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          457                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          483                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        425234482                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       425234482                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    203506939                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      203506939                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    203506939                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       203506939                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    203506939                       # number of overall hits
-system.cpu0.icache.overall_hits::total      203506939                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6185325                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6185325                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6185325                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6185325                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6185325                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6185325                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  68820233655                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  68820233655                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  68820233655                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  68820233655                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  68820233655                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  68820233655                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    209692264                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    209692264                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    209692264                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    209692264                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    209692264                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    209692264                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029497                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.029497                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029497                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.029497                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029497                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.029497                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11126.373094                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11126.373094                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11126.373094                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11126.373094                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11126.373094                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11126.373094                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     10317197                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets         1776                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           708038                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             15                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.571530                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets   118.400000                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      5849403                       # number of writebacks
-system.cpu0.icache.writebacks::total          5849403                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       335371                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       335371                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       335371                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       335371                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       335371                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       335371                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5849954                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      5849954                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      5849954                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      5849954                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      5849954                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      5849954                       # number of overall MSHR misses
+system.cpu0.icache.tags.tag_accesses        420833426                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       420833426                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    201561746                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      201561746                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    201561746                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       201561746                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    201561746                       # number of overall hits
+system.cpu0.icache.overall_hits::total      201561746                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6014149                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6014149                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6014149                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6014149                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6014149                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6014149                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  68585469625                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  68585469625                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  68585469625                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  68585469625                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  68585469625                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  68585469625                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    207575895                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    207575895                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    207575895                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    207575895                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    207575895                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    207575895                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028973                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028973                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028973                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028973                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028973                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028973                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11404.019027                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 11404.019027                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11404.019027                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 11404.019027                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11404.019027                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 11404.019027                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     10444384                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         1542                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           695799                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             13                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.010634                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   118.615385                       # average number of cycles each access was blocked
+system.cpu0.icache.writebacks::writebacks      5681079                       # number of writebacks
+system.cpu0.icache.writebacks::total          5681079                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       332513                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       332513                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       332513                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       332513                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       332513                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       332513                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5681636                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      5681636                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      5681636                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      5681636                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      5681636                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      5681636                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  62003791719                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  62003791719                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  62003791719                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  62003791719                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  62003791719                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  62003791719                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  61685306454                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  61685306454                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  61685306454                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  61685306454                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  61685306454                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  61685306454                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939780498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939780498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027898                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.027898                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.027898                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.022098                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.022098                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.022098                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027371                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027371                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027371                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027371                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027371                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027371                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10856.962054                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10856.962054                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10856.962054                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10856.962054                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10856.962054                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10856.962054                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7728604                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7739029                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         9391                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7915167                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7926437                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit        10130                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1009379                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2564693                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16115.455050                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          16793989                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2580455                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.508150                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage      1009963                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2664029                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16072.729216                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          16415073                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2680041                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.124934                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      3423391000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15189.817195                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    51.994619                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    35.520086                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.176107                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   837.947042                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.927113                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003173                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.002168                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000011                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.051144                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.983609                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1242                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14441                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           78                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          110                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          653                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          401                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           26                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1001                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5348                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4520                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3402                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.075806                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004822                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.881409                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       398023302                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      398023302                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       546484                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       178619                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        725103                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      3848803                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      3848803                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      7764047                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      7764047                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          499                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          499                       # number of UpgradeReq hits
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14987.796585                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    47.087094                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    49.541309                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   988.304228                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.914783                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002874                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003024                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.060321                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.981002                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1464                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14480                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           10                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           48                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          590                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          290                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          526                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           35                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           10                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1208                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5747                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2985                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4461                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.089355                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.883789                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       394147733                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      394147733                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       551770                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       179424                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        731194                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3854487                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3854487                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      7627202                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      7627202                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          654                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          654                       # number of UpgradeReq hits
 system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            5                       # number of SCUpgradeReq hits
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021381                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.046145                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.027576                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
 system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998080                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998080                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.997532                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.997532                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999974                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999974                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.270745                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.270745                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.093915                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.093915                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253420                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253420                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.753793                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.753793                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.019877                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.039832                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.093915                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.257456                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.160622                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.019877                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.039832                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.093915                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.257456                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.160622                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42988.076570                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13154.672931                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13154.672931                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9772.524616                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9772.524616                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data      1380500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1380500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63955.199401                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63955.199401                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38443.002051                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38443.002051                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41025.969021                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41025.969021                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   881.607694                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   881.607694                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38443.002051                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46642.387601                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 44202.245388                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38443.002051                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46642.387601                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 44202.245388                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          731                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.271539                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.271539                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.098632                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.098632                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.262326                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.262326                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.760463                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.760463                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021381                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.046145                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.098632                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.264499                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.167441                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021381                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.046145                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.098632                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.264499                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.167441                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53051.347988                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 51761.923963                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 52511.574632                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12708.788008                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12708.788008                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9644.535714                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9644.535714                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       941500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       941500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65142.209116                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65142.209116                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39529.884651                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39529.884651                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 43157.647565                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 43157.647565                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   727.616057                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   727.616057                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53051.347988                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 51761.923963                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39529.884651                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48482.814733                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 45930.650616                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53051.347988                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 51761.923963                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39529.884651                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48482.814733                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 45930.650616                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          710                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    91.375000                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   118.333333                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.unused_prefetches           42139                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks      1615717                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1615717                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            6                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           11                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.unused_prefetches           45316                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1671374                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1671374                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           14                       # number of ReadReq MSHR hits
 system.cpu0.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        41013                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        41013                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            5                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5478                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5478                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           13                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total           13                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           11                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        46491                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        46513                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            6                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           11                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            5                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        46491                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        46513                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11077                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7399                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        18476                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            2                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::total            2                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       765922                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       765922                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       259441                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       259441                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       189304                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       189304                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278860                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       278860                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       549392                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       549392                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       980542                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       980542                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       595013                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       595013                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11077                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7399                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       549392                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1259402                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1827270                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        11077                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7399                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       549392                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1259402                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       765922                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2593192                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        47908                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total        47908                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            7                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5947                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5947                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           12                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total           12                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           14                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            7                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        53855                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        53879                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           14                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            7                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        53855                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        53879                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12052                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8666                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        20718                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            3                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::total            3                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       803197                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       803197                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       264383                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       264383                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       190766                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       190766                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       279571                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       279571                       # number of ReadExReq MSHR misses
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+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       560381                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1018547                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1018547                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       598274                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       598274                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12052                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8666                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       560381                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1298118                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1879217                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12052                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8666                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       560381                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1298118                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total      2682414                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        19295                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40588                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        20724                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        20724                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        19706                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40999                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        21266                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        21266                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40019                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        61312                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    683811500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  48317121571                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  48317121571                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7648488996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7648488996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3692133999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3692133999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      5108000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5108000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16036130498                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16036130498                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17824036498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17824036498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34158749978                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34158749978                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  42060830499                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  42060830499                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17824036498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  50194880476                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  68702728474                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17824036498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  50194880476                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  48317121571                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 117019850045                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40972                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        62265                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    567159000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    396729500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    963888500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  57196003159                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  57196003159                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7687713495                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7687713495                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3687086997                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3687086997                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      5229000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5229000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16511973000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16511973000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  18789663000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  18789663000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  37621826984                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  37621826984                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  42300516999                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  42300516999                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    567159000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    396729500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  18789663000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  54133799984                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  73887351484                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    567159000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    396729500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  18789663000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  54133799984                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total 131083354643                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3635082000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6415164000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3780809967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3780809967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3705524000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6485606000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7415891967                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10195973967                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.024847                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3705524000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6485606000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021375                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.046070                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027553                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998080                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998080                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997532                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997532                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999974                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999974                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.236031                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.236031                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093914                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.252013                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.252013                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.753776                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.753776                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248290                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.156635                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248290                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.231814                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.231814                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.098631                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.098631                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.260803                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.260803                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.760448                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.760448                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021375                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.046070                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.098631                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.253963                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.162774                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021375                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.046070                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.098631                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.253963                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.222290                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37010.797792                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63083.605865                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29480.648764                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29480.648764                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19503.729446                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19503.729446                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data      1277000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1277000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57506.026314                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57506.026314                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32443.203574                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34836.600552                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34836.600552                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70688.926963                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70688.926963                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39856.122569                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37598.564237                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39856.122569                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45125.794791                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.232345                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46524.206004                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 71210.429271                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29077.941831                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29077.941831                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19327.799487                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19327.799487                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       871500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       871500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.823294                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 59061.823294                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33530.157161                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33530.157161                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36936.760880                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36936.760880                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70704.254236                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70704.254236                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33530.157161                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41701.755914                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39318.158299                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33530.157161                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41701.755914                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48867.682111                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188395.024618                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158055.681482                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182436.304140                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182436.304140                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188040.393789                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158189.370472                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185309.277268                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 166296.548261                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     24114479                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12402894                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2291                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      1959388                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1958967                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          421                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        868302                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     10703945                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        20725                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        20724                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5471023                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      7766214                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2549883                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       981532                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       467602                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       343874                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       514595                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1212904                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1189199                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5849954                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4880551                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       848509                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       789376                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17591867                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18635587                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       390565                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1180743                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         37798762                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    749097616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    700307787                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1488232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4460536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1455354171                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    6848442                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     19646181                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.117106                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.321630                       # Request fanout histogram
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90440.398321                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104161.342648                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests     23859843                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12280153                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1945                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      2008292                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2007802                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          490                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        875651                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     10557046                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        21267                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        21266                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5532941                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      7629125                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2654810                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1033772                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       476440                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       348822                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       520615                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1237465                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1213308                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5681636                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4942147                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       844889                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       786739                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17086897                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18759020                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       394013                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1192566                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         37432496                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    727551888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    705113777                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1504832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4510600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1438681097                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    7112172                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     19795414                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.118782                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.323609                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          17346012     88.29%     88.29% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2299647     11.71%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               522      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          17444556     88.12%     88.12% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2350368     11.87%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               490      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      19646181                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   23957915414                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    186819649                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      19795414                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   23702360441                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    185100538                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   8802550782                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   8549815301                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8265265885                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8326796053                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    204815934                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    206206896                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    623887061                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    629446573                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              135174598                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         89157012                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6771553                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            95119508                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               59219614                       # Number of BTB hits
+system.cpu1.branchPred.lookups              144214101                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         95658264                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          7037471                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups           101536339                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               63283833                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            62.258116                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               18509493                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            199065                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        4260619                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           2645570                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         1615049                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       400784                       # Number of mispredicted indirect branches.
+system.cpu1.branchPred.BTBHitPct            62.326290                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               19487906                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            205159                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4571638                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2870819                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1700819                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       415354                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1734,87 +1715,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   620331                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               620331                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        13694                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        99863                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       301286                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       319045                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2609.283957                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 15339.812797                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       316072     99.07%     99.07% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1597      0.50%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607         1113      0.35%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          132      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679           45      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   655828                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               655828                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        14723                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3       107099                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       315531                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       340297                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2456.990511                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 14831.918999                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       337419     99.15%     99.15% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1530      0.45%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607         1096      0.32%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          124      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           45      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::327680-393215           65      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           13      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           10      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       319045                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       336255                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 21304.924834                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17913.652779                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 23319.449537                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       331614     98.62%     98.62% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1015      0.30%     98.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         2524      0.75%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          218      0.06%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          559      0.17%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215          132      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751          112      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           49      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823           16      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::786432-851967            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       340297                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       353965                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 21023.430283                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17819.927272                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 22140.509228                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       349562     98.76%     98.76% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1039      0.29%     99.05% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         2363      0.67%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          142      0.04%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          520      0.15%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          154      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751          109      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           57      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       336255                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 493108416476                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.613633                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.555238                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 491595088976     99.69%     99.69% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    828838000      0.17%     99.86% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    323227000      0.07%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    140968000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9    113706500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     58901000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     19970500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     26949000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       748000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19        19500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 493108416476                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        99864     87.94%     87.94% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        13694     12.06%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       113558                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       620331                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       353965                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 524755655220                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.627277                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.547876                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 523184603720     99.70%     99.70% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    876126000      0.17%     99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    338256000      0.06%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    142712500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9    110713000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     57399000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     19068500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     26227000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       540000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19         6500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21         1500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23         1500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 524755655220                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K       107100     87.91%     87.91% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        14723     12.09%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       121823                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       655828                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       620331                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       113558                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       655828                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       121823                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       113558                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       733889                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       121823                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       777651                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    99541236                       # DTB read hits
-system.cpu1.dtb.read_misses                    446261                       # DTB read misses
-system.cpu1.dtb.write_hits                   80566614                       # DTB write hits
-system.cpu1.dtb.write_misses                   174070                       # DTB write misses
-system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   106468062                       # DTB read hits
+system.cpu1.dtb.read_misses                    473211                       # DTB read misses
+system.cpu1.dtb.write_hits                   85858726                       # DTB write hits
+system.cpu1.dtb.write_misses                   182617                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   43247                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      634                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6731                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   44338                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      492                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  7273                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    41159                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                99987497                       # DTB read accesses
-system.cpu1.dtb.write_accesses               80740684                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    40937                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               106941273                       # DTB read accesses
+system.cpu1.dtb.write_accesses               86041343                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        180107850                       # DTB hits
-system.cpu1.dtb.misses                         620331                       # DTB misses
-system.cpu1.dtb.accesses                    180728181                       # DTB accesses
+system.cpu1.dtb.hits                        192326788                       # DTB hits
+system.cpu1.dtb.misses                         655828                       # DTB misses
+system.cpu1.dtb.accesses                    192982616                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1844,1175 +1827,1148 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    88034                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                88034                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1080                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        62024                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        10531                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        77503                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1737.752087                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 13376.771603                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        76531     98.75%     98.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          407      0.53%     99.27% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303           54      0.07%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071          157      0.20%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839          274      0.35%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607           44      0.06%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        77503                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        73635                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28077.836627                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23325.571005                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 31326.629409                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        71135     96.60%     96.60% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          154      0.21%     96.81% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1986      2.70%     99.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143          113      0.15%     99.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679          137      0.19%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           53      0.07%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           44      0.06%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    90500                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                90500                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1174                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        63013                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        10919                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        79581                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1858.653447                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 14270.720139                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535        78947     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071          217      0.27%     99.48% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607          367      0.46%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143           26      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679           15      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-393215            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        79581                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        75106                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27703.186164                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23129.879308                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 30256.665627                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        72610     96.68%     96.68% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          191      0.25%     96.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1968      2.62%     99.55% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143          115      0.15%     99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679          133      0.18%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           46      0.06%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           21      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        73635                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 428680982536                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.877576                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.328123                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    52527553308     12.25%     12.25% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   376108944728     87.74%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       42347500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        2103500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          33500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 428680982536                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        62024     98.29%     98.29% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         1080      1.71%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        63104                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        75106                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 438856254800                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.887236                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.316700                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    49536953716     11.29%     11.29% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   389273644084     88.70%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       42101500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        2811500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         744000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 438856254800                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        63013     98.17%     98.17% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         1174      1.83%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        64187                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        88034                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        88034                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        90500                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        90500                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63104                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63104                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       151138                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   212987962                       # ITB inst hits
-system.cpu1.itb.inst_misses                     88034                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        64187                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        64187                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       154687                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   226870355                       # ITB inst hits
+system.cpu1.itb.inst_misses                     90500                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   31450                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              46091                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1084                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   32400                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   212403                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   223247                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               213075996                       # ITB inst accesses
-system.cpu1.itb.hits                        212987962                       # DTB hits
-system.cpu1.itb.misses                          88034                       # DTB misses
-system.cpu1.itb.accesses                    213075996                       # DTB accesses
-system.cpu1.numCycles                       763303942                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               226960855                       # ITB inst accesses
+system.cpu1.itb.hits                        226870355                       # DTB hits
+system.cpu1.itb.misses                          90500                       # DTB misses
+system.cpu1.itb.accesses                    226960855                       # DTB accesses
+system.cpu1.numCycles                       812532558                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          89198965                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     599138491                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  135174598                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          80374677                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    631697152                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               14629606                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2135822                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              325301                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6190061                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       869593                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       862105                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                212754259                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1709590                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  28554                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         738593802                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.951348                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.213932                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          91759705                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     638580491                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  144214101                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          85642558                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    676433492                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               15215298                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2168545                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              336979                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      6484962                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       887415                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       890942                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                226625049                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1736948                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  29701                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         786569689                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.951781                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.213726                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               402298959     54.47%     54.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               130678569     17.69%     72.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                44867308      6.07%     78.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               160748966     21.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               428022323     54.42%     54.42% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               139668800     17.76%     72.17% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                47662444      6.06%     78.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               171216122     21.77%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           738593802                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.177091                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.784928                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               106478117                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            366845169                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                222515957                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             37512815                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5241744                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19111386                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              2112679                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             619567000                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             23338360                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5241744                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               141946273                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               54617946                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     243861784                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                224134357                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             68791698                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             602126263                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              6118576                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents             11056239                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                380631                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                940722                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              33286587                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           12083                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          573060902                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            928019832                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       710062229                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           649328                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            514926448                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                58134448                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          16118585                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      14068970                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 75560239                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            99853363                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           83838519                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          9473424                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         8115334                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 579120615                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           16293769                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                584059770                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2714782                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       54810980                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     35376701                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        290425                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    738593802                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.790773                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.055961                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           786569689                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.177487                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.785914                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               110960591                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            393393476                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                236254465                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             40475350                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5485807                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            20188292                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              2163849                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             661116472                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             24295467                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5485807                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               148680347                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               59294510                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     260447701                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                238523513                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             74137811                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             642734014                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              6463851                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents             12050420                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                431614                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1024133                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              35807802                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           12087                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          613144176                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            993338486                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       758389620                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           787806                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            551826661                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                61317509                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          17340731                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      15198476                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 81471302                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           106673767                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           89326102                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         10094322                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         8631476                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 618122262                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           17529509                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                623787865                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2873824                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       57783921                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     37389903                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        307135                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    786569689                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.793048                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.056857                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          417929764     56.58%     56.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          136913052     18.54%     75.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          111746112     15.13%     90.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           64370034      8.72%     98.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7629808      1.03%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               5032      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          444068370     56.46%     56.46% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          146437024     18.62%     75.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          119059525     15.14%     90.21% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           68792645      8.75%     98.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            8206769      1.04%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               5356      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      738593802                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      786569689                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               58567749     44.20%     44.20% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 70680      0.05%     44.25% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                  16113      0.01%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              26      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              36085591     27.23%     71.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             37772354     28.50%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               62505184     44.18%     44.18% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 68578      0.05%     44.23% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  15954      0.01%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              29      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              38525280     27.23%     71.47% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             40370294     28.53%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               36      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            397950619     68.14%     68.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1394287      0.24%     68.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                80723      0.01%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  4      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         45828      0.01%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           102773744     17.60%     85.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           81814529     14.01%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               56      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            425111535     68.15%     68.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1458161      0.23%     68.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                82493      0.01%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  4      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                1      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   1      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         80022      0.01%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           109884961     17.62%     86.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           87170631     13.97%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             584059770                       # Type of FU issued
-system.cpu1.iq.rate                          0.765173                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  132512513                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.226882                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        2040871763                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        649951389                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    566663887                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1068872                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            423239                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       394625                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             715907019                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 665228                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2663748                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             623787865                       # Type of FU issued
+system.cpu1.iq.rate                          0.767708                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  141485319                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.226816                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        2177185436                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        693073885                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    605244442                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1319124                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            525529                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       491804                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             764456486                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 816642                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2875534                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     12784321                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        18121                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       150654                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5561892                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     13536096                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        19732                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       165171                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5907805                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2706765                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      4288761                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2920913                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      4601873                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5241744                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                8152179                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2696224                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          595550479                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               5485807                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                8833718                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              2787810                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          635796262                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             99853363                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            83838519                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13801566                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 59598                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              2567849                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        150654                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1960671                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      3092522                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             5053193                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            576018607                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             99536730                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          7427921                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts            106673767                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            89326102                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          14923932                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 69191                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              2639688                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        165171                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2071854                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      3210854                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             5282708                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            615332242                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            106464546                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          7808914                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       136095                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   180100552                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               107831822                       # Number of branches executed
-system.cpu1.iew.exec_stores                  80563822                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.754639                       # Inst execution rate
-system.cpu1.iew.wb_sent                     567845555                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    567058512                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                275064587                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                450436874                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.742900                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.610662                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       47911948                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       16003344                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4698494                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    729478017                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.741083                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.544204                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       144491                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   192321367                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               115394599                       # Number of branches executed
+system.cpu1.iew.exec_stores                  85856821                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.757302                       # Inst execution rate
+system.cpu1.iew.wb_sent                     606557665                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    605736246                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                294174085                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                482464820                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.745492                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.609732                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       50535620                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       17222374                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4915629                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    776983088                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.743733                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.546908                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    491334549     67.35%     67.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    124605119     17.08%     84.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     52434637      7.19%     91.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     17448264      2.39%     94.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     12346698      1.69%     95.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      8646744      1.19%     96.89% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5821113      0.80%     97.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3490122      0.48%     98.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     13350771      1.83%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    522401316     67.23%     67.23% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    133381083     17.17%     84.40% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     55837578      7.19%     91.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     18787317      2.42%     94.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     13118953      1.69%     95.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      9117290      1.17%     96.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      6295998      0.81%     97.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3737021      0.48%     98.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     14306532      1.84%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    729478017                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           459298656                       # Number of instructions committed
-system.cpu1.commit.committedOps             540603397                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    776983088                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           491216523                       # Number of instructions committed
+system.cpu1.commit.committedOps             577867843                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     165345668                       # Number of memory references committed
-system.cpu1.commit.loads                     87069041                       # Number of loads committed
-system.cpu1.commit.membars                    3858315                       # Number of memory barriers committed
-system.cpu1.commit.branches                 102318506                       # Number of branches committed
-system.cpu1.commit.fp_insts                    386565                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                496515316                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13693042                       # Number of function calls committed.
+system.cpu1.commit.refs                     176555967                       # Number of memory references committed
+system.cpu1.commit.loads                     93137670                       # Number of loads committed
+system.cpu1.commit.membars                    4128399                       # Number of memory barriers committed
+system.cpu1.commit.branches                 109594417                       # Number of branches committed
+system.cpu1.commit.fp_insts                    483207                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                530271703                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            14440728                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       374009133     69.18%     69.18% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1144857      0.21%     69.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           64258      0.01%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        39481      0.01%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       87069041     16.11%     85.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      78276627     14.48%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       399975864     69.22%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1198206      0.21%     69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           65313      0.01%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        72493      0.01%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       93137670     16.12%     85.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      83418297     14.44%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        540603397                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             13350771                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1300306905                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1186107059                       # The number of ROB writes
-system.cpu1.timesIdled                        1002683                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       24710140                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94016410262                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  459298656                       # Number of Instructions Simulated
-system.cpu1.committedOps                    540603397                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.661890                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.661890                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.601724                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.601724                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               679475596                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              404035591                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   636627                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  333028                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                123323505                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               123972693                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1293234240                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15956756                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5664060                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          461.921265                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          153938367                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5664570                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            27.175649                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8482615799500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   461.921265                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.902190                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.902190                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu1.commit.op_class_0::total        577867843                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             14306532                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1386603636                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1266352729                       # The number of ROB writes
+system.cpu1.timesIdled                        1031751                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       25962869                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 94124971438                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  491216523                       # Number of Instructions Simulated
+system.cpu1.committedOps                    577867843                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.654123                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.654123                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.604550                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.604550                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               726234004                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              431188126                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   774766                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  462404                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                133303662                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               133988748                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1377831690                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              17262707                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          6040824                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          459.378668                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          164299100                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          6041336                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            27.195822                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8482617709500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   459.378668                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.897224                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.897224                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          393                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        343399100                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       343399100                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     81011302                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       81011302                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     68259476                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      68259476                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       190553                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       190553                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       137870                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       137870                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1767079                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1767079                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1811409                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1811409                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    149270778                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       149270778                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    149461331                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      149461331                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6609494                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6609494                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      7403019                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      7403019                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       691160                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       691160                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       462153                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       462153                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       284407                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       284407                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       195281                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       195281                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     14012513                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      14012513                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     14703673                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     14703673                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 113682780000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 113682780000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 163432974267                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 163432974267                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  19652724076                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  19652724076                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4573915000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   4573915000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5496232500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   5496232500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5776500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5776500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 277115754267                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 277115754267                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 277115754267                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 277115754267                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     87620796                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     87620796                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     75662495                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     75662495                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       881713                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       881713                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       600023                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       600023                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2051486                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2051486                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2006690                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2006690                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    163283291                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    163283291                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    164165004                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    164165004                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075433                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.075433                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.097843                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.097843                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.783883                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.783883                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.770225                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.770225                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.138635                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.138635                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097315                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097315                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.085817                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.085817                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.089566                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.089566                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17199.921809                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 17199.921809                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22076.530435                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 22076.530435                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42524.281084                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42524.281084                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16082.287004                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16082.287004                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28145.249666                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28145.249666                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          401                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        366496301                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       366496301                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     86507946                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       86507946                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     72726229                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      72726229                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       199332                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       199332                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       142639                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       142639                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1934214                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1934214                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1984655                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1984655                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    159376814                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       159376814                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    159576146                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      159576146                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      7084890                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      7084890                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      7887926                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      7887926                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       742812                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       742812                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       468512                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       468512                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       301623                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       301623                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       202162                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       202162                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     15441328                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      15441328                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     16184140                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     16184140                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 122386342500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 122386342500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 173974758337                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 173974758337                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20327422974                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  20327422974                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   5004935500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   5004935500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5709587500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5709587500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3496000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3496000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 316688523811                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 316688523811                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 316688523811                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 316688523811                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     93592836                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     93592836                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     80614155                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     80614155                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       942144                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       942144                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       611151                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       611151                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2235837                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2235837                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2186817                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2186817                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    174818142                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    174818142                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    175760286                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    175760286                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075699                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.075699                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.097848                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.097848                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.788427                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.788427                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.766606                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.766606                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.134904                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.134904                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.092446                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.092446                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.088328                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.088328                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.092081                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.092081                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17274.275606                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 17274.275606                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22055.830435                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22055.830435                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 43387.198138                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 43387.198138                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16593.348319                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16593.348319                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28242.634620                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28242.634620                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19776.306667                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19776.306667                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18846.702743                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18846.702743                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      5374733                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     26726963                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           381404                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         750366                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.091968                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    35.618569                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      5664164                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5664164                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3334691                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3334691                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5984035                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5984035                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3399                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         3399                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       145205                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       145205                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      9318726                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      9318726                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      9318726                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      9318726                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3274803                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3274803                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1418984                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1418984                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       691046                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       691046                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       458754                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       458754                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       139202                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       139202                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195277                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       195277                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4693787                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4693787                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5384833                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5384833                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        19232                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        19232                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        17726                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        17726                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        36958                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        36958                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  51262951500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  51262951500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  34883587324                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  34883587324                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16764876500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16764876500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19026160076                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19026160076                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   2027619500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   2027619500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5301023500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5301023500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5708500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5708500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  86146538824                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  86146538824                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102911415324                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 102911415324                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3119149500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3119149500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2971127000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2971127000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   6090276500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   6090276500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037375                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037375                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018754                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018754                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.783754                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.783754                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.764561                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.764561                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067854                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067854                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097313                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097313                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028746                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028746                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032801                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032801                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15653.751233                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15653.751233                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24583.495884                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24583.495884                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24260.145490                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24260.145490                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41473.556800                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41473.556800                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14566.022758                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14566.022758                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27146.174409                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27146.174409                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20509.150755                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20509.150755                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19567.831458                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19567.831458                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      5568492                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     28779495                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           387755                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         802381                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.360852                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    35.867618                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks      6040976                       # number of writebacks
+system.cpu1.dcache.writebacks::total          6040976                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3573916                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3573916                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6375716                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      6375716                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3475                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3475                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       153685                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       153685                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      9953107                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      9953107                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      9953107                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      9953107                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3510974                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3510974                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1512210                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1512210                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       742708                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       742708                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       465037                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       465037                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       147938                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       147938                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       202156                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       202156                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      5488221                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      5488221                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      6230929                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      6230929                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        18701                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        18701                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        17029                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        17029                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        35730                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        35730                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  55262810500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  55262810500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  37074565990                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  37074565990                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  18477747500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  18477747500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19695654974                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19695654974                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   2170800500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   2170800500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5507478500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5507478500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3449000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3449000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 112033031464                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 112033031464                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 130510778964                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 130510778964                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3038329000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3038329000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3038329000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3038329000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037513                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037513                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018759                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018759                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.788317                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.788317                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.760920                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.760920                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066167                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066167                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.092443                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.092443                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031394                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031394                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035451                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035451                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15740.022712                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15740.022712                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24516.810489                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24516.810489                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24878.885780                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24878.885780                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42352.877242                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 42352.877242                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14673.718044                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14673.718044                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27243.705356                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27243.705356                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18353.312331                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18353.312331                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19111.347617                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19111.347617                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162185.394135                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162185.394135                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167614.069728                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167614.069728                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164789.125494                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 164789.125494                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          6084021                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.481326                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          206310871                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          6084533                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            33.907429                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8522353869000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.481326                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979456                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.979456                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20413.360079                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20413.360079                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20945.637314                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20945.637314                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162468.798460                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162468.798460                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 85035.796250                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 85035.796250                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.replacements          6229961                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.669710                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          220025292                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          6230473                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            35.314380                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8522353535000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.669710                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979824                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.979824                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          345                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        431579068                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       431579068                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    206310871                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      206310871                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    206310871                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       206310871                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    206310871                       # number of overall hits
-system.cpu1.icache.overall_hits::total      206310871                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      6436378                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      6436378                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      6436378                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       6436378                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      6436378                       # number of overall misses
-system.cpu1.icache.overall_misses::total      6436378                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  72269477183                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  72269477183                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  72269477183                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  72269477183                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  72269477183                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  72269477183                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    212747249                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    212747249                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    212747249                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    212747249                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    212747249                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    212747249                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030254                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.030254                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030254                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.030254                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030254                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.030254                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11228.283544                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 11228.283544                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11228.283544                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 11228.283544                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11228.283544                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 11228.283544                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs     11099833                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          317                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           762485                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.557444                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets    79.250000                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks      6084021                       # number of writebacks
-system.cpu1.icache.writebacks::total          6084021                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       351808                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       351808                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       351808                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       351808                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       351808                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       351808                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      6084570                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      6084570                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      6084570                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      6084570                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      6084570                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      6084570                       # number of overall MSHR misses
+system.cpu1.icache.tags.tag_accesses        459465626                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       459465626                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    220025292                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      220025292                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    220025292                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       220025292                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    220025292                       # number of overall hits
+system.cpu1.icache.overall_hits::total      220025292                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      6592262                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      6592262                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      6592262                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       6592262                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      6592262                       # number of overall misses
+system.cpu1.icache.overall_misses::total      6592262                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  74756974451                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  74756974451                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  74756974451                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  74756974451                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  74756974451                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  74756974451                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    226617554                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    226617554                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    226617554                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    226617554                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    226617554                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    226617554                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029090                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.029090                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029090                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.029090                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029090                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.029090                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11340.109730                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 11340.109730                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11340.109730                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 11340.109730                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11340.109730                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 11340.109730                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs     11528745                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          835                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           773545                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              6                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.903781                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets   139.166667                       # average number of cycles each access was blocked
+system.cpu1.icache.writebacks::writebacks      6229961                       # number of writebacks
+system.cpu1.icache.writebacks::total          6229961                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       361744                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       361744                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       361744                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       361744                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       361744                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       361744                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      6230518                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      6230518                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      6230518                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      6230518                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      6230518                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      6230518                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  65151824817                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  65151824817                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  65151824817                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  65151824817                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  65151824817                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  65151824817                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9154498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9154498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9154498                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      9154498                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028600                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.028600                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.028600                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10707.712265                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10707.712265                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10707.712265                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136634.298507                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136634.298507                       # average overall mshr uncacheable latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7756566                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7763412                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         6220                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  67349232950                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  67349232950                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  67349232950                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  67349232950                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  67349232950                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  67349232950                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8957498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8957498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8957498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8957498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027494                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027494                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027494                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.027494                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027494                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.027494                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10809.572005                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10809.572005                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10809.572005                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10809.572005                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10809.572005                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10809.572005                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst       133694                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total       133694                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst       133694                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total       133694                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      8304723                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      8311187                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         5839                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       969756                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2332043                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13399.306231                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          17632836                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2347889                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.510081                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9842790935000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12578.549266                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    73.835699                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.403592                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   671.517674                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.767734                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004507                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004602                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.040986                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.817829                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1168                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           87                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14591                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          213                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          557                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          388                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           63                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
+system.cpu1.l2cache.prefetcher.pfSpanPage      1024317                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2528309                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13413.609149                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          18251408                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2544361                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.173278                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9891515003500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12660.361458                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    61.649049                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    73.939309                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000012                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   617.659322                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.772727                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003763                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004513                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.000000                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.037699                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.818702                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1288                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           59                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14705                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          259                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          581                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          431                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           38                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1235                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4922                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4629                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3692                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.071289                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005310                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.890564                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       403369890                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      403369890                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       629324                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       196368                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        825692                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3534370                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3534370                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      8212493                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      8212493                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          814                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          814                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       892249                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       892249                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5494357                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      5494357                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3102678                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      3102678                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       175982                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       175982                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       629324                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       196368                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      5494357                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3994927                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       10314976                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       629324                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       196368                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      5494357                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3994927                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      10314976                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        13918                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10528                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        24446                       # number of ReadReq misses
-system.cpu1.l2cache.WritebackDirty_misses::writebacks            2                       # number of WritebackDirty misses
-system.cpu1.l2cache.WritebackDirty_misses::total            2                       # number of WritebackDirty misses
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1409                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5268                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4214                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3711                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078613                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003601                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.897522                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       421641447                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      421641447                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       670573                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       201040                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        871613                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3790012                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3790012                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      8479233                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      8479233                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          992                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          992                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            7                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total            7                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       953658                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       953658                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5605859                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      5605859                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3317239                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      3317239                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       173754                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       173754                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       670573                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       201040                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      5605859                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      4270897                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       10748369                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       670573                       # number of overall hits
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 system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
 system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
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-system.cpu1.l2cache.WritebackDirty_accesses::total      3534372                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000000                       # miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000000                       # miss rate for WritebackDirty accesses
 system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
 system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996503                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996503                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
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+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999965                       # miss rate for SCUpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.252287                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.252287                       # miss rate for ReadExReq accesses
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-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.096995                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.243715                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.243715                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.614820                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.614820                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021637                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050885                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.096995                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.245646                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.156618                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021637                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050885                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.096995                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.245646                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.156618                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 57796.858382                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15194.075246                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15194.075246                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10004.883033                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10004.883033                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622833.222222                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622833.222222                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58439.638933                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58439.638933                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38511.607731                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38511.607731                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43191.477474                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43191.477474                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1475.489498                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1475.489498                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38511.607731                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 46720.212749                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 44332.515181                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38511.607731                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 46720.212749                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 44332.515181                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs         1668                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.248580                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.248580                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.100252                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.100252                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.245778                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.245778                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.624819                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.624819                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020071                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048935                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.100252                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246406                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.159859                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020071                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048935                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.100252                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246406                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.159859                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 56014.015289                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 63079.321346                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 59049.171477                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14885.158453                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14885.158453                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10164.650797                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10164.650797                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1125832.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1125832.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58894.858043                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58894.858043                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38502.808930                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38502.808930                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43623.931282                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43623.931282                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1643.686046                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1643.686046                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 56014.015289                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 63079.321346                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38502.808930                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 47073.849603                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 44597.158558                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 56014.015289                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 63079.321346                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38502.808930                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 47073.849603                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 44597.158558                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs         1476                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs              18                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs              14                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    92.666667                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   105.428571                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.unused_prefetches           46928                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks      1248737                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1248737                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            4                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            8                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        53310                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        53310                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         6042                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         6042                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            6                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            8                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        59352                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        59366                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            4                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            8                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        59352                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        59366                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        13914                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10520                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        24434                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            2                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::total            2                       # number of WritebackDirty MSHR misses
+system.cpu1.l2cache.unused_prefetches           50570                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1373649                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1373649                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            2                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadExReq_mshr_hits::total        59817                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         6475                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         6475                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            7                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            7                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        66292                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
 system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
 system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       810022                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       810022                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       231959                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       231959                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       195268                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       195268                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            9                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       247745                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       247745                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       590165                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       590165                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       993804                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       993804                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       280894                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       280894                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        13914                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10520                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       590165                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1241549                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1856148                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        13914                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10520                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       590165                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1241549                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       810022                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2666170                       # number of overall MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       868323                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       868323                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       250358                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       250358                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       202146                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       202146                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       624615                       # number of ReadCleanReq MSHR misses
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+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       289360                       # number of InvalidateReq MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        19232                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        19299                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        17726                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        17726                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        18701                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        18768                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        17029                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        17029                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        36958                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        37025                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1265966500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  58037263327                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  58037263327                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   7346311996                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7346311996                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3833341496                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3833341496                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      5197499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5197499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  12807729999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  12807729999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  19187264000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  19187264000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  36825734486                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  36825734486                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  14981372997                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  14981372997                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  19187264000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  49633464485                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  70086694985                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  19187264000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  49633464485                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  58037263327                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 128123958312                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8651000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2965138000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2973789000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2838108000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2838108000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8651000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5803246000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5811897000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028741                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        35730                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        35797                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    686821000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    590353500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1277174500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  65644901114                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  65644901114                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   7861561998                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7861561998                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3988088997                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3988088997                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3095498                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3095498                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  13308484000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  13308484000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20301742000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20301742000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  40328599477                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  40328599477                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  15597274497                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  15597274497                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    686821000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    590353500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20301742000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  53637083477                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  75215999977                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    686821000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    590353500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20301742000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  53637083477                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  65644901114                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 140860901091                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8454000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2888554500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2897008500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8454000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2888554500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2897008500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020068                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048892                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026871                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996503                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996503                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996053                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996053                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999965                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999965                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.207613                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.207613                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096994                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.242242                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242242                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.614806                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.614806                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234439                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.151764                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234439                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.201448                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.201448                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.100252                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.100252                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.244306                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.244306                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.624804                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.624804                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020068                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.048892                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.100252                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234709                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.154677                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020068                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.048892                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.100252                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234709                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.217994                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 51811.676353                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 71648.996357                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31670.734897                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31670.734897                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19631.181228                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19631.181228                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 577499.888889                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 577499.888889                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 51697.229002                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 51697.229002                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32511.694187                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37055.329306                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37055.329306                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53334.613758                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53334.613758                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 39977.048417                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 37759.216929                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 39977.048417                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 48055.434692                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154177.308652                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154090.315560                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160109.895069                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 160109.895069                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 157022.728503                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 156972.234976                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     24388069                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12550954                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1330                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      2014096                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2013701                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          395                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        959951                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     11237676                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        17726                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        17726                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4787619                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      8213812                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2728404                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1028067                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       448479                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       348012                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       489399                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           78                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1222080                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1199432                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      6084570                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5051662                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       514998                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       456882                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18253249                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18257850                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       433982                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1356808                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         38301889                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    778787952                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    707763692                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1655168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      5145936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1493352748                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    6663078                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     19657279                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.121604                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.326890                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.222549                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 53065.252618                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 75599.634138                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31401.281357                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31401.281357                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19728.755439                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19728.755439                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1031832.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031832.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52054.180063                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52054.180063                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32502.808930                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32502.808930                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37531.909259                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37531.909259                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53902.662763                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53902.662763                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32502.808930                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40323.146607                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38009.686354                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32502.808930                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40323.146607                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 49473.708995                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154459.895193                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154358.935422                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 80843.954660                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 80928.806883                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests     25472686                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     13111869                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1712                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      2149417                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2149008                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          409                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq       1009964                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     11730214                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        17029                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        17029                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      5169290                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      8480923                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2927219                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1103039                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       459055                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       356155                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       515583                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           73                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1297103                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1275135                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      6230518                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5372910                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       516382                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       463121                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18691087                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     19440124                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       443982                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1442906                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         40018099                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    797468912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    755702222                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1691072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      5474464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1560336670                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    7082459                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     20668727                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.122834                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.328306                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          17267267     87.84%     87.84% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2389617     12.16%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               395      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          18130322     87.72%     87.72% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2537996     12.28%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               409      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      19657279                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   24252664474                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      20668727                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   25335696459                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    176228657                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    177629109                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   9133388497                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   9352273561                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8423069488                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8995491238                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    227423320                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    232944299                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    714183249                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    759270636                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40322                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40322                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136632                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136632                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47654                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40305                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40305                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136595                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136595                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47570                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -3025,13 +2981,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122588                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231240                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231240                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122504                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231216                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231216                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353908                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47674                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353800                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47590                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3044,21 +3000,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155695                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338976                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338976                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155611                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338880                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338880                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496757                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36957001                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496577                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36858001                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               329000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               326000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -3072,73 +3028,73 @@ system.iobus.reqLayer16.occupancy               13500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            24079502                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            24204504                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36400000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36391000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567357875                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           567248472                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92687000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92640000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147936000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147912000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115615                       # number of replacements
-system.iocache.tags.tagsinuse               11.303922                       # Cycle average of tags in use
+system.iocache.tags.replacements               115604                       # number of replacements
+system.iocache.tags.tagsinuse               11.311799                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115631                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115620                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9121269324000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.412531                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.891391                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.463283                       # Average percentage of cache occupancy
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 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
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-system.iocache.ReadReq_miss_latency::total   1713740013                       # number of ReadReq miss cycles
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 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
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-system.iocache.WriteLineReq_miss_latency::total  13535070862                       # number of WriteLineReq miss cycles
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-system.iocache.demand_miss_latency::total   1714109013                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5567500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1708541513                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1714109013                       # number of overall miss cycles
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 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8892                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8932                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8892                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8932                       # number of overall (read+write) accesses
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 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3152,55 +3108,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       140500                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 192143.669928                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 191929.668832                       # average ReadReq miss latency
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+system.iocache.ReadReq_avg_miss_latency::realview.ide 188583.005068                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 188385.284849                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126818.368769                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126818.368769                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 192143.669928                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 191906.517353                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 192143.669928                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 191906.517353                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34688                       # number of cycles access was blocked
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+system.iocache.WriteLineReq_avg_miss_latency::total 126942.788087                       # average WriteLineReq miss latency
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+system.iocache.demand_avg_miss_latency::total 131680.188780                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139587.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 131677.452875                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 131680.188780                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         33801                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3476                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3396                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.979287                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.953180                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106693                       # number of writebacks
-system.iocache.writebacks::total               106693                       # number of writebacks
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8892                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8929                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8880                       # number of ReadReq MSHR misses
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 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8892                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8932                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8892                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8932                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1263941513                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1267290013                       # number of ReadReq MSHR miss cycles
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+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1230617085                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1233981585                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8192379111                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8192379111                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3567500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1263941513                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1267509013                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3567500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1263941513                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1267509013                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8205400767                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8205400767                       # number of WriteLineReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::realview.ide   9436017852                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9439601352                       # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::realview.ide   9436017852                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9439601352                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3214,649 +3168,643 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        90500                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142143.669928                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 141929.668832                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90932.432432                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138583.005068                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 138385.284849                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76759.417501                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76759.417501                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 142143.669928                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 141906.517353                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 142143.669928                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 141906.517353                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1503046                       # number of replacements
-system.l2c.tags.tagsinuse                63375.622092                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6171586                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1562708                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.949289                       # Average number of references to valid blocks.
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76881.425371                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76881.425371                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89587.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 81620.803508                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 81623.559007                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89587.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 81620.803508                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 81623.559007                       # average overall mshr miss latency
+system.l2c.tags.replacements                  1658646                       # number of replacements
+system.l2c.tags.tagsinuse                63614.355421                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6503693                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1717473                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.786780                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle               4906135000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   21677.292557                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    83.067014                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    94.369601                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3446.989039                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6115.798225                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  4388.751690                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   261.257745                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   419.349614                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3918.629584                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8309.441217                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14660.675806                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.330769                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001268                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.001440                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.052597                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.093320                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.066967                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003986                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006399                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.059794                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.126792                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.223704                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.967035                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022         9545                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          198                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        49919                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          721                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          554                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         8260                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          193                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          332                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2886                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5698                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        40984                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.145645                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003021                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.761703                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 78456956                       # Number of tag accesses
-system.l2c.tags.data_accesses                78456956                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks      2864457                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2864457                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total               1                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data          177336                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          132362                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              309698                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         38451                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         42622                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             81073                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            52385                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            53709                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               106094                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6384                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4273                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       499570                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       608768                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       311188                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6757                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4531                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       536739                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       583922                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       292843                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2854975                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       132875                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       127159                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           260034                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6384                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4273                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              499570                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              661153                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       311188                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6757                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4531                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              536739                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              637631                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       292843                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2961069                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6384                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4273                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             499570                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             661153                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       311188                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6757                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4531                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             536739                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             637631                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       292843                       # number of overall hits
-system.l2c.overall_hits::total                2961069                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         62895                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         64271                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            127166                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        12027                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        12595                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           24622                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          80267                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          60030                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140297                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1639                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1057                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        49818                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       124211                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       228039                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3279                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3223                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        53421                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       140654                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       285232                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         890573                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       448396                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       141685                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         590081                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1639                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1057                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             49818                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            204478                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       228039                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         3279                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         3223                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             53421                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            200684                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       285232                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1030870                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1639                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1057                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            49818                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           204478                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       228039                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         3279                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         3223                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            53421                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           200684                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       285232                       # number of overall misses
-system.l2c.overall_misses::total              1030870                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data   1112376000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data   1041657500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   2154033500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    166517500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    204256500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    370774000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  11267452492                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   8441524499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  19708976991                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    239750000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    155989500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6853821500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  17860631492                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  42675512933                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    464430000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    455098500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   7368110000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  20598242999                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  52661073904                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 149332660828                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data    199010000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data    130631000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total    329641000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    239750000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    155989500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6853821500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  29128083984                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  42675512933                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    464430000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    455098500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   7368110000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  29039767498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  52661073904                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    169041637819                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    239750000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    155989500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6853821500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  29128083984                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  42675512933                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    464430000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    455098500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   7368110000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  29039767498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  52661073904                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   169041637819                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2864457                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2864457                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       240231                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       196633                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          436864                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        50478                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        55217                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        105695                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       132652                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       113739                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           246391                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         8023                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5330                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       549388                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       732979                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       539227                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        10036                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7754                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       590160                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       724576                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       578075                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3745548                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       581271                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       268844                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       850115                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8023                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5330                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          549388                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          865631                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       539227                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        10036                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         7754                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          590160                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          838315                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       578075                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3991939                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8023                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5330                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         549388                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         865631                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       539227                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        10036                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         7754                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         590160                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         838315                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       578075                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3991939                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.261811                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.326858                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.291088                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.238262                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.228100                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.232953                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.605095                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.527787                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.569408                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.090679                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.169461                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.090520                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.194119                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.237768                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.771406                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.527016                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.694119                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.090679                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.236218                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.090520                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.239390                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.258238                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.090679                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.236218                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.090520                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.239390                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.258238                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17686.238970                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16207.270775                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 16938.753283                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13845.306394                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16217.268757                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 15058.646739                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 140374.655736                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 140621.764101                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 140480.387970                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137577.211048                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 143792.671277                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137925.347710                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146446.194200                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 167681.549775                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   443.826439                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   921.981861                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   558.636865                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 137577.211048                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 142450.943300                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 137925.347710                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 144703.949981                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 163979.587939                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 137577.211048                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 142450.943300                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 137925.347710                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 144703.949981                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 163979.587939                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             14431                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   21778.868920                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    77.174149                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   104.892582                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3369.245029                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4690.877672                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  5127.772728                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   275.118534                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   421.752346                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3923.044466                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    10215.764671                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13629.844323                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.332319                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001178                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.001601                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.051411                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.071577                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.078244                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004198                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006435                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.059861                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.155880                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.207975                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.970678                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9349                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          246                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        49232                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           12                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1           39                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          275                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          523                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         8500                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          244                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2922                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4073                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        41884                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.142654                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003754                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.751221                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 83070472                       # Number of tag accesses
+system.l2c.tags.data_accesses                83070472                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      3045027                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         3045027                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks            2                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total               2                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data          177681                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          151575                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              329256                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         38520                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         46161                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             84681                       # number of SCUpgradeReq hits
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+system.l2c.ReadExReq_hits::total               115184                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6506                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4755                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::cpu0.data       629843                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       303617                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6637                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4374                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       567907                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       649267                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       304398                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2982502                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       134777                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       127780                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           262557                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6506                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.inst              567907                       # number of demand (read+write) hits
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+system.l2c.overall_hits::cpu0.dtb.walker         6506                       # number of overall hits
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+system.l2c.overall_hits::cpu0.l2cache.prefetcher       303617                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         6637                       # number of overall hits
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+system.l2c.overall_hits::cpu1.inst             567907                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             706135                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       304398                       # number of overall hits
+system.l2c.overall_hits::total                3097686                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         62380                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total            130233                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        11700                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total           24895                       # number of SCUpgradeReq misses
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+system.l2c.ReadExReq_misses::total             144620                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2677                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       275934                       # number of ReadSharedReq misses
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+system.l2c.InvalidateReq_misses::total         600348                       # number of InvalidateReq misses
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+system.l2c.overall_misses::cpu1.l2cache.prefetcher       324363                       # number of overall misses
+system.l2c.overall_misses::total              1162942                       # number of overall misses
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+system.l2c.UpgradeReq_miss_latency::total   2192020000                       # number of UpgradeReq miss cycles
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+system.l2c.overall_miss_latency::cpu1.inst   7794605500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  31477422990                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  60057715420                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   192609804880                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      3045027                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      3045027                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks            2                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total            2                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       240061                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       219428                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          459489                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        50220                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        59356                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total        109576                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       141041                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       118763                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           259804                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9183                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6645                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       560375                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       769921                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       579551                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        10047                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7643                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       624614                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       804084                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       628761                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      4000824                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       586879                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       276026                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       862905                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         9183                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6645                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          560375                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          910962                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       579551                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        10047                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7643                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          624614                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          922847                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       628761                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4260628                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         9183                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6645                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         560375                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         910962                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       579551                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        10047                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7643                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         624614                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         922847                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       628761                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4260628                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.259851                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.309227                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.283430                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.232975                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.222303                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.227194                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.586532                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.521164                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.556650                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.291517                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.284424                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.098464                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.181938                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.339405                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.427712                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.090787                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.192538                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.254528                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.770350                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.537073                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.695729                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.291517                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.284424                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.098464                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.244580                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.339405                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.427712                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.090787                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.234830                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.272951                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.291517                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.284424                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.098464                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.244580                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.339405                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.427712                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.090787                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.234830                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.272951                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16591.167041                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17052.495837                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 16831.525036                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14902.991453                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17354.262978                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 16202.229363                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 141568.153388                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 141799.482866                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 141667.158630                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143760.926410                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 143657.407407                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 138045.218116                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 148066.737775                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142242.815249                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138625.420618                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137454.026840                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146629.530336                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 169025.023911                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   329.067334                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data  1089.516749                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   516.847728                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143760.926410                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 143657.407407                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 138045.218116                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 145653.864549                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142242.815249                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138625.420618                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 137454.026840                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 145250.023026                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 165622.881347                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143760.926410                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 143657.407407                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 138045.218116                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 145653.864549                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142242.815249                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138625.420618                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 137454.026840                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 145250.023026                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 165622.881347                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             15923                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      146                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      177                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     98.842466                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     89.960452                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1201695                       # number of writebacks
-system.l2c.writebacks::total                  1201695                       # number of writebacks
+system.l2c.writebacks::writebacks             1312187                       # number of writebacks
+system.l2c.writebacks::total                  1312187                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker            3                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          163                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          145                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data            9                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          342                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           34                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          114                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           21                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          335                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst            163                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            145                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                342                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             34                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            114                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             21                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                335                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.dtb.walker            3                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst           163                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           145                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               342                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        53917                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        53917                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        62895                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        64271                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       127166                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        12027                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        12595                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        24622                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        80267                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        60030                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        140297                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1639                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1057                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        49655                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       124186                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       228039                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         3279                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         3223                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        53276                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       140645                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       285232                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       890231                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       448396                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       141685                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       590081                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1639                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1057                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        49655                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       204453                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       228039                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         3279                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         3223                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        53276                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       200675                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       285232                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1030528                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1639                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1057                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        49655                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       204453                       # number of overall MSHR misses
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::total     0.291088                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.232953                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.605095                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.527787                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.569408                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.169426                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.194107                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.237677                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.771406                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.527016                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.694119                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.236190                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.239379                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.258152                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.236190                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.239379                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.258152                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70692.837205                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70554.993605                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70623.169637                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73729.899310                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.148233                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73639.996588                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 130368.343130                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 130616.007063                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 130474.313079                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 133791.209065                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136444.058879                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157694.494940                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70333.476438                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69675.876000                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70175.579271                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132447.412789                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 134700.653121                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 153988.715131                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132447.412789                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 134700.653121                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 153988.715131                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.259851                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.309227                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.283430                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.232975                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.222303                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.227194                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.586532                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.521164                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.556650                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.291190                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.284424                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.098174                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.181894                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.339405                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.427712                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.090605                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.192512                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254444                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.770350                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.537073                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.695729                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.291190                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.284424                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.098174                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.244543                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.339405                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.427712                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.090605                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.234807                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.272872                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.291190                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.284424                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.098174                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.244543                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.476117                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.339405                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.427712                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.090605                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.234807                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.515876                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.272872                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70682.414155                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70539.976095                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70608.202168                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73684.614701                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.793255                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73615.805945                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 131561.389628                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 131793.771904                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 131660.845450                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 128053.317774                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 138064.715404                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127488.239500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136630.231188                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159033.895931                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70271.633390                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69591.955264                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70103.798129                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 128053.317774                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135649.713205                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127488.239500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135248.758735                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 155628.884125                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 128053.317774                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135649.713205                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127488.239500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135248.758735                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 155628.884125                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170383.753615                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136186.402184                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138777.173583                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165411.940842                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143086.795385                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155119.729441                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170027.531412                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136469.009894                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138985.217937                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167809.080387                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 139496.185978                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 145167.281609                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               59885                       # Transaction distribution
-system.membus.trans_dist::ReadResp             959045                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38450                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38450                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1308388                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           245549                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           443766                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         303375                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            149775                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           134703                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        899160                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        692677                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122588                       # Packet count per connected master and slave (bytes)
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81776.885043                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 71423.925661                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 84707.847746                       # average overall mshr uncacheable latency
+system.membus.trans_dist::ReadReq               59765                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1086669                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38295                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38295                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1418881                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           277094                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           441724                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         308123                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            153866                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           139435                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1026904                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        703178                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122504                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26142                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4883481                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5032287                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238261                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       238261                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5270548                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155695                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25676                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5303073                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5451329                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237588                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237588                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5688917                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155611                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52284                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    142819456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    143027991                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7275456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7275456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               150303447                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           603397                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4141095                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51352                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    158370176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    158577695                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7233920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               165811615                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           603403                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4427877                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4141095    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4427877    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4141095                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            97863497                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4427877                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            97877995                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            22133983                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21789496                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9091243819                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9855054431                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5543319054                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6236968511                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45567476                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45519188                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3910,58 +3858,58 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     12058125                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6550145                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1934123                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         145409                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       132628                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        12781                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              59887                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4587364                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38450                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38450                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      4172911                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2698369                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          743738                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        384448                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1128186                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          137                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           300120                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          300120                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4534724                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       956843                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       850115                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9259077                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8380798                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17639875                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    229804683                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    209683148                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              439487831                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3155812                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          8637402                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.346247                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.478873                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     12681630                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6883923                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      2005926                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         170885                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       155146                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        15739                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              59767                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4843433                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38295                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38295                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      4463947                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2878269                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          761897                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        392804                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1154700                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          117                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           312867                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          312867                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4790902                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       969633                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       862905                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9568329                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9002574                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18570903                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    239712817                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    228526446                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              468239263                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3311598                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          9100879                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.338787                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.476937                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5659510     65.52%     65.52% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                2965111     34.33%     99.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  12781      0.15%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                6033358     66.29%     66.29% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3051782     33.53%     99.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  15739      0.17%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8637402                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9396796139                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            9100879                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9916846796                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2598429                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2612852                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4205091357                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4354241663                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4119595686                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4394264623                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5119                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    4933                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13991                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   14218                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 0db15e453..ff7be42c7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.327140                       # Nu
 sim_ticks                                51327139864000                       # Number of ticks simulated
 final_tick                               51327139864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 139665                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164109                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8451911555                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 688288                       # Number of bytes of host memory used
-host_seconds                                  6072.84                       # Real time elapsed on the host
+host_inst_rate                                 139449                       # Simulator instruction rate (inst/s)
+host_op_rate                                   163855                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8438816943                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 688284                       # Number of bytes of host memory used
+host_seconds                                  6082.27                       # Real time elapsed on the host
 sim_insts                                   848164321                       # Number of instructions simulated
 sim_ops                                     996610207                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -579,7 +579,7 @@ system.cpu.itb.accesses                     357169890                       # DT
 system.cpu.numCycles                       1631144067                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          646909214                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles          646909150                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                     1002667158                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                   225024609                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches          133765720                       # Number of branches that fetch has predicted taken
@@ -593,21 +593,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles          873                       #
 system.cpu.fetch.CacheLines                 356634442                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes               6247312                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                   47880                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples         1571640484                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::mean              0.747058                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::stdev             1.149321                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1013991405     64.52%     64.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1013991341     64.52%     64.52% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::1                214266060     13.63%     78.15% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                 70309362      4.47%     82.62% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::3                273073721     17.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1571640484                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.137955                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        0.614702                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                526349627                       # Number of cycles decode is idle
+system.cpu.decode.IdleCycles                526349563                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles             552086440                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                 434104674                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles              49724049                       # Number of cycles decode is unblocking
@@ -617,27 +617,27 @@ system.cpu.decode.BranchMispred               3814526                       # Nu
 system.cpu.decode.DecodedInsts             1085977369                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts              29430616                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                9375758                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                571292055                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                571291991                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                65924513                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles      371563835                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                 438965882                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles             114518505                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1065686030                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts             1065686033                       # Number of instructions processed by rename
 system.cpu.rename.SquashedInsts               6908876                       # Number of squashed instructions processed by rename
 system.cpu.rename.ROBFullEvents               5086020                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                 334343                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                 634469                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               63514971                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents               63514970                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.FullRegisterEvents            20439                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1013378726                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1640198292                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1259502846                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands          1013378727                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1640198295                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1259502849                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups           1473679                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             947186300                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 66192423                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 66192424                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts           26900223                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts       23242764                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101754926                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                 101754923                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads            173828486                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores           150818351                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads           9879664                       # Number of conflicting loads.
@@ -649,11 +649,11 @@ system.cpu.iq.iqSquashedInstsIssued           3378731                       # Nu
 system.cpu.iq.iqSquashedInstsExamined        61252774                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined     34075299                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved         309098                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1571640548                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples    1571640484                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         0.665378                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::stdev        0.919633                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           924076981     58.80%     58.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           924076917     58.80%     58.80% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::1           334351644     21.27%     80.07% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::2           234725096     14.94%     95.01% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::3            72033056      4.58%     99.59% # Number of insts issued each cycle
@@ -665,7 +665,7 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1571640548                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1571640484                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                57663018     35.01%     35.01% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                 100158      0.06%     35.07% # attempts to use FU when none available
@@ -738,7 +738,7 @@ system.cpu.iq.FU_type_0::total             1045735608                       # Ty
 system.cpu.iq.rate                           0.641106                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                   164692672                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.157490                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3828710884                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads         3828710820                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes        1118319185                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses   1027391540                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads             2472282                       # Number of floating instruction queue reads
@@ -755,7 +755,7 @@ system.cpu.iew.lsq.thread0.squashedStores      6061186                       # N
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads      2527357                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1438792                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked       1438756                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                9375758                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                 6990377                       # Number of cycles IEW is blocking
@@ -789,11 +789,11 @@ system.cpu.iew.wb_fanout                     0.618086                       # av
 system.cpu.commit.commitSquashedInsts        51892888                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls        26891556                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           8548258                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples   1559580657                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::mean     0.639024                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     1.273898                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1047836838     67.19%     67.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1047836774     67.19%     67.19% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1    288037345     18.47%     85.66% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2    120098323      7.70%     93.36% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3     36644408      2.35%     95.71% # Number of insts commited each cycle
@@ -805,7 +805,7 @@ system.cpu.commit.committed_per_cycle::8     11706752      0.75%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1559580657                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            848164321                       # Number of instructions committed
 system.cpu.commit.committedOps              996610207                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -852,10 +852,10 @@ system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Cl
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         996610207                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              11706752                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2588836198                       # The number of ROB reads
+system.cpu.rob.rob_reads                   2588836134                       # The number of ROB reads
 system.cpu.rob.rob_writes                  2108972650                       # The number of ROB writes
-system.cpu.timesIdled                         8176252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59503519                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                         8176249                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59503583                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.quiesceCycles                 101023135782                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu.committedInsts                   848164321                       # Number of Instructions Simulated
 system.cpu.committedOps                     996610207                       # Number of Ops (including micro ops) Simulated
@@ -869,7 +869,7 @@ system.cpu.fp_regfile_reads                   1462624                       # nu
 system.cpu.fp_regfile_writes                   780384                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                 225040074                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                225673032                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2558050181                       # number of misc regfile reads
+system.cpu.misc_regfile_reads              2558050117                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               26930699                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           9706309                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.972800                       # Cycle average of tags in use
@@ -899,10 +899,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      3295516
 system.cpu.dcache.LoadLockedReq_hits::total      3295516                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      3691142                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      3691142                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     275426405                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        275426405                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    275804158                       # number of overall hits
-system.cpu.dcache.overall_hits::total       275804158                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     275749871                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        275749871                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    276127624                       # number of overall hits
+system.cpu.dcache.overall_hits::total       276127624                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      9582006                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       9582006                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data     11252664                       # number of WriteReq misses
@@ -915,10 +915,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data       446459
 system.cpu.dcache.LoadLockedReq_misses::total       446459                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20834670                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20834670                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22005420                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22005420                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data     22068660                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       22068660                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     23239410                       # number of overall misses
+system.cpu.dcache.overall_misses::total      23239410                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total 168553352000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827                       # number of WriteReq miss cycles
@@ -929,10 +929,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6881905000
 system.cpu.dcache.LoadLockedReq_miss_latency::total   6881905000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       299500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       299500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 612836911827                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 612836911827                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 612836911827                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 612836911827                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 665180471800                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 665180471800                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 665180471800                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 665180471800                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    156764287                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    156764287                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    139496788                       # number of WriteReq accesses(hits+misses)
@@ -945,10 +945,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3741975
 system.cpu.dcache.LoadLockedReq_accesses::total      3741975                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691149                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      3691149                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    296261075                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    296261075                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    297809578                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    297809578                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    297818531                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    297818531                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    299367034                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    299367034                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061124                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.061124                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080666                       # miss rate for WriteReq accesses
@@ -961,10 +961,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119311
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119311                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070325                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070325                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073891                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073891                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074101                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074101                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.077628                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.077628                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523                       # average WriteReq miss latency
@@ -975,18 +975,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29414.284547                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27849.362195                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30141.407399                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28622.950058                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     32180640                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs           1601871                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.089408                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      7511281                       # number of writebacks
 system.cpu.dcache.writebacks::total           7511281                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4454269                       # number of ReadReq MSHR hits
@@ -997,10 +995,10 @@ system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7130
 system.cpu.dcache.WriteLineReq_mshr_hits::total         7130                       # number of WriteLineReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218050                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total       218050                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13703391                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13703391                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13703391                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13703391                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13710521                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13710521                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13710521                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13710521                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5127737                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      5127737                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2003542                       # number of WriteReq MSHR misses
@@ -1013,10 +1011,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       228409
 system.cpu.dcache.LoadLockedReq_mshr_misses::total       228409                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7131279                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7131279                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8295216                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8295216                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8358139                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8358139                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9522076                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9522076                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
@@ -1035,16 +1033,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3210622500
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3210622500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       292500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       292500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 162503876437                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 186189032937                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 213174289910                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 236859446410                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192022000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192022000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228178464                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228178464                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420200464                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420200464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6192022000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6192022000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032710                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032710                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014363                       # mshr miss rate for WriteReq accesses
@@ -1057,10 +1053,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061040
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061040                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024071                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024071                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027854                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027854                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028065                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028065                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031807                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031807                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577                       # average WriteReq mshr miss latency
@@ -1073,17 +1069,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements          15141033                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.928986                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           340718799                       # Total number of references to valid blocks.
@@ -1142,8 +1135,6 @@ system.cpu.icache.blocked::no_mshrs              1460                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    16.247260                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks     15141033                       # number of writebacks
 system.cpu.icache.writebacks::total          15141033                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst       752570                       # number of ReadReq MSHR hits
@@ -1188,7 +1179,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1146896                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65342.232394                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           46291207                       # Total number of references to valid blocks.
@@ -1383,8 +1373,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       961909                       # number of writebacks
 system.cpu.l2cache.writebacks::total           961909                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
@@ -1460,11 +1448,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total  95507463453
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770895500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189659000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836145500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836145500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607041000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025804500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5770895500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8189659000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006451                       # mshr miss rate for ReadReq accesses
@@ -1520,12 +1506,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests     50432401                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     25583822                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3563                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1682,11 +1665,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8814                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8854                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115478                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115518                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8814                       # number of overall misses
-system.iocache.overall_misses::total             8854                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115478                       # number of overall misses
+system.iocache.overall_misses::total           115518                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1678338975                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1683410975                       # number of ReadReq miss cycles
@@ -1695,11 +1678,11 @@ system.iocache.WriteReq_miss_latency::total       351000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13416126023                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13416126023                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5423000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1678338975                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1683761975                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15094464998                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15099887998                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5423000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1678338975                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1683761975                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15094464998                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15099887998                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8814                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8851                       # number of ReadReq accesses(hits+misses)
@@ -1708,11 +1691,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8814                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8854                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115478                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115518                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8814                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8854                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115478                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115518                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1734,19 +1717,17 @@ system.iocache.WriteReq_avg_miss_latency::total       117000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130712.906337                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130714.589917                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130712.906337                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130714.589917                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         34291                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3518                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.747300                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -1757,11 +1738,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8814                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8854                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115478                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115518                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8814                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8854                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115478                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115518                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3222000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1237638975                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1240860975                       # number of ReadReq MSHR miss cycles
@@ -1770,11 +1751,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       201000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8077839572                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8077839572                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3423000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1237638975                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1241061975                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9315478547                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9318901547                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3423000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1237638975                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1241061975                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9315478547                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9318901547                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1796,12 +1777,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        67000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80670.558242                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80670.558242                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
 system.membus.trans_dist::ReadResp             410008                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
@@ -1847,7 +1827,7 @@ system.membus.reqLayer0.occupancy           103925500                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5584000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5571500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer5.occupancy          7165123486                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
index a24da51f0..dd0bedb40 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111167                       # Nu
 sim_ticks                                51111167216500                       # Number of ticks simulated
 final_tick                               51111167216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1780456                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2092420                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            92650032032                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 679092                       # Number of bytes of host memory used
-host_seconds                                   551.66                       # Real time elapsed on the host
+host_inst_rate                                1195823                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1405350                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            62227318824                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 678332                       # Number of bytes of host memory used
+host_seconds                                   821.36                       # Real time elapsed on the host
 sim_insts                                   982203438                       # Number of instructions simulated
 sim_ops                                    1154301153                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -300,10 +300,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      4303642
 system.cpu.dcache.LoadLockedReq_hits::total      4303642                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      4555646                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      4555646                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     330184303                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        330184303                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    330608768                       # number of overall hits
-system.cpu.dcache.overall_hits::total       330608768                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     330520588                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        330520588                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    330945053                       # number of overall hits
+system.cpu.dcache.overall_hits::total       330945053                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      6003373                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       6003373                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      2568142                       # number of WriteReq misses
@@ -316,10 +316,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data       253809
 system.cpu.dcache.LoadLockedReq_misses::total       253809                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      8571515                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        8571515                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     10157717                       # number of overall misses
-system.cpu.dcache.overall_misses::total      10157717                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data      9818285                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9818285                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     11404487                       # number of overall misses
+system.cpu.dcache.overall_misses::total      11404487                       # number of overall misses
 system.cpu.dcache.ReadReq_accesses::cpu.data    177114143                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    177114143                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    161641675                       # number of WriteReq accesses(hits+misses)
@@ -332,10 +332,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4557451
 system.cpu.dcache.LoadLockedReq_accesses::total      4557451                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      4555647                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      4555647                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    338755818                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    338755818                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    340766485                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    340766485                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    340338873                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    340338873                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    342349540                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    342349540                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033896                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.033896                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015888                       # miss rate for WriteReq accesses
@@ -348,21 +348,18 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055691
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055691                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025303                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025303                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.029808                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.029808                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.028849                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.028849                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.033312                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.033312                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      8917390                       # number of writebacks
 system.cpu.dcache.writebacks::total           8917390                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements          14265253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           968529210                       # Total number of references to valid blocks.
@@ -409,11 +406,8 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks     14265253                       # number of writebacks
 system.cpu.icache.writebacks::total          14265253                       # number of writebacks
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1725806                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65319.576270                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           46897183                       # Total number of references to valid blocks.
@@ -555,11 +549,8 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1507080                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1507080                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     52385887                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     26512957                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1744                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -670,11 +661,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115477                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115517                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115477                       # number of overall misses
+system.iocache.overall_misses::total           115517                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
@@ -683,11 +674,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115477                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115517                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115477                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115517                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -707,11 +698,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
 system.membus.trans_dist::ReadResp             524946                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index d41a2f111..72aef18b4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.256536                       # Nu
 sim_ticks                                47256535705500                       # Number of ticks simulated
 final_tick                               47256535705500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1671940                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1966949                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            80984002716                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 693668                       # Number of bytes of host memory used
-host_seconds                                   583.53                       # Real time elapsed on the host
+host_inst_rate                                1118024                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1315296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            54153885278                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 690972                       # Number of bytes of host memory used
+host_seconds                                   872.63                       # Real time elapsed on the host
 sim_insts                                   975625723                       # Number of instructions simulated
 sim_ops                                    1147772483                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -331,10 +331,10 @@ system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2079285
 system.cpu0.dcache.LoadLockedReq_hits::total      2079285                       # number of LoadLockedReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2039805                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      2039805                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    165871488                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       165871488                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    166085900                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      166085900                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data    166131177                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       166131177                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    166345589                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      166345589                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      3292661                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      3292661                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data      1484857                       # number of WriteReq misses
@@ -347,10 +347,10 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       118361
 system.cpu0.dcache.LoadLockedReq_misses::total       118361                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data       156654                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total       156654                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4777518                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4777518                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5552076                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5552076                       # number of overall misses
+system.cpu0.dcache.demand_misses::cpu0.data      5600711                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5600711                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6375269                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6375269                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     88854005                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     88854005                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data     81795001                       # number of WriteReq accesses(hits+misses)
@@ -363,10 +363,10 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2197646
 system.cpu0.dcache.LoadLockedReq_accesses::total      2197646                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2196459                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total      2196459                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    170649006                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    170649006                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    171637976                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    171637976                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data    171731888                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    171731888                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    172720858                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    172720858                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037057                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.037057                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018153                       # miss rate for WriteReq accesses
@@ -379,21 +379,18 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053858
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053858                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.071321                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.071321                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027996                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027996                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032348                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032348                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.032613                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.032613                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036911                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.036911                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      6248192                       # number of writebacks
 system.cpu0.dcache.writebacks::total          6248192                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements          5479450                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.989014                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          489031557                       # Total number of references to valid blocks.
@@ -440,11 +437,8 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      5479450                       # number of writebacks
 system.cpu0.icache.writebacks::total          5479450                       # number of writebacks
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
 system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
@@ -590,11 +584,8 @@ system.cpu0.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu0.l2cache.writebacks::writebacks      1558575                       # number of writebacks
 system.cpu0.l2cache.writebacks::total         1558575                       # number of writebacks
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
 system.cpu0.toL2Bus.snoop_filter.tot_requests     24117057                       # Total number of requests made to the snoop filter.
 system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12284855                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1399                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -863,10 +854,10 @@ system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2062470
 system.cpu1.dcache.LoadLockedReq_hits::total      2062470                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2047982                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total      2047982                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    162001697                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       162001697                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    162189982                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      162189982                       # number of overall hits
+system.cpu1.dcache.demand_hits::cpu1.data    162066607                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       162066607                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    162254892                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      162254892                       # number of overall hits
 system.cpu1.dcache.ReadReq_misses::cpu1.data      3369907                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total      3369907                       # number of ReadReq misses
 system.cpu1.dcache.WriteReq_misses::cpu1.data      1463877                       # number of WriteReq misses
@@ -879,10 +870,10 @@ system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       145888
 system.cpu1.dcache.LoadLockedReq_misses::total       145888                       # number of LoadLockedReq misses
 system.cpu1.dcache.StoreCondReq_misses::cpu1.data       158992                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total       158992                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4833784                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4833784                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5624082                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5624082                       # number of overall misses
+system.cpu1.dcache.demand_misses::cpu1.data      5269627                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5269627                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6059925                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6059925                       # number of overall misses
 system.cpu1.dcache.ReadReq_accesses::cpu1.data     87745578                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     87745578                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data     79089903                       # number of WriteReq accesses(hits+misses)
@@ -895,10 +886,10 @@ system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2208358
 system.cpu1.dcache.LoadLockedReq_accesses::total      2208358                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2206974                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total      2206974                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    166835481                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    166835481                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    167814064                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    167814064                       # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data    167336234                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    167336234                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    168314817                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    168314817                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038405                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.038405                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018509                       # miss rate for WriteReq accesses
@@ -911,21 +902,18 @@ system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066062
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066062                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.072041                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::total     0.072041                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028973                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.028973                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033514                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.033514                       # miss rate for overall accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031491                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.031491                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.036004                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.036004                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks      5963482                       # number of writebacks
 system.cpu1.dcache.writebacks::total          5963482                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements          4804881                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          496.439171                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs          476906226                       # Total number of references to valid blocks.
@@ -972,11 +960,8 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks      4804881                       # number of writebacks
 system.cpu1.icache.writebacks::total          4804881                       # number of writebacks
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
@@ -1123,11 +1108,8 @@ system.cpu1.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu1.l2cache.writebacks::writebacks      1199052                       # number of writebacks
 system.cpu1.l2cache.writebacks::total         1199052                       # number of writebacks
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
 system.cpu1.toL2Bus.snoop_filter.tot_requests     22219600                       # Total number of requests made to the snoop filter.
 system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11357015                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          386                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1237,11 +1219,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8887                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8927                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115615                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115655                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8887                       # number of overall misses
-system.iocache.overall_misses::total             8927                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115615                       # number of overall misses
+system.iocache.overall_misses::total           115655                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8887                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8924                       # number of ReadReq accesses(hits+misses)
@@ -1250,11 +1232,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8887                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8927                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115615                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115655                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8887                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8927                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115615                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115655                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1274,11 +1256,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106694                       # number of writebacks
 system.iocache.writebacks::total               106694                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                  1766126                       # number of replacements
 system.l2c.tags.tagsinuse                63106.596515                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4618110                       # Total number of references to valid blocks.
@@ -1483,11 +1462,8 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks             1473799                       # number of writebacks
 system.l2c.writebacks::total                  1473799                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               82185                       # Transaction distribution
 system.membus.trans_dist::ReadResp             568654                       # Transaction distribution
 system.membus.trans_dist::WriteReq              38847                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index 734b4a589..a0709a582 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111167                       # Nu
 sim_ticks                                51111167216500                       # Number of ticks simulated
 final_tick                               51111167216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1770185                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2080350                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            92115569363                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 676500                       # Number of bytes of host memory used
-host_seconds                                   554.86                       # Real time elapsed on the host
+host_inst_rate                                1114977                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1310339                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            58020354238                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 675736                       # Number of bytes of host memory used
+host_seconds                                   880.92                       # Real time elapsed on the host
 sim_insts                                   982203438                       # Number of instructions simulated
 sim_ops                                    1154301153                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -300,10 +300,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      4303642
 system.cpu.dcache.LoadLockedReq_hits::total      4303642                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      4555646                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      4555646                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     330184303                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        330184303                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    330608768                       # number of overall hits
-system.cpu.dcache.overall_hits::total       330608768                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     330520588                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        330520588                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    330945053                       # number of overall hits
+system.cpu.dcache.overall_hits::total       330945053                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      6003373                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       6003373                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      2568142                       # number of WriteReq misses
@@ -316,10 +316,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data       253809
 system.cpu.dcache.LoadLockedReq_misses::total       253809                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      8571515                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        8571515                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     10157717                       # number of overall misses
-system.cpu.dcache.overall_misses::total      10157717                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data      9818285                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9818285                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     11404487                       # number of overall misses
+system.cpu.dcache.overall_misses::total      11404487                       # number of overall misses
 system.cpu.dcache.ReadReq_accesses::cpu.data    177114143                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    177114143                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    161641675                       # number of WriteReq accesses(hits+misses)
@@ -332,10 +332,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4557451
 system.cpu.dcache.LoadLockedReq_accesses::total      4557451                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      4555647                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      4555647                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    338755818                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    338755818                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    340766485                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    340766485                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    340338873                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    340338873                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    342349540                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    342349540                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033896                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.033896                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015888                       # miss rate for WriteReq accesses
@@ -348,21 +348,18 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055691
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055691                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025303                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025303                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.029808                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.029808                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.028849                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.028849                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.033312                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.033312                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      8917390                       # number of writebacks
 system.cpu.dcache.writebacks::total           8917390                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements          14265253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           968529210                       # Total number of references to valid blocks.
@@ -409,11 +406,8 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks     14265253                       # number of writebacks
 system.cpu.icache.writebacks::total          14265253                       # number of writebacks
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1725806                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65319.576270                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           46897183                       # Total number of references to valid blocks.
@@ -555,11 +549,8 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1507080                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1507080                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     52385887                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     26512957                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1744                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -670,11 +661,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115477                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115517                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115477                       # number of overall misses
+system.iocache.overall_misses::total           115517                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
@@ -683,11 +674,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115477                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115517                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115477                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115517                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -707,11 +698,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
 system.membus.trans_dist::ReadResp             524946                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 665a239cf..3b055f28d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.460623                       # Nu
 sim_ticks                                47460623015500                       # Number of ticks simulated
 final_tick                               47460623015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 731783                       # Simulator instruction rate (inst/s)
-host_op_rate                                   860761                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            39683148028                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 744736                       # Number of bytes of host memory used
-host_seconds                                  1195.99                       # Real time elapsed on the host
+host_inst_rate                                 734945                       # Simulator instruction rate (inst/s)
+host_op_rate                                   864481                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            39854660745                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 745756                       # Number of bytes of host memory used
+host_seconds                                  1190.84                       # Real time elapsed on the host
 sim_insts                                   875204273                       # Number of instructions simulated
 sim_ops                                    1029460892                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -646,10 +646,10 @@ system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1847375
 system.cpu0.dcache.LoadLockedReq_hits::total      1847375                       # number of LoadLockedReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1814831                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      1814831                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    152875582                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       152875582                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    153075138                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      153075138                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data    153056972                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       153056972                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    153256528                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      153256528                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      2983943                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      2983943                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data      1350734                       # number of WriteReq misses
@@ -662,10 +662,10 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       159632
 system.cpu0.dcache.LoadLockedReq_misses::total       159632                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data       191006                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total       191006                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4334677                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4334677                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4954267                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4954267                       # number of overall misses
+system.cpu0.dcache.demand_misses::cpu0.data      5084807                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5084807                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5704397                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5704397                       # number of overall misses
 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  47916762500                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::total  47916762500                       # number of ReadReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  34952130000                       # number of WriteReq miss cycles
@@ -678,10 +678,10 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5329904000
 system.cpu0.dcache.StoreCondReq_miss_latency::total   5329904000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5776000                       # number of StoreCondFailReq miss cycles
 system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5776000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  82868892500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  82868892500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  82868892500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  82868892500                       # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 128993802000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 128993802000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 128993802000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 128993802000                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     82707420                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     82707420                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data     74502839                       # number of WriteReq accesses(hits+misses)
@@ -694,10 +694,10 @@ system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2007007
 system.cpu0.dcache.LoadLockedReq_accesses::total      2007007                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2005837                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total      2005837                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    157210259                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    157210259                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    158029405                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    158029405                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data    158141779                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    158141779                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    158960925                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    158960925                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036078                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.036078                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018130                       # miss rate for WriteReq accesses
@@ -710,10 +710,10 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.079537
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079537                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095225                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095225                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027572                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027572                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031350                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.031350                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.032153                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.032153                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.035886                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.035886                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022                       # average ReadReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573                       # average WriteReq miss latency
@@ -726,18 +726,16 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25368.475539                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25368.475539                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.047795                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 22613.047795                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      5459134                       # number of writebacks
 system.cpu0.dcache.writebacks::total          5459134                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        24235                       # number of ReadReq MSHR hits
@@ -762,10 +760,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       116332
 system.cpu0.dcache.LoadLockedReq_mshr_misses::total       116332                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       191006                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total       191006                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4289040                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4289040                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4907486                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4907486                       # number of overall MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5039170                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5039170                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5657616                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5657616                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29450                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29450                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28924                       # number of WriteReq MSHR uncacheable
@@ -786,16 +784,14 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5138961000
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5138961000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5713000                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5713000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  76374032500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  76374032500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  91252922000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  91252922000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 121748812000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 121748812000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136627701500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 136627701500                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5439516500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5439516500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5307758000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5307758000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10747274500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10747274500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5439516500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5439516500                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035785                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035785                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017843                       # mshr miss rate for WriteReq accesses
@@ -808,10 +804,10 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057963
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.057963                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095225                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095225                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027282                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027282                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031054                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031054                       # mshr miss rate for overall accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.031865                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.031865                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.035591                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.035591                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198                       # average ReadReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792                       # average WriteReq mshr miss latency
@@ -826,17 +822,14 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24160.489128                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24160.489128                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24149.341613                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24149.341613                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93183.891801                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93183.891801                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements          5000286                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.853700                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          450204172                       # Total number of references to valid blocks.
@@ -895,8 +888,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      5000286                       # number of writebacks
 system.cpu0.icache.writebacks::total          5000286                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5000799                       # number of ReadReq MSHR misses
@@ -935,7 +926,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued      7383328                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified      7383330                       # number of prefetch candidates identified
 system.cpu0.l2cache.prefetcher.pfBufferHit            1                       # number of redundant prefetches already in prefetch queue
@@ -1149,8 +1139,6 @@ system.cpu0.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu0.l2cache.unused_prefetches           39383                       # number of HardPF blocks evicted w/o reference
 system.cpu0.l2cache.writebacks::writebacks      1473434                       # number of writebacks
 system.cpu0.l2cache.writebacks::total         1473434                       # number of writebacks
@@ -1233,11 +1221,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total  98500032601
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5203415000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10834186500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5090437000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5090437000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10293852000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15924623500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5203415000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10834186500                       # number of overall MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.039628                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.050848                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.043899                       # mshr miss rate for ReadReq accesses
@@ -1301,12 +1287,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89139.257204                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106741.805338                       # average overall mshr uncacheable latency
 system.cpu0.toL2Bus.snoop_filter.tot_requests     21678176                       # Total number of requests made to the snoop filter.
 system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11128402                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          962                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1634,10 +1617,10 @@ system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1631683
 system.cpu1.dcache.LoadLockedReq_hits::total      1631683                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1602426                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total      1602426                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    142590680                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       142590680                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    142761779                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      142761779                       # number of overall hits
+system.cpu1.dcache.demand_hits::cpu1.data    142736138                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       142736138                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    142907237                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      142907237                       # number of overall hits
 system.cpu1.dcache.ReadReq_misses::cpu1.data      2875045                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total      2875045                       # number of ReadReq misses
 system.cpu1.dcache.WriteReq_misses::cpu1.data      1313230                       # number of WriteReq misses
@@ -1650,10 +1633,10 @@ system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       165519
 system.cpu1.dcache.LoadLockedReq_misses::total       165519                       # number of LoadLockedReq misses
 system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193387                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total       193387                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4188275                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4188275                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      4814576                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      4814576                       # number of overall misses
+system.cpu1.dcache.demand_misses::cpu1.data      4671770                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4671770                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5298071                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5298071                       # number of overall misses
 system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  45279528500                       # number of ReadReq miss cycles
 system.cpu1.dcache.ReadReq_miss_latency::total  45279528500                       # number of ReadReq miss cycles
 system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  30099423000                       # number of WriteReq miss cycles
@@ -1666,10 +1649,10 @@ system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5550193500
 system.cpu1.dcache.StoreCondReq_miss_latency::total   5550193500                       # number of StoreCondReq miss cycles
 system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      6333000                       # number of StoreCondFailReq miss cycles
 system.cpu1.dcache.StoreCondFailReq_miss_latency::total      6333000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  75378951500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  75378951500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  75378951500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  75378951500                       # number of overall miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  93474799500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  93474799500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  93474799500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  93474799500                       # number of overall miss cycles
 system.cpu1.dcache.ReadReq_accesses::cpu1.data     76904053                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     76904053                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data     69874902                       # number of WriteReq accesses(hits+misses)
@@ -1682,10 +1665,10 @@ system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1797202
 system.cpu1.dcache.LoadLockedReq_accesses::total      1797202                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1795813                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total      1795813                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    146778955                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    146778955                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    147576355                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    147576355                       # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data    147407908                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    147407908                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    148205308                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    148205308                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037385                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.037385                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018794                       # miss rate for WriteReq accesses
@@ -1698,10 +1681,10 @@ system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092098
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092098                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.107688                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::total     0.107688                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028535                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.028535                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032624                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.032624                       # miss rate for overall accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031693                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.031693                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035748                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.035748                       # miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709                       # average ReadReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748                       # average WriteReq miss latency
@@ -1714,18 +1697,16 @@ system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20008.433527                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20008.433527                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17643.176073                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17643.176073                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks      5111729                       # number of writebacks
 system.cpu1.dcache.writebacks::total          5111729                       # number of writebacks
 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16692                       # number of ReadReq MSHR hits
@@ -1750,10 +1731,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       120540
 system.cpu1.dcache.LoadLockedReq_mshr_misses::total       120540                       # number of LoadLockedReq MSHR misses
 system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193387                       # number of StoreCondReq MSHR misses
 system.cpu1.dcache.StoreCondReq_mshr_misses::total       193387                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4171181                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4171181                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4797482                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4797482                       # number of overall MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4654676                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4654676                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5280977                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5280977                       # number of overall MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         8711                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.ReadReq_mshr_uncacheable::total         8711                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         9093                       # number of WriteReq MSHR uncacheable
@@ -1774,16 +1755,14 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5356877500
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5356877500                       # number of StoreCondReq MSHR miss cycles
 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      6262000                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      6262000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  69734968500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  69734968500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  84014947000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  84014947000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  87347321500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  87347321500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101627300000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 101627300000                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1460511000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1460511000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1571513500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1571513500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3032024500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3032024500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1460511000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1460511000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037168                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037168                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018788                       # mshr miss rate for WriteReq accesses
@@ -1796,10 +1775,10 @@ system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067071
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067071                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.107688                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.107688                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028418                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028418                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032508                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032508                       # mshr miss rate for overall accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031577                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031577                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035633                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035633                       # mshr miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986                       # average ReadReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940                       # average WriteReq mshr miss latency
@@ -1814,17 +1793,14 @@ system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18765.499790                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18765.499790                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19244.033822                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19244.033822                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82032.745450                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82032.745450                       # average overall mshr uncacheable latency
 system.cpu1.icache.tags.replacements          4920276                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          496.059748                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs          415625824                       # Total number of references to valid blocks.
@@ -1882,8 +1858,6 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks      4920276                       # number of writebacks
 system.cpu1.icache.writebacks::total          4920276                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4920793                       # number of ReadReq MSHR misses
@@ -1922,7 +1896,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364                       # average overall mshr uncacheable latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued      7108517                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified      7108606                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit           78                       # number of redundant prefetches already in prefetch queue
@@ -2132,8 +2105,6 @@ system.cpu1.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu1.l2cache.unused_prefetches           39620                       # number of HardPF blocks evicted w/o reference
 system.cpu1.l2cache.writebacks::writebacks      1103180                       # number of writebacks
 system.cpu1.l2cache.writebacks::total         1103180                       # number of writebacks
@@ -2218,11 +2189,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total  95457897080
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13938500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1390451500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1404390000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1502902000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1502902000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13938500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2893353500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2907292000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1390451500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1404390000                       # number of overall MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.036189                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048991                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.041059                       # mshr miss rate for ReadReq accesses
@@ -2286,12 +2255,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78097.702763                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78396.226415                       # average overall mshr uncacheable latency
 system.cpu1.toL2Bus.snoop_filter.tot_requests     20782124                       # Total number of requests made to the snoop filter.
 system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10655468                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          892                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -2451,11 +2417,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8879                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8919                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115607                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115647                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8879                       # number of overall misses
-system.iocache.overall_misses::total             8919                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115607                       # number of overall misses
+system.iocache.overall_misses::total           115647                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5198000                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1680349949                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1685547949                       # number of ReadReq miss cycles
@@ -2464,11 +2430,11 @@ system.iocache.WriteReq_miss_latency::total       369000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13547011908                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13547011908                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5567000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1680349949                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1685916949                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15227361857                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15232928857                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5567000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1680349949                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1685916949                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15227361857                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15232928857                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8879                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8916                       # number of ReadReq accesses(hits+misses)
@@ -2477,11 +2443,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8879                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8919                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115607                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115647                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8879                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8919                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115607                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115647                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2503,19 +2469,17 @@ system.iocache.WriteReq_avg_miss_latency::total       123000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 189249.909787                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 189025.333445                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 131716.607619                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 131719.187329                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 189249.909787                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 189025.333445                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 131716.607619                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 131719.187329                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         33462                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3547                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.433888                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106693                       # number of writebacks
 system.iocache.writebacks::total               106693                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -2526,11 +2490,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8879                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8919                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115607                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115647                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8879                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8919                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115607                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115647                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1236399949                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1239747949                       # number of ReadReq MSHR miss cycles
@@ -2539,11 +2503,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       219000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8204144644                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8204144644                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3567000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1236399949                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1239966949                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9440544593                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9444111593                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3567000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1236399949                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1239966949                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9440544593                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9444111593                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2565,12 +2529,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        73000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 139025.333445                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 81660.665816                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 81663.264875                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 139025.333445                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 81660.665816                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 81663.264875                       # average overall mshr miss latency
 system.l2c.tags.replacements                  1288575                       # number of replacements
 system.l2c.tags.tagsinuse                63334.482670                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    5304464                       # Total number of references to valid blocks.
@@ -2897,8 +2860,6 @@ system.l2c.blocked::no_mshrs                       25                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs            52                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks             1038944                       # number of writebacks
 system.l2c.writebacks::total                  1038944                       # number of writebacks
 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           98                       # number of ReadSharedReq MSHR hits
@@ -3026,14 +2987,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4673220523
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11957000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1233601518                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total  10773300041                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4598373544                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1348007106                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5946380650                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9271594067                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4673220523                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11957000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2581608624                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  16719680691                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1233601518                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10773300041                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.275559                       # mshr miss rate for UpgradeReq accesses
@@ -3131,15 +3089,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst       108700                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80056.540977                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst       108700                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69295.670037                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 90220.331804                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               81394                       # Transaction distribution
 system.membus.trans_dist::ReadResp             801457                       # Transaction distribution
 system.membus.trans_dist::WriteReq              38017                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index 3c1e4fda0..9849a9aeb 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.759374                       # Nu
 sim_ticks                                51759374264500                       # Number of ticks simulated
 final_tick                               51759374264500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1125548                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1322684                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            69608471837                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 675480                       # Number of bytes of host memory used
-host_seconds                                   743.58                       # Real time elapsed on the host
+host_inst_rate                                 729832                       # Simulator instruction rate (inst/s)
+host_op_rate                                   857659                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            45135767006                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 675484                       # Number of bytes of host memory used
+host_seconds                                  1146.75                       # Real time elapsed on the host
 sim_insts                                   836933434                       # Number of instructions simulated
 sim_ops                                     983519389                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -613,10 +613,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      3338150
 system.cpu.dcache.LoadLockedReq_hits::total      3338150                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      3623891                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      3623891                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     283201595                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        283201595                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    283575709                       # number of overall hits
-system.cpu.dcache.overall_hits::total       283575709                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     283534216                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        283534216                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    283908330                       # number of overall hits
+system.cpu.dcache.overall_hits::total       283908330                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      4894991                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       4894991                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      1998130                       # number of WriteReq misses
@@ -629,10 +629,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data       287378
 system.cpu.dcache.LoadLockedReq_misses::total       287378                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      6893121                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        6893121                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      8029572                       # number of overall misses
-system.cpu.dcache.overall_misses::total       8029572                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data      8114631                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        8114631                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9251082                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9251082                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data  84471929500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total  84471929500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data  70206054500                       # number of WriteReq miss cycles
@@ -643,10 +643,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4418678000
 system.cpu.dcache.LoadLockedReq_miss_latency::total   4418678000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 154677984000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 154677984000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 154677984000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 154677984000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 202906742000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 202906742000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 202906742000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 202906742000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    152330440                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    152330440                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    137764276                       # number of WriteReq accesses(hits+misses)
@@ -659,10 +659,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3625528
 system.cpu.dcache.LoadLockedReq_accesses::total      3625528                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      3623892                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      3623892                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    290094716                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    290094716                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    291605281                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    291605281                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    291648847                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    291648847                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    293159412                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    293159412                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032134                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.032134                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014504                       # miss rate for WriteReq accesses
@@ -675,10 +675,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079265
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079265                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023762                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023762                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.027536                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.027536                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.027823                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.027823                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.031556                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.031556                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297                       # average WriteReq miss latency
@@ -689,18 +689,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22439.470307                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19263.540323                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25005.048535                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21933.298397                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      7313678                       # number of writebacks
 system.cpu.dcache.writebacks::total           7313678                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21981                       # number of ReadReq MSHR hits
@@ -725,10 +723,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       218778
 system.cpu.dcache.LoadLockedReq_mshr_misses::total       218778                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      6849886                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      6849886                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      7984572                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      7984572                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8071396                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8071396                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9206082                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9206082                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
@@ -747,16 +745,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3007041000
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3007041000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 145533577500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 166975219500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 192540825500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 213982467500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6199681500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6199681500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6217603000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6217603000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12417284500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12417284500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6199681500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6199681500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031990                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031990                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014350                       # mshr miss rate for WriteReq accesses
@@ -769,10 +765,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060344
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060344                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023613                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.023613                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027381                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027381                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027675                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.027675                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031403                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031403                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701                       # average WriteReq mshr miss latency
@@ -785,17 +781,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements          13331164                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.820795                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           824117568                       # Total number of references to valid blocks.
@@ -855,8 +848,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks     13331164                       # number of writebacks
 system.cpu.icache.writebacks::total          13331164                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13331681                       # number of ReadReq MSHR misses
@@ -895,7 +886,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1036266                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65255.052774                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           41658706                       # Total number of references to valid blocks.
@@ -1087,8 +1077,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       879823                       # number of writebacks
 system.cpu.l2cache.writebacks::total           879823                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2426                       # number of ReadReq MSHR misses
@@ -1152,11 +1140,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total  78834601014
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5777601500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10675326000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5829950000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5829950000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607551500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  16505276000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5777601500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10675326000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007675                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010168                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008763                       # mshr miss rate for ReadReq accesses
@@ -1210,12 +1196,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests     45953712                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     23239521                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1757                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1372,11 +1355,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8860                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8900                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115524                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115564                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8860                       # number of overall misses
-system.iocache.overall_misses::total             8900                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115524                       # number of overall misses
+system.iocache.overall_misses::total           115564                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1628892126                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1633962126                       # number of ReadReq miss cycles
@@ -1385,11 +1368,11 @@ system.iocache.WriteReq_miss_latency::total       351000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13410994738                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13410994738                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1628892126                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1634313126                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15039886864                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15045307864                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1628892126                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1634313126                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15039886864                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15045307864                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8860                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8897                       # number of ReadReq accesses(hits+misses)
@@ -1398,11 +1381,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8860                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8900                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115524                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115564                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8860                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8900                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115524                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115564                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1424,19 +1407,17 @@ system.iocache.WriteReq_avg_miss_latency::total       117000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183847.869752                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183630.688315                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130188.418545                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130190.265688                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183847.869752                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183630.688315                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130188.418545                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130190.265688                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         32190                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3353                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.600358                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -1447,11 +1428,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8860                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8900                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115524                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115564                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8860                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8900                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115524                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115564                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1185892126                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1189112126                       # number of ReadReq MSHR miss cycles
@@ -1460,11 +1441,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       201000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8072604881                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8072604881                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1185892126                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1189313126                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9258497007                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9261918007                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1185892126                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1189313126                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9258497007                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9261918007                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1486,12 +1467,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        67000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133630.688315                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80145.356746                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133630.688315                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80145.356746                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               76827                       # Transaction distribution
 system.membus.trans_dist::ReadResp             389416                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index 16266538d..a460c7e41 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111167                       # Nu
 sim_ticks                                51111167216500                       # Number of ticks simulated
 final_tick                               51111167216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1764627                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2073818                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            91826344419                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 678044                       # Number of bytes of host memory used
-host_seconds                                   556.61                       # Real time elapsed on the host
+host_inst_rate                                1129745                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1327694                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            58788800163                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 676512                       # Number of bytes of host memory used
+host_seconds                                   869.40                       # Real time elapsed on the host
 sim_insts                                   982203438                       # Number of instructions simulated
 sim_ops                                    1154301153                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -326,12 +326,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total      4303548
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2275074                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2280572                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      4555646                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    165146293                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    165037797                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       330184090                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    165355623                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    165252780                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      330608403                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data    165290534                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    165229841                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       330520375                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    165499864                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    165444824                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      330944688                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      3016518                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::cpu1.data      2987065                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      6003583                       # number of ReadReq misses
@@ -349,12 +349,12 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       127060
 system.cpu0.dcache.LoadLockedReq_misses::total       253903                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4311974                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      4259754                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       8571728                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5100211                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      5057415                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     10157626                       # number of overall misses
+system.cpu0.dcache.demand_misses::cpu0.data      5073464                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      4745034                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       9818498                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5861701                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      5542695                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     11404396                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     88617297                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu1.data     88496846                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total    177114143                       # number of ReadReq accesses(hits+misses)
@@ -373,12 +373,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total      4557451
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2275074                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2280573                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total      4555647                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    169458267                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    169297551                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    338755818                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    170455834                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    170310195                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    340766029                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data    170363998                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    169974875                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    340338873                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    171361565                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    170987519                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    342349084                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034040                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033753                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.033897                       # miss rate for ReadReq accesses
@@ -396,23 +396,20 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055692
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055712                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025446                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025161                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.025304                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029921                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029695                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029808                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029780                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.027916                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028849                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034207                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032416                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.033312                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      8917390                       # number of writebacks
 system.cpu0.dcache.writebacks::total          8917390                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements         14265253                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          968529210                       # Total number of references to valid blocks.
@@ -473,11 +470,8 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks     14265253                       # number of writebacks
 system.cpu0.icache.writebacks::total         14265253                       # number of writebacks
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -742,11 +736,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115477                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115517                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115477                       # number of overall misses
+system.iocache.overall_misses::total           115517                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
@@ -755,11 +749,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115477                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115517                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115477                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115517                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -779,11 +773,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                  1725796                       # number of replacements
 system.l2c.tags.tagsinuse                65319.576265                       # Cycle average of tags in use
 system.l2c.tags.total_refs                   46978291                       # Total number of references to valid blocks.
@@ -993,11 +984,8 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks             1507081                       # number of writebacks
 system.l2c.writebacks::total                  1507081                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
 system.membus.trans_dist::ReadResp             524934                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index eb3e33d10..1b1aa2e1b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.278333                       # Nu
 sim_ticks                                51278333141000                       # Number of ticks simulated
 final_tick                               51278333141000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 303802                       # Simulator instruction rate (inst/s)
-host_op_rate                                   357005                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18317890976                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 300545                       # Simulator instruction rate (inst/s)
+host_op_rate                                   353177                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18121485754                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 688280                       # Number of bytes of host memory used
-host_seconds                                  2799.36                       # Real time elapsed on the host
+host_seconds                                  2829.70                       # Real time elapsed on the host
 sim_insts                                   850450745                       # Number of instructions simulated
 sim_ops                                     999383448                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -224,10 +224,10 @@ system.physmem.wrQLenPdf::22                    25980                       # Wh
 system.physmem.wrQLenPdf::23                    26739                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                    26656                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                    27115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    28437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    28436                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                    27753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    28093                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    29855                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    28091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    29858                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                    26497                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                    26161                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::32                    25503                       # What write queue length does an incoming req see
@@ -262,20 +262,20 @@ system.physmem.wrQLenPdf::60                       91                       # Wh
 system.physmem.wrQLenPdf::61                       98                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       52                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                       60                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       267353                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      211.870778                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.094335                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     252.016088                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       267354                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      211.869985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.094359                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     252.014491                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::0-127         129551     48.46%     48.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        69660     26.06%     74.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        69661     26.06%     74.51% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383        23971      8.97%     83.48% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511        11874      4.44%     87.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         7888      2.95%     90.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4787      1.79%     92.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         7889      2.95%     90.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4786      1.79%     92.66% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::768-895         3806      1.42%     94.08% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023         2811      1.05%     95.14% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151        13005      4.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         267353                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         267354                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples         24743                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        17.307279                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::stdev       12.628838                       # Reads before turning the bus around for writes
@@ -339,12 +339,12 @@ system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Wr
 system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total           24743                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8299174160                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16328955410                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     8299247161                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16329028411                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2141275000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19379.05                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       19379.22                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38129.05                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  38129.22                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.53                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.57                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        0.53                       # Average system read bandwidth in MiByte/s
@@ -356,7 +356,7 @@ system.physmem.busUtilWrite                      0.00                       # Da
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         5.79                       # Average write queue length when enqueuing
 system.physmem.readRowHits                     313353                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    304366                       # Number of row buffer hits during writes
+system.physmem.writeRowHits                    304365                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   73.17                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  66.62                       # Row buffer hit rate for writes
 system.physmem.avgGap                     57915294.39                       # Average gap between requests
@@ -375,14 +375,14 @@ system.physmem_0.memoryStateTime::REF    1692411240000                       # T
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT    123966214393                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  988023960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  537516375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  988031520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  537520500                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                1638335400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy               1459121040                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           3310356385440                       # Energy for refresh commands per rank (pJ)
 system.physmem_1.actBackEnergy           1177251222825                       # Energy for active background per rank (pJ)
 system.physmem_1.preBackEnergy           29686423716000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34178654321040                       # Total energy per rank (pJ)
+system.physmem_1.totalEnergy             34178654332725                       # Total energy per rank (pJ)
 system.physmem_1.averagePower              667.571395                       # Core power per rank (mW)
 system.physmem_1.memoryStateTime::IDLE   48870902891583                       # Time in different power states
 system.physmem_1.memoryStateTime::REF    1692411240000                       # Time in different power states
@@ -672,16 +672,16 @@ system.cpu0.dcache.StoreCondReq_hits::cpu1.data       472149
 system.cpu0.dcache.StoreCondReq_hits::cpu2.data       627026                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1076109                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      3720139                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    116923310                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     36437095                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     49298761                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     83402769                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       286061935                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    117082223                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     36484268                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     49373898                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     83517377                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      286457766                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data    117052465                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     36481990                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data     49356444                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data     83500509                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       286391408                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    117211378                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     36529163                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data     49431581                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data     83615117                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      286787239                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      2029256                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::cpu1.data       653198                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::cpu2.data       985570                       # number of ReadReq misses
@@ -710,24 +710,24 @@ system.cpu0.dcache.LoadLockedReq_misses::total       356935
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu3.data            3                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2881220                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       910778                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1585735                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      6906953                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      12284686                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3353041                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1061174                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1793016                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      7252298                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     13459529                       # number of overall misses
+system.cpu0.dcache.demand_misses::cpu0.data      3558664                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      1023283                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1738093                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      7191429                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      13511469                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4030485                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1173679                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1945374                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      7536774                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     14686312                       # number of overall misses
 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  10960907500                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  17114957500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  61176605000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  89252470000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  61176597000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  89252462000                       # number of ReadReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9674205500                       # number of WriteReq miss cycles
 system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22728130500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 118919824516                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 151322160516                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 118919985516                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 151322321516                       # number of WriteReq miss cycles
 system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   2777991000                       # number of WriteLineReq miss cycles
 system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   3811495000                       # number of WriteLineReq miss cycles
 system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data   7834790952                       # number of WriteLineReq miss cycles
@@ -738,14 +738,14 @@ system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2393915500
 system.cpu0.dcache.LoadLockedReq_miss_latency::total   3676853500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       109000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total       109000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  20635113000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  39843088000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 180096429516                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 240574630516                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  20635113000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  39843088000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 180096429516                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 240574630516                       # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  23413104000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  43654583000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data 187931373468                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 254999060468                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  23413104000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  43654583000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data 187931373468                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 254999060468                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     62809109                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu1.data     19614550                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu2.data     27097166                       # number of ReadReq accesses(hits+misses)
@@ -776,16 +776,16 @@ system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       472149
 system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       627026                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1076112                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total      3720144                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    119804530                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     37347873                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data     50884496                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     90309722                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    298346621                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    120435264                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     37545442                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     51166914                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     90769675                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    299917295                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data    120611129                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     37505273                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data     51094537                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     90691938                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    299902877                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    121241863                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     37702842                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data     51376955                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     91151891                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    301473551                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032308                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033302                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.036372                       # miss rate for ReadReq accesses
@@ -814,24 +814,24 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094978
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024049                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024386                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.031163                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076481                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.041176                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027841                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028264                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.035042                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.079898                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.044877                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029505                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.027284                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.034017                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.079295                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.045053                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.033243                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.031130                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.037865                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.082684                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.048715                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16780.375170                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17365.542275                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17492.264147                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12456.076276                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17492.261860                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12456.075159                       # average ReadReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37558.061573                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37869.803304                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34877.929856                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 29559.093025                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34877.977076                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29559.124475                       # average WriteReq miss latency
 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24692.155904                       # average WriteLineReq miss latency
 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 25016.704079                       # average WriteLineReq miss latency
 system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27541.131596                       # average WriteLineReq miss latency
@@ -842,22 +842,20 @@ system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13374.800963
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10301.185090                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 36333.333333                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        21800                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22656.578222                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25125.943490                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26074.656873                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19583.295048                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19445.550871                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22221.267406                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24833.015620                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17873.926384                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     13201149                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22880.380110                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25116.367766                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26132.688436                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 18872.785814                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19948.473134                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22440.200702                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24935.253925                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17363.042571                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     13201195                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets        42765                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs           880108                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets            406                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.999465                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.999517                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets   105.332512                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      7502187                       # number of writebacks
 system.cpu0.dcache.writebacks::total          7502187                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3304                       # number of ReadReq MSHR hits
@@ -876,13 +874,13 @@ system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10548
 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       110240                       # number of LoadLockedReq MSHR hits
 system.cpu0.dcache.LoadLockedReq_mshr_hits::total       129352                       # number of LoadLockedReq MSHR hits
 system.cpu0.dcache.demand_mshr_hits::cpu1.data         8214                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       395160                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      4766953                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      5170327                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       395194                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      4769003                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      5172411                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.overall_mshr_hits::cpu1.data         8214                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       395160                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      4766953                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      5170327                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       395194                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      4769003                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      5172411                       # number of overall MSHR hits
 system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       649894                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       856500                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1559551                       # number of ReadReq MSHR misses
@@ -905,14 +903,14 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        68747
 system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136309                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            3                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       902564                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      1190575                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data      2140000                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4233139                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1052579                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      1395207                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data      2478269                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4926055                       # number of overall MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      1015069                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      1342899                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data      2422426                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4780394                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1165084                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      1547531                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data      2760695                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5473310                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6276                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6461                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         6522                       # number of ReadReq MSHR uncacheable
@@ -927,12 +925,12 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        12758
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        37346                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10091751000                       # number of ReadReq MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13620756000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26803800500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50516307500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26803792500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50516299500                       # number of ReadReq MSHR miss cycles
 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9207058000                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  12098027000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21802343152                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  43107428152                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21802435152                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  43107520152                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3089558000                       # number of SoftPFReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   4271039000                       # number of SoftPFReq MSHR miss cycles
 system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6719235000                       # number of SoftPFReq MSHR miss cycles
@@ -947,26 +945,22 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    981967500
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1882790500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       106000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       106000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19298809000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25718783000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  48606143652                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  93623735652                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22388367000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29989822000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  55325378652                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 107703567652                       # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  21964295000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  29376615500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  56011957104                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 107352867604                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  25053853000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  33647654500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  62731192104                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 121432699604                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1244510500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1253007000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1222915500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3720433000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1201167500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1184957500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1195953455                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3582078455                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2445678000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2437964500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2418868955                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7302511455                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1244510500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1253007000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1222915500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3720433000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033133                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031608                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031867                       # mshr miss rate for ReadReq accesses
@@ -989,22 +983,22 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.061778
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036271                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024166                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023398                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023696                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.014189                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028035                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027268                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027303                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.016425                       # mshr miss rate for overall accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.027065                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.026283                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.026710                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015940                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.030902                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.030121                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.030287                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018155                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15528.303077                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15902.809107                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17186.870131                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16476.586338                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17186.865002                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16476.583729                       # average ReadReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36439.062809                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36213.505949                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37561.169288                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36932.530626                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37561.327786                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36932.609448                       # average WriteReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20594.993834                       # average SoftPFReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20871.804019                       # average SoftPFReq mshr miss latency
 system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19863.584898                       # average SoftPFReq mshr miss latency
@@ -1019,27 +1013,22 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14283.786929
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.664608                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 35333.333333                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35333.333333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21382.205583                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21601.984755                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22713.151239                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22116.858353                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21270.011087                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21494.890722                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22324.202357                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21864.061130                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21638.228534                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21875.521167                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 23122.257235                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22456.907862                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21503.902723                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21742.798367                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22722.970884                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22186.336897                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198296.765456                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193933.911159                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 187506.209752                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193178.929332                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204245.451454                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198485.343384                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 191782.144804                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 198047.130812                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 201174.467385                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 196119.740970                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 189596.249804                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 195536.642612                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 102369.869211                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100796.959215                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95854.796990                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 99620.655492                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements         15833780                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.971388                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          559992507                       # Total number of references to valid blocks.
@@ -1094,16 +1083,16 @@ system.cpu0.icache.overall_misses::cpu3.inst      5076367
 system.cpu0.icache.overall_misses::total     16196934                       # number of overall misses
 system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22554803500                       # number of ReadReq miss cycles
 system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  53200018000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  68390400817                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 144145222317                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  68390346817                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 144145168317                       # number of ReadReq miss cycles
 system.cpu0.icache.demand_miss_latency::cpu1.inst  22554803500                       # number of demand (read+write) miss cycles
 system.cpu0.icache.demand_miss_latency::cpu2.inst  53200018000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst  68390400817                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 144145222317                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst  68390346817                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 144145168317                       # number of demand (read+write) miss cycles
 system.cpu0.icache.overall_miss_latency::cpu1.inst  22554803500                       # number of overall miss cycles
 system.cpu0.icache.overall_miss_latency::cpu2.inst  53200018000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst  68390400817                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 144145222317                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst  68390346817                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 144145168317                       # number of overall miss cycles
 system.cpu0.icache.ReadReq_accesses::cpu0.inst    347196455                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::cpu1.inst    108288078                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::cpu2.inst     67884539                       # number of ReadReq accesses(hits+misses)
@@ -1136,24 +1125,22 @@ system.cpu0.icache.overall_miss_rate::cpu3.inst     0.096106
 system.cpu0.icache.overall_miss_rate::total     0.028110                       # miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.567356                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13737.403425                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13472.312151                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8899.537549                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13472.301513                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8899.534215                       # average ReadReq miss latency
 system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13529.567356                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13737.403425                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13472.312151                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8899.537549                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13472.301513                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8899.534215                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13529.567356                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13737.403425                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13472.312151                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8899.537549                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13472.301513                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8899.534215                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs        58905                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs             3585                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.430962                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks     15833780                       # number of writebacks
 system.cpu0.icache.writebacks::total         15833780                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       362545                       # number of ReadReq MSHR hits
@@ -1176,16 +1163,16 @@ system.cpu0.icache.overall_mshr_misses::cpu3.inst      4713822
 system.cpu0.icache.overall_mshr_misses::total     10253537                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  20887728500                       # number of ReadReq MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  49327378000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  60408755849                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 130623862349                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  60408719849                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 130623826349                       # number of ReadReq MSHR miss cycles
 system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  20887728500                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  49327378000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  60408755849                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 130623862349                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  60408719849                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 130623826349                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  20887728500                       # number of overall MSHR miss cycles
 system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  49327378000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  60408755849                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 130623862349                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  60408719849                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 130623826349                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015395                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.057047                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.089243                       # mshr miss rate for ReadReq accesses
@@ -1200,17 +1187,16 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.089243
 system.cpu0.icache.overall_mshr_miss_rate::total     0.017795                       # mshr miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12529.567356                       # average ReadReq mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12737.403425                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12815.239067                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12739.395425                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12815.231430                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12739.391914                       # average ReadReq mshr miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12529.567356                       # average overall mshr miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12737.403425                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12815.239067                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12739.395425                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12815.231430                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12739.391914                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12529.567356                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12737.403425                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12815.239067                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12739.395425                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12815.231430                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12739.391914                       # average overall mshr miss latency
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1755,9 +1741,9 @@ system.cpu3.dtb.walker.walkWaitTime::720896-786431            3      0.00%    10
 system.cpu3.dtb.walker.walkWaitTime::786432-851967            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::total       188958                       # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkCompletionTime::samples       235670                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 22726.303730                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 18499.636586                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 17978.207208                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 22726.150974                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 18499.548679                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 17978.117081                       # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::0-65535       231036     98.03%     98.03% # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3674      1.56%     99.59% # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::131072-196607          687      0.29%     99.88% # Table walker service (enqueue to completion) latency
@@ -1926,11 +1912,11 @@ system.cpu3.itb.accesses                     53000163                       # DT
 system.cpu3.numCycles                       367393110                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles         140035519                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.icacheStallCycles         140035473                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu3.fetch.Insts                     329019087                       # Number of instructions fetch has processed
 system.cpu3.fetch.Branches                   74192352                       # Number of branches that fetch encountered
 system.cpu3.fetch.predictedBranches          45005042                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                    204823297                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.Cycles                    204823343                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu3.fetch.SquashCycles                7558478                       # Number of cycles fetch has spent squashing
 system.cpu3.fetch.TlbCycles                   1392210                       # Number of cycles fetch has spent waiting for tlb
 system.cpu3.fetch.MiscStallCycles               11060                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
@@ -1960,8 +1946,8 @@ system.cpu3.fetch.rateDist::max_value               8                       # Nu
 system.cpu3.fetch.rateDist::total           352706869                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.branchRate                 0.201943                       # Number of branch fetches per cycle
 system.cpu3.fetch.rate                       0.895551                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles               114206086                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles            168667065                       # Number of cycles decode is blocked
+system.cpu3.decode.IdleCycles               114206040                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles            168667111                       # Number of cycles decode is blocked
 system.cpu3.decode.RunCycles                 59684206                       # Number of cycles decode is running
 system.cpu3.decode.UnblockCycles              7159093                       # Number of cycles decode is unblocking
 system.cpu3.decode.SquashCycles               2988451                       # Number of cycles decode is squashing
@@ -1970,26 +1956,26 @@ system.cpu3.decode.BranchMispred               801920                       # Nu
 system.cpu3.decode.DecodedInsts             358900429                       # Number of instructions handled by decode
 system.cpu3.decode.SquashedInsts              2465138                       # Number of squashed instructions handled by decode
 system.cpu3.rename.SquashCycles               2988451                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles               118341629                       # Number of cycles rename is idle
+system.cpu3.rename.IdleCycles               118341583                       # Number of cycles rename is idle
 system.cpu3.rename.BlockCycles               14120881                       # Number of cycles rename is blocking
 system.cpu3.rename.serializeStallCycles     134077735                       # count of cycles rename stalled for serializing inst
 system.cpu3.rename.RunCycles                 62618980                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles             20557126                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts             350288916                       # Number of instructions processed by rename
+system.cpu3.rename.UnblockCycles             20557172                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts             350288919                       # Number of instructions processed by rename
 system.cpu3.rename.ROBFullEvents                64776                       # Number of times rename has blocked due to ROB full
 system.cpu3.rename.IQFullEvents               1233598                       # Number of times rename has blocked due to IQ full
 system.cpu3.rename.LQFullEvents                933453                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents              10294511                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.SQFullEvents              10294556                       # Number of times rename has blocked due to SQ full
 system.cpu3.rename.FullRegisterEvents            2108                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands          333834443                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            533414827                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups       412704170                       # Number of integer rename lookups
+system.cpu3.rename.RenamedOperands          333834444                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            533414830                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups       412704173                       # Number of integer rename lookups
 system.cpu3.rename.fp_rename_lookups           534789                       # Number of floating rename lookups
 system.cpu3.rename.CommittedMaps            279088781                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                54745657                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.UndoneMaps                54745658                       # Number of HB maps that are undone due to squashing
 system.cpu3.rename.serializingInsts           7872437                       # count of serializing insts renamed
 system.cpu3.rename.tempSerializingInsts       6763416                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                 39440190                       # count of insts added to the skid buffer
+system.cpu3.rename.skidInsts                 39440187                       # count of insts added to the skid buffer
 system.cpu3.memDep0.insertedLoads            56882383                       # Number of loads inserted to the mem dependence unit.
 system.cpu3.memDep0.insertedStores           47659648                       # Number of stores inserted to the mem dependence unit.
 system.cpu3.memDep0.conflictingLoads          7390317                       # Number of conflicting loads.
@@ -2107,7 +2093,7 @@ system.cpu3.iew.lsq.thread0.squashedStores      4830568                       #
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads      2150262                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked      4167982                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.cacheBlocked      4167936                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
 system.cpu3.iew.iewSquashCycles               2988451                       # Number of cycles IEW is squashing
 system.cpu3.iew.iewBlockCycles                8896535                       # Number of cycles IEW is blocking
@@ -2206,7 +2192,7 @@ system.cpu3.commit.op_class_0::total        293946017                       # Cl
 system.cpu3.commit.bw_lim_events             12651800                       # number cycles where commit BW limit reached
 system.cpu3.rob.rob_reads                   670506126                       # The number of ROB reads
 system.cpu3.rob.rob_writes                  688548433                       # The number of ROB writes
-system.cpu3.timesIdled                        2399442                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.timesIdled                        2399435                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu3.idleCycles                       14686241                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu3.quiesceCycles                 98624955783                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu3.committedInsts                  250222532                       # Number of Instructions Simulated
@@ -2319,19 +2305,19 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8806                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8846                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115470                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115510                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8806                       # number of overall misses
-system.iocache.overall_misses::total             8846                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115470                       # number of overall misses
+system.iocache.overall_misses::total           115510                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide   1073978422                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1073978422                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::realview.ide   6143621711                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   6143621711                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   1073978422                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1073978422                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   1073978422                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1073978422                       # number of overall miss cycles
+system.iocache.demand_miss_latency::realview.ide   7217600133                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7217600133                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   7217600133                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7217600133                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8806                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8843                       # number of ReadReq accesses(hits+misses)
@@ -2340,11 +2326,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8806                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8846                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115470                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115510                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8806                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8846                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115470                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115510                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2362,53 +2348,50 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 121959.848058
 system.iocache.ReadReq_avg_miss_latency::total 121449.555807                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 57597.893488                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 57597.893488                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 121959.848058                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 121408.367850                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 121959.848058                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 121408.367850                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 62506.279839                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 62484.634516                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 62506.279839                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 62484.634516                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         21262                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 2148                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.898510                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide         5707                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total         5707                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        48856                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        48856                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         5707                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         5707                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         5707                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         5707                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        54563                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        54563                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        54563                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        54563                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide    788628422                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total    788628422                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3698645601                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3698645601                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide    788628422                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    788628422                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide    788628422                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    788628422                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   4487274023                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4487274023                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   4487274023                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4487274023                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.648081                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.645369                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.458036                       # mshr miss rate for WriteLineReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::total     0.458036                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.648081                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.645150                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.648081                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.645150                       # mshr miss rate for overall accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.472530                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.472366                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.472530                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.472366                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138186.161206                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 138186.161206                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75705.043413                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75705.043413                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 138186.161206                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 138186.161206                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 138186.161206                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 138186.161206                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 82240.236479                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 82240.236479                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 82240.236479                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 82240.236479                       # average overall mshr miss latency
 system.l2c.tags.replacements                  1158394                       # number of replacements
 system.l2c.tags.tagsinuse                65318.411237                       # Cycle average of tags in use
 system.l2c.tags.total_refs                   47534578                       # Total number of references to valid blocks.
@@ -2623,16 +2606,16 @@ system.l2c.UpgradeReq_miss_latency::cpu3.data    400123500
 system.l2c.UpgradeReq_miss_latency::total    814695000                       # number of UpgradeReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data   6374133500                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu2.data   8353928000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data  15150863500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  29878925000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data  15150955500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  29879017000                       # number of ReadExReq miss cycles
 system.l2c.ReadCleanReq_miss_latency::cpu1.inst    923051000                       # number of ReadCleanReq miss cycles
 system.l2c.ReadCleanReq_miss_latency::cpu2.inst   3058997000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst   3584990498                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   7567038498                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst   3584977500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   7567025500                       # number of ReadCleanReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu1.data   3921909000                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu2.data   5597904500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data  11199575500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  20719389000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data  11199567500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  20719381000                       # number of ReadSharedReq miss cycles
 system.l2c.InvalidateReq_miss_latency::cpu2.data       701500                       # number of InvalidateReq miss cycles
 system.l2c.InvalidateReq_miss_latency::cpu3.data      3195500                       # number of InvalidateReq miss cycles
 system.l2c.InvalidateReq_miss_latency::total      3897000                       # number of InvalidateReq miss cycles
@@ -2646,9 +2629,9 @@ system.l2c.demand_miss_latency::cpu2.inst   3058997000                       # n
 system.l2c.demand_miss_latency::cpu2.data  13951832500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu3.dtb.walker    151670000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu3.itb.walker    115932500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst   3584990498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data  26350439000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     58680805998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst   3584977500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data  26350523000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     58680877000                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker     56208500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.itb.walker     55753500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.inst    923051000                       # number of overall miss cycles
@@ -2659,9 +2642,9 @@ system.l2c.overall_miss_latency::cpu2.inst   3058997000                       #
 system.l2c.overall_miss_latency::cpu2.data  13951832500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu3.dtb.walker    151670000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu3.itb.walker    115932500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst   3584990498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data  26350439000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    58680805998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst   3584977500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data  26350523000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    58680877000                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.dtb.walker       158649                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker       108349                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.dtb.walker        59053                       # number of ReadReq accesses(hits+misses)
@@ -2821,16 +2804,16 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 42158.202508
 system.l2c.UpgradeReq_avg_miss_latency::total 24046.487603                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130748.774384                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132278.683852                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 147115.758453                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74886.400662                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 147116.651778                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74886.631244                       # average ReadExReq miss latency
 system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130929.219858                       # average ReadCleanReq miss latency
 system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133908.115917                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136176.802325                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 80979.394054                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136176.308592                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 80979.254955                       # average ReadCleanReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 133407.340635                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 134795.070914                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141102.347175                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 79745.779738                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141102.246384                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 79745.748947                       # average ReadSharedReq miss latency
 system.l2c.InvalidateReq_avg_miss_latency::cpu2.data    26.509712                       # average InvalidateReq miss latency
 system.l2c.InvalidateReq_avg_miss_latency::cpu3.data    58.819740                       # average InvalidateReq miss latency
 system.l2c.InvalidateReq_avg_miss_latency::total     7.904008                       # average InvalidateReq miss latency
@@ -2844,9 +2827,9 @@ system.l2c.demand_avg_miss_latency::cpu2.inst 133908.115917
 system.l2c.demand_avg_miss_latency::cpu2.data 133276.964741                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 136886.281588                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu3.itb.walker 137850.772889                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 136176.802325                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 144498.398754                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 77349.390886                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 136176.308592                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 144498.859386                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 77349.484476                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135442.168675                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140437.027708                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 130929.219858                       # average overall miss latency
@@ -2857,17 +2840,15 @@ system.l2c.overall_avg_miss_latency::cpu2.inst 133908.115917
 system.l2c.overall_avg_miss_latency::cpu2.data 133276.964741                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 136886.281588                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu3.itb.walker 137850.772889                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 136176.802325                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 144498.398754                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 77349.390886                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 136176.308592                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 144498.859386                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 77349.484476                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              963697                       # number of writebacks
 system.l2c.writebacks::total                   963697                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            2                       # number of ReadReq MSHR hits
@@ -2968,16 +2949,16 @@ system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        68500
 system.l2c.SCUpgradeReq_mshr_miss_latency::total        68500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5886623500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   7722386503                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  14120672814                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  27729682817                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  14120764814                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  27729774817                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    852551000                       # number of ReadCleanReq MSHR miss cycles
 system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   2830553008                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3321691586                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   7004795594                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3321678588                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   7004782596                       # number of ReadCleanReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   3627879599                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   5182253070                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  10405522708                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  19215655377                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  10405514708                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  19215647377                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1325214500                       # number of InvalidateReq MSHR miss cycles
 system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   1812241000                       # number of InvalidateReq MSHR miss cycles
 system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   3731463500                       # number of InvalidateReq MSHR miss cycles
@@ -2992,9 +2973,9 @@ system.l2c.demand_mshr_miss_latency::cpu2.inst   2830553008
 system.l2c.demand_mshr_miss_latency::cpu2.data  12904639573                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    140343503                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    106366503                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst   3321691586                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data  24526195522                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  54426514794                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst   3321678588                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data  24526279522                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  54426585796                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     52058500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     51783500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst    852551000                       # number of overall MSHR miss cycles
@@ -3005,21 +2986,17 @@ system.l2c.overall_mshr_miss_latency::cpu2.inst   2830553008
 system.l2c.overall_mshr_miss_latency::cpu2.data  12904639573                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    140343503                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    106366503                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst   3321691586                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data  24526195522                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  54426514794                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst   3321678588                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data  24526279522                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  54426585796                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1166018500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1172239500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1141338500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total   3479596500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1133536000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1116215000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1124184998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   3373935998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2299554500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2288454500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2265523498                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6853532498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1166018500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1172239500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1141338500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3479596500                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.007028                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.009040                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003503                       # mshr miss rate for ReadReq accesses
@@ -3090,16 +3067,16 @@ system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        68500
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120748.774384                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122278.660148                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137112.547472                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 129040.689545                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137113.440798                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 129041.117669                       # average ReadExReq mshr miss latency
 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120929.219858                       # average ReadCleanReq mshr miss latency
 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123907.941166                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126175.324242                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124596.150729                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126174.830510                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124595.919530                       # average ReadCleanReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123405.660215                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124798.388200                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131103.109627                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127855.477184                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131103.008832                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127855.423955                       # average ReadSharedReq mshr miss latency
 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 67688.962100                       # average InvalidateReq mshr miss latency
 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 68484.657244                       # average InvalidateReq mshr miss latency
 system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 68685.248587                       # average InvalidateReq mshr miss latency
@@ -3114,9 +3091,9 @@ system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123907.941166
 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123278.208361                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126175.324242                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134496.973058                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 128015.097468                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126174.830510                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134497.433698                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 128015.264469                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125442.168675                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130437.027708                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120929.219858                       # average overall mshr miss latency
@@ -3127,22 +3104,17 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123907.941166
 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123278.208361                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126175.324242                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134496.973058                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 128015.097468                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126174.830510                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134497.433698                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 128015.264469                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185790.073295                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181433.137285                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 174998.236737                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180673.788878                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192745.451454                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186970.686767                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180273.412123                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 186539.282247                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 189154.766801                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 184092.550881                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 177576.696818                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 183514.499491                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95913.342107                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94299.694313                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 89460.612949                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 93171.865796                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               76738                       # Transaction distribution
 system.membus.trans_dist::ReadResp             445217                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33648                       # Transaction distribution
@@ -3189,11 +3161,11 @@ system.membus.reqLayer0.occupancy            62370000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1759502                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1751500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          3098675220                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          3098674718                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2309466891                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2309468641                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer3.occupancy           28779324                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
@@ -3249,8 +3221,8 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     51706902                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     26184437                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     51706899                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     26184435                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_requests         3148                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops           2316                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops         2316                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
@@ -3282,28 +3254,28 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      292
 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6124520                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size::total             3057992990                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                         1664727                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         38155395                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples         38155391                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            0.016407                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           0.127033                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               37529393     98.36%     98.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               37529389     98.36%     98.36% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                 626002      1.64%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           38155395                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        30930828488                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           38155391                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        30930822494                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           835176                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       15386050434                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       15386050433                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
 system.toL2Bus.respLayer1.occupancy        7871932216                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.toL2Bus.respLayer2.occupancy         287489224                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         705270826                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         705270825                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index 272e9258d..ad76c447e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,161 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.761757                       # Number of seconds simulated
-sim_ticks                                51761756862000                       # Number of ticks simulated
-final_tick                               51761756862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.284902                       # Number of seconds simulated
+sim_ticks                                51284901790000                       # Number of ticks simulated
+final_tick                               51284901790000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 265912                       # Simulator instruction rate (inst/s)
-host_op_rate                                   283734                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5899295346                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 166610                       # Simulator instruction rate (inst/s)
+host_op_rate                                   195762                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9559915430                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 696216                       # Number of bytes of host memory used
-host_seconds                                  8774.23                       # Real time elapsed on the host
-sim_insts                                  2333170820                       # Number of instructions simulated
-sim_ops                                    2489548001                       # Number of ops (including micro ops) simulated
+host_seconds                                  5364.58                       # Real time elapsed on the host
+sim_insts                                   893791087                       # Number of instructions simulated
+sim_ops                                    1050181412                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       151872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       131712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3595840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         25977120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       153216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       139456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3729408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         26080296                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        414272                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             60373192                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3595840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3729408                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7325248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78844864                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       151616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       131392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3547392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         26803872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       164672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       152640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3783872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         26210856                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        417152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             61363464                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3547392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3783872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7331264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     79575360                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78865444                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2373                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2058                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             56185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            405901                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2394                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2179                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             58272                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            407509                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6473                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                943344                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1231951                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          79595940                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2369                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2053                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             55428                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            418819                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2573                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2385                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             59123                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            409549                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6518                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                958817                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1243365                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1234524                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2934                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               69469                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              501859                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2960                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2694                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               72049                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              503853                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8003                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1166367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          69469                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          72049                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             141519                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1523226                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1245938                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               69170                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              522646                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2976                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               73781                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              511083                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8134                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1196521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          69170                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          73781                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             142952                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1551633                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1523624                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1523226                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2934                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              69469                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             501859                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2960                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2694                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              72049                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             504250                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8003                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2689991                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        943344                       # Number of read requests accepted
-system.physmem.writeReqs                      1234524                       # Number of write requests accepted
-system.physmem.readBursts                      943344                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1234524                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 60330432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     43584                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78865536                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  60373192                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78865444                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      681                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1552035                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1551633                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              69170                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             522647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2976                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              73781                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             511484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8134                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2748556                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        958817                       # Number of read requests accepted
+system.physmem.writeReqs                      1245938                       # Number of write requests accepted
+system.physmem.readBursts                      958817                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1245938                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 61319744                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     44544                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  79596352                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  61363464                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               79595940                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      696                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2241                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               54550                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               62293                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               54512                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               54260                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               56553                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               67360                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               57276                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               56002                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               51757                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               79766                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              59095                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              64327                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              57398                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              60635                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              53657                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              53222                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               73571                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               79159                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               74534                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               76045                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               77226                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               85193                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               75384                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               76786                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               72797                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               79168                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              77101                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              81604                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              76385                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              80183                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              73603                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              73535                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               56014                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               61765                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               56852                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               54266                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               57300                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               65586                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               58254                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               56988                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               55394                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               83577                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              57993                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              64464                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              57098                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              62288                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              55335                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              54947                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               75753                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               78600                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               75987                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               76409                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               77268                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               81844                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               76609                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               77405                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               75535                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               81820                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              76863                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              81595                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              75866                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              80975                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              75599                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              75565                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          35                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51761755618000                       # Total gap between requests
+system.physmem.numWrRetry                          53                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51284900546000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  943329                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  958802                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1231951                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    533668                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    268938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     92505                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     42053                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       700                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       555                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       557                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       322                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      352                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      193                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1243365                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    542154                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    273293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     94311                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     42898                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       714                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       582                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       526                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1098                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       760                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       325                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      373                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      195                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                      181                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      104                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      140                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      128                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -165,173 +165,174 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::1024-1151        45047      8.23%    100.00% # Bytes accessed per row activation
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 system.physmem.rdPerTurnAround::512-1023            2      0.00%     99.99% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::2560-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::7680-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::total           63900                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         63900                       # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::gmean       18.392697                       # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::24-31            6734     10.54%     96.07% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::72-79             150      0.23%     99.66% # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::328-335             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           63900                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    25011662426                       # Total ticks spent queuing
-system.physmem.totMemAccLat               42686593676                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4713315000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26532.98                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           64596                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    25254361125                       # Total ticks spent queuing
+system.physmem.totMemAccLat               43219129875                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4790605000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26358.22                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45282.98                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.17                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.17                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45108.22                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.20                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.55                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.19                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     724331                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    903369                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.84                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.31                       # Row buffer hit rate for writes
-system.physmem.avgGap                     23767168.45                       # Average gap between requests
-system.physmem.pageHitRate                      74.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2099502720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1145562000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3609886800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4003979040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3380826018960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1247139310140                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29963069496750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34601893756410                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.483818                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49846129273502                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1728438660000                       # Time in different power states
+system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         9.83                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     736278                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    909804                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.85                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.15                       # Row buffer hit rate for writes
+system.physmem.avgGap                     23261042.86                       # Average gap between requests
+system.physmem.pageHitRate                      74.76                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2087694000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1139118750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3642795000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4016790000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3349680278880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1234735113780                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29687838385500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34283140175910                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.484113                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49388248138285                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1712515480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    187184326498                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    184135332965                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2037593880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1111782375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3742837800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3981156480                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3380826018960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1247115577050                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29963090307000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34601905273545                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.484040                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49846127379717                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1728438660000                       # Time in different power states
+system.physmem_1.actEnergy                 2113632360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1153271625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3830509800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4042340640                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3349680278880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1240634967750                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29682663075000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34284118076055                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.503181                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49379589334828                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1712515480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    187190202783                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    192796355672                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -347,33 +348,33 @@ system.realview.nvmem.num_reads::total             38                       # Nu
 system.realview.nvmem.bw_read::cpu0.inst           21                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.inst           20                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               41                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               42                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst           21                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu1.inst           20                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total           41                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst           21                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           20                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              41                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              42                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              441769882                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted        346318853                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5806285                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           315736094                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits              267112052                       # Number of BTB hits
+system.cpu0.branchPred.lookups              131701737                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         88290011                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5749928                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            88871773                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               60662484                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            84.599784                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17170317                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            190049                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        5021410                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2619937                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         2401473                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       415468                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            68.258438                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               16943081                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            189225                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4992924                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2589273                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         2403651                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       412581                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -404,93 +405,91 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   892710                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               892710                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17744                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        89453                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       550305                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       342405                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2673.589755                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 15902.851063                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       339616     99.19%     99.19% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1452      0.42%     99.61% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          967      0.28%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          143      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679          137      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           16      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           33      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287           35      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   895264                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               895264                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17123                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90441                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       554296                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       340968                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2750.470719                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 16351.798354                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       338087     99.16%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1498      0.44%     99.59% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          976      0.29%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          136      0.04%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679          169      0.05%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           22      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           39      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287           36      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       342405                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       416567                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23523.175143                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18877.823931                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 19885.199602                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       406963     97.69%     97.69% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         7350      1.76%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1585      0.38%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          137      0.03%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          275      0.07%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215          156      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           65      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           27      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       416567                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 844595026420                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.078472                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.490568                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 843548733920     99.88%     99.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    573107500      0.07%     99.94% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    199238500      0.02%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    117034000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     49115000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     33953000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     28746000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     36613000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      8069500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       361500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        23000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47         9000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51        14500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::52-55         3000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::56-59         3000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::60-63         2000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 844595026420                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        89453     83.45%     83.45% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        17744     16.55%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       107197                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       892710                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total       340968                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       416487                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22961.536615                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18398.217426                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 19575.689133                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       407358     97.81%     97.81% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6820      1.64%     99.45% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1636      0.39%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          111      0.03%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          329      0.08%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215          154      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           63      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       416487                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 342294024144                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.109470                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.721232                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 341240531644     99.69%     99.69% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    582822500      0.17%     99.86% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    199579000      0.06%     99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    117924500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     46760000      0.01%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     24862000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     28899000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     44321000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      7892500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       388000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        22500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47        11000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51        10500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 342294024144                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        90442     84.08%     84.08% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        17123     15.92%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       107565                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       895264                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       892710                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107197                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       895264                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107565                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107197                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       999907                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107565                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total      1002829                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   311659377                       # DTB read hits
-system.cpu0.dtb.read_misses                    618746                       # DTB read misses
-system.cpu0.dtb.write_hits                   81669046                       # DTB write hits
-system.cpu0.dtb.write_misses                   273964                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1566                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   104837372                       # DTB read hits
+system.cpu0.dtb.read_misses                    616098                       # DTB read misses
+system.cpu0.dtb.write_hits                   80671443                       # DTB write hits
+system.cpu0.dtb.write_misses                   279166                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1102                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21904                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    550                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   56873                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      200                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9024                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              21868                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    546                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   55634                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      233                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9003                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    58972                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               312278123                       # DTB read accesses
-system.cpu0.dtb.write_accesses               81943010                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    56722                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               105453470                       # DTB read accesses
+system.cpu0.dtb.write_accesses               80950609                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        393328423                       # DTB hits
-system.cpu0.dtb.misses                         892710                       # DTB misses
-system.cpu0.dtb.accesses                    394221133                       # DTB accesses
+system.cpu0.dtb.hits                        185508815                       # DTB hits
+system.cpu0.dtb.misses                         895264                       # DTB misses
+system.cpu0.dtb.accesses                    186404079                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -520,852 +519,838 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                   100670                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               100670                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3435                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        68577                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        13827                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        86843                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1681.770551                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 11901.774457                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        85828     98.83%     98.83% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          525      0.60%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303           54      0.06%     99.50% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          177      0.20%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839          176      0.20%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           42      0.05%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375           17      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks                   102402                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               102402                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3079                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69849                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        14173                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        88229                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1559.917941                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 11109.318329                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        87313     98.96%     98.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          469      0.53%     99.49% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303           83      0.09%     99.59% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          147      0.17%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839          141      0.16%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           43      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375           17      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::294912-327679            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        86843                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        85839                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29252.396929                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24357.820404                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 23461.302389                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        83908     97.75%     97.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          516      0.60%     98.35% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1196      1.39%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           80      0.09%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679          102      0.12%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        85839                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 638425660712                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.889219                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.314244                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    70792067924     11.09%     11.09% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   567575291288     88.90%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       51231500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        6018000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         857500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5         106500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6          88000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 638425660712                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        68577     95.23%     95.23% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         3435      4.77%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        72012                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        88229                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        87101                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 28953.462073                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24215.206372                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 22576.849397                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        85266     97.89%     97.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          483      0.55%     98.45% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607         1148      1.32%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           69      0.08%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           97      0.11%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           24      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           11      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        87101                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 630054255476                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.901585                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.298241                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    62069607016      9.85%      9.85% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   567926877960     90.14%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       53229500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        3926000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         600500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          14500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 630054255476                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        69849     95.78%     95.78% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         3079      4.22%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        72928                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       100670                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       100670                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102402                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102402                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72012                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72012                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       172682                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   300349481                       # ITB inst hits
-system.cpu0.itb.inst_misses                    100670                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72928                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72928                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       175330                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    93547159                       # ITB inst hits
+system.cpu0.itb.inst_misses                    102402                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1566                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1102                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21904                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    550                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   41410                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21868                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    546                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   41100                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   188775                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   189115                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               300450151                       # ITB inst accesses
-system.cpu0.itb.hits                        300349481                       # DTB hits
-system.cpu0.itb.misses                         100670                       # DTB misses
-system.cpu0.itb.accesses                    300450151                       # DTB accesses
-system.cpu0.numCycles                      1153591288                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                93649561                       # ITB inst accesses
+system.cpu0.itb.hits                         93547159                       # DTB hits
+system.cpu0.itb.misses                         102402                       # DTB misses
+system.cpu0.itb.accesses                     93649561                       # DTB accesses
+system.cpu0.numCycles                       688011025                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         452660277                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                    1310968350                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  441769882                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches         286902306                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    657569557                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13257965                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2520501                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               22487                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             4210                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      4808989                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       163286                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         3813                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                300145403                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3627233                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  38474                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples        1124381714                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.254786                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.113096                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         243601869                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     585571838                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  131701737                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          80194838                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    401370000                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13146214                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2578790                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               20091                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             3656                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      4829637                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       164032                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         3268                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 93342305                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3584098                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  39018                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         659144176                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.038197                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.295091                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               722021873     64.22%     64.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               121051325     10.77%     74.98% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18164334      1.62%     76.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13282328      1.18%     77.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4               182681747     16.25%     94.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 8985206      0.80%     94.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9665427      0.86%     95.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8249650      0.73%     96.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                40279824      3.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               515420904     78.20%     78.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                17940395      2.72%     80.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                18023461      2.73%     83.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13220348      2.01%     85.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                27959766      4.24%     89.90% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 8806264      1.34%     91.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9588960      1.45%     92.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8203319      1.24%     93.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                39980759      6.07%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total          1124381714                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.382952                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       1.136424                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               405971329                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            336686919                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                362849881                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13601656                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5263930                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            71142613                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1385162                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts            1364494980                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4266008                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5263930                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               413565658                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               26498073                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     263444659                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                368730385                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             46870910                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts            1349255091                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               116974                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2261616                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1896807                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              27181012                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3751                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands         1320809578                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups           1942299251                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups      1409770765                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           775838                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps           1225247186                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                95562392                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15257380                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13270852                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 75639942                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           307378259                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           85793639                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13768177                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14589388                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                1316697465                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15319190                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued               1317684473                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           854895                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       81379212                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     50931090                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        359979                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples   1124381714                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        1.171919                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.498403                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           659144176                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.191424                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.851108                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               197499187                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            338466010                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                104398182                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13546805                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5231982                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19379138                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1360316                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             638255296                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4185441                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5231982                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               205063449                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               27153307                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     262923483                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                110249317                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             48520379                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             622996110                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               132355                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2247994                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1861879                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              28960972                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            3803                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          595426650                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            956549851                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       734166245                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           794435                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            500270864                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                95155781                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15187791                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13237681                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 75403173                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           100496845                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           84720468                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13599194                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14388955                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 590484103                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15298411                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                591681421                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           857551                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       80930976                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     50447616                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        351888                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    659144176                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.897651                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.636567                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          479017696     42.60%     42.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          355860200     31.65%     74.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           94607581      8.41%     82.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           82377744      7.33%     89.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           74414845      6.62%     96.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           16123062      1.43%     98.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           11093083      0.99%     99.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6457333      0.57%     99.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4430170      0.39%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          427475761     64.85%     64.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           97836885     14.84%     79.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           42770645      6.49%     86.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           30584958      4.64%     90.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           22743510      3.45%     94.28% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           15987914      2.43%     96.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           10968411      1.66%     98.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6384440      0.97%     99.33% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4391652      0.67%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total     1124381714                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      659144176                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                3027806     25.46%     25.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 21993      0.18%     25.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   1913      0.02%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4879295     41.03%     66.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3961438     33.31%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                2986555     25.26%     25.26% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 23747      0.20%     25.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   2157      0.02%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4879643     41.27%     66.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3932744     33.26%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               30      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            919558912     69.79%     69.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1403204      0.11%     69.89% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                63552      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                184      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         53817      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           313882941     23.82%     93.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           82721833      6.28%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass              139      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            401347935     67.83%     67.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1444621      0.24%     68.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                64829      0.01%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                116      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         56174      0.01%     68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           107054227     18.09%     86.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           81713380     13.81%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total            1317684473                       # Type of FU issued
-system.cpu0.iq.rate                          1.142246                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11892445                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.009025                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        3771522724                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes       1413606609                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses   1295090800                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             975276                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            499965                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       431562                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses            1329056054                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 520834                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4724292                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             591681421                       # Type of FU issued
+system.cpu0.iq.rate                          0.859988                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11824846                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019985                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1854198838                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        686917057                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    569115204                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             990577                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            508872                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       439153                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             602977632                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 528496                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4632250                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     16714956                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        20317                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       722500                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      8583352                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     16643333                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        19794                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       724475                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      8465055                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3995442                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      8184292                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3918685                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      8300346                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5263930                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               15793558                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              8769722                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts         1332158998                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1730842                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            307378259                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            85793639                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          12984237                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                229560                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              8457997                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        722500                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2474503                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2706494                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5180997                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts           1310764150                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            311649701                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          6040737                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5231982                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15925349                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              9030114                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          605926435                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1719706                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts            100496845                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            84720468                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          12946615                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                222991                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              8727203                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        724475                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2456659                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2686981                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5143640                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            584799722                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            104827609                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          5998636                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       142343                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   393318158                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               417986859                       # Number of branches executed
-system.cpu0.iew.exec_stores                  81668457                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.136247                       # Inst execution rate
-system.cpu0.iew.wb_sent                    1296930060                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                   1295522362                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                592614892                       # num instructions producing a value
-system.cpu0.iew.wb_consumers               1110609614                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      1.123034                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.533594                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       81425087                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       14959211                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4440844                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples   1110541032                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     1.126151                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.560922                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       143921                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   185499348                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               108059724                       # Number of branches executed
+system.cpu0.iew.exec_stores                  80671739                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.849986                       # Inst execution rate
+system.cpu0.iew.wb_sent                     570956210                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    569554357                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                281415896                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                488383708                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.827827                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.576219                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       80977867                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       14946523                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4408529                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    645374166                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.813252                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.811592                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    504262189     45.41%     45.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    302033951     27.20%     72.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2    135703334     12.22%     84.82% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3    118428443     10.66%     95.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10778674      0.97%     96.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6605089      0.59%     97.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6100457      0.55%     97.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3862548      0.35%     97.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22766347      2.05%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    452622252     70.13%     70.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     95504432     14.80%     84.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     32341034      5.01%     89.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     15221107      2.36%     92.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10764054      1.67%     93.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6526900      1.01%     94.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6016149      0.93%     95.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3811802      0.59%     96.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22566436      3.50%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total   1110541032                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts          1171621966                       # Number of instructions committed
-system.cpu0.commit.committedOps            1250637443                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    645374166                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           446835848                       # Number of instructions committed
+system.cpu0.commit.committedOps             524851533                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     367873590                       # Number of memory references committed
-system.cpu0.commit.loads                    290663303                       # Number of loads committed
-system.cpu0.commit.membars                    3675290                       # Number of memory barriers committed
-system.cpu0.commit.branches                 409547032                       # Number of branches committed
-system.cpu0.commit.fp_insts                    413703                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts               1052721176                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13293497                       # Number of function calls committed.
+system.cpu0.commit.refs                     160108924                       # Number of memory references committed
+system.cpu0.commit.loads                     83853511                       # Number of loads committed
+system.cpu0.commit.membars                    3685792                       # Number of memory barriers committed
+system.cpu0.commit.branches                  99662639                       # Number of branches committed
+system.cpu0.commit.fp_insts                    420768                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                481718978                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13112301                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       881582024     70.49%     70.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1088872      0.09%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           47670      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        45287      0.00%     70.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead      290663303     23.24%     93.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      77210287      6.17%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       363528180     69.26%     69.26% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1118140      0.21%     69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           48609      0.01%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        47680      0.01%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       83853511     15.98%     85.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      76255413     14.53%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total       1250637443                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22766347                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  2415886012                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 2677991243                       # The number of ROB writes
-system.cpu0.timesIdled                        4174406                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       29209574                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 53218608185                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                 1171621966                       # Number of Instructions Simulated
-system.cpu0.committedOps                   1250637443                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              0.984610                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.984610                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.015630                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.015630                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads              1363459198                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              822633893                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   827834                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  497604                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                434759871                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               435903549                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             2497252569                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15072789                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements         10543122                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.973214                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          714246594                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10543634                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            67.741975                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   297.299431                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   214.673783                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.580663                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.419285                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total        524851533                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22566436                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1224636916                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1225450764                       # The number of ROB writes
+system.cpu0.timesIdled                        4112135                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       28866849                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 54222947414                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  446835848                       # Number of Instructions Simulated
+system.cpu0.committedOps                    524851533                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.539740                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.539740                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.649460                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.649460                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               688252111                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              407094655                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   800302                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  473448                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                125192637                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               126303504                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1203085849                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15043668                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10538852                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.973177                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          302937432                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10539364                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.743426                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       2695088500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   218.644895                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   293.328283                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.427041                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.572907                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999948                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       2981506473                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      2981506473                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data    286698087                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data    284974964                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      571673051                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67938381                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     66316619                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     134255000                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       207203                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       195617                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       402820                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       177871                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       146629                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       324500                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1740566                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1760771                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3501337                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2018486                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2021987                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4040473                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    354636468                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    351291583                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       705928051                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    354843671                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    351487200                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      706330871                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6383220                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6242093                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12625313                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6497631                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6239975                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     12737606                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       683741                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       608697                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1292438                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       573671                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       664585                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1238256                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       331614                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       318292                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       649906                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            5                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     12880851                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     12482068                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      25362919                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13564592                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     13090765                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     26655357                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110753552000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111947542000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 222701094000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 287335391122                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 284659105303                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 571994496425                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  22737846434                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  30047699861                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  52785546295                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4579227500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4402893000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   8982120500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       138500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.tags.tag_accesses       1336210971                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1336210971                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     79968247                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     80371614                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      160339861                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67069375                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total     134274964                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       199346                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       203477                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       402823                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       140986                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       183532                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       324518                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1741209                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1760714                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3501923                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2021774                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2019563                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      4041337                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    147178608                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    147760735                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       294939343                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    147377954                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total      295342166                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6393063                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total     12628655                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      6405631                       # number of WriteReq misses
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+system.cpu0.dcache.WriteReq_misses::total     12723077                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       674803                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       616721                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1291524                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       612571                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       626179                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1238750                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       334024                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       316429                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       650453                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            7                       # number of StoreCondReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total           14                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     13411265                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data     13179217                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      26590482                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     14086068                       # number of overall misses
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+system.cpu0.dcache.overall_misses::total     27882006                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112258104000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112113839000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 224371943000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 288348477097                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 285240354815                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 573588831912                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25994460850                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  27091662781                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  53086123631                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4580448500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4477345000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   9057793500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       368500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        96000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       234500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 398088943122                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 396606647303                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 794695590425                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 398088943122                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 396606647303                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 794695590425                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data    293081307                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data    291217057                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    584298364                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     74436012                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     72556594                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    146992606                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       890944                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       804314                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1695258                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       751542                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       811214                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1562756                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2072180                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2079063                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4151243                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2018491                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2021989                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4040480                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    367517319                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    363773651                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    731290970                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    368408263                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    364577965                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    732986228                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.021780                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.021435                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.021608                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.087291                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.086001                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.086655                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.767434                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.756790                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.762384                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763325                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.819247                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792354                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.160031                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.153094                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156557                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.035048                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.034313                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.034682                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036819                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.035907                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.036365                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.733956                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17934.295756                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17639.253300                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44221.561846                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45618.629130                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44905.965566                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 39635.690899                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45212.726530                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 42628.944495                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13808.908852                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13832.873588                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13820.645601                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        27700                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        48000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        33500                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30905.484670                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31774.113657                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 31332.970406                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29347.653296                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30296.674587                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 29813.729016                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     70477710                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       116225                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3519959                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1128                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    20.022310                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   103.036348                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8078087                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8078087                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3526105                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3409163                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      6935268                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5405186                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5181209                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10586395                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3376                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3483                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         6859                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       204163                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       196814                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       400977                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      8931291                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      8590372                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17521663                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      8931291                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      8590372                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17521663                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2857115                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2832930                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5690045                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1092445                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1058766                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2151211                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       668680                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       599708                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1268388                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       570295                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       661102                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1231397                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       127451                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121478                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       248929                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            5                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3949560                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3891696                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7841256                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4618240                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4491404                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9109644                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16758                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16944                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15500                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18208                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32258                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35152                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67410                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48892925500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49984550000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98877475500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  50989234756                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  50617210449                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101606445205                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13305949000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11256900000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24562849000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  21948256934                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  29156940361                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  51105197295                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1850360000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1748512000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3598872000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       133500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        94000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       227500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99882160256                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100601760449                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 200483920705                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 113188109256                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111858660449                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 225046769705                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3097490500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3134623000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232113500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2979818500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3228691491                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6208509991                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6077309000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6363314491                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12440623491                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.009749                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.009728                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009738                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014676                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014592                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014635                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750530                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.745614                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.748198                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.758833                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.814954                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787965                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061506                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058429                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059965                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.010747                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.010698                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.010722                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.012536                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.012319                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.012428                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17112.690774                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17644.117574                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17377.274784                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46674.418168                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47807.740756                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47232.207908                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19898.829036                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18770.635042                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19365.406327                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38485.795832                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44103.542813                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41501.804288                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14518.206997                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14393.651525                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14457.423603                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        26700                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        47000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        32500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25289.439901                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25850.364584                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25567.832590                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24508.927482                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24905.054288                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24704.233196                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184836.525838                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184998.996695                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.209602                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 192246.354839                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177322.687335                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184185.059659                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188396.955794                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 181022.829170                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184551.602003                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         16336648                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.932732                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          580722956                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16337160                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.546139                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      19421278500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   279.802291                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   232.130441                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.546489                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.453380                       # Average percentage of cache occupancy
+system.cpu0.dcache.StoreCondReq_miss_latency::total       464500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 426601041947                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 424445856596                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 851046898543                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 426601041947                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 424445856596                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 851046898543                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     86361310                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     86607206                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    172968516                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     73475006                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     73523035                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    146998041                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       874149                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       820198                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1694347                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       753557                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       809711                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1563268                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2075233                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2077143                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4152376                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2021781                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2019570                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4041351                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    160589873                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    160939952                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    321529825                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    161464022                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    161760150                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    323224172                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074027                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.071999                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.073011                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.087181                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.085925                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.086553                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771954                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.751917                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.762255                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.812906                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.773336                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792411                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.160957                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152339                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156646                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.083513                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.081889                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.082700                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087240                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.085286                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.086262                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17559.361452                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17979.662396                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17766.891486                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45014.843518                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45151.213768                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45082.556045                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 42435.017084                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 43265.045268                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 42854.590217                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13712.932304                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14149.603861                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13925.362017                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 52642.857143                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13714.285714                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 33178.571429                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31809.157596                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32205.696029                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 32005.696570                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30285.317517                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30766.002036                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 30523.158862                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     71133587                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       117068                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3523085                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           1178                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    20.190710                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    99.378608                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks      8064911                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8064911                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3541728                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3397150                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      6938878                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5324879                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5249115                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10573994                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3231                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3726                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         6957                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       207685                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       194963                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       402648                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      8869838                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      8649991                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     17519829                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      8869838                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      8649991                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     17519829                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2851335                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2838442                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5689777                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1080752                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1068331                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2149083                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       659293                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       608119                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1267412                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       609340                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       622453                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1231793                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       126339                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121466                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       247805                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           14                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4541427                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      4529226                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      9070653                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5200720                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      5137345                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total     10338065                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16852                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16826                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15677                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18019                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32529                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        34845                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49729929500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49824787000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  99554716500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  51055928904                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  51023445012                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 102079373916                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13986697500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11236562000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  25223259500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  25203665850                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  26199660281                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  51403326131                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1811818500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1809464500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3621283000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       361500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        89000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       450500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 125989524254                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 127047892293                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 253037416547                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139976221754                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 138284454293                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 278260676047                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3092079500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3139092000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6231171500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3092079500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3139092000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6231171500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033016                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032774                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032895                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014709                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014531                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014620                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.754211                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.741430                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.748024                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.808618                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.768735                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787960                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060879                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058477                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059678                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028280                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028142                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028211                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032210                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031759                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031984                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17440.928372                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17553.568824                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17497.120977                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47241.114431                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47759.959237                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47499.037457                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21214.691344                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.571002                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19901.389209                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 41362.237585                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42090.985634                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41730.490538                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14340.927979                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14896.880609                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14613.437986                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 51642.857143                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 32178.571429                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27742.276658                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28050.685104                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27896.273460                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26914.777522                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26917.494210                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26916.127539                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183484.423214                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186561.987400                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185022.017341                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95056.088413                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 90087.300904                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92486.292932                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.replacements         16323462                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.933155                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          169414196                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16323974                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.378245                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      19400599500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   237.111231                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   274.821924                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.463108                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.536762                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          293                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        614644224                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       614644224                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    291297674                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    289425282                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      580722956                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    291297674                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    289425282                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       580722956                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    291297674                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    289425282                       # number of overall hits
-system.cpu0.icache.overall_hits::total      580722956                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8834570                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8749295                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17583865                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8834570                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      8749295                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      17583865                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8834570                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      8749295                       # number of overall misses
-system.cpu0.icache.overall_misses::total     17583865                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 118633487353                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 118783272350                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 237416759703                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 118633487353                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 118783272350                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 237416759703                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 118633487353                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 118783272350                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 237416759703                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    300132244                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    298174577                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    598306821                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    300132244                       # number of demand (read+write) accesses
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-system.cpu0.icache.demand_accesses::total    598306821                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    300132244                       # number of overall (read+write) accesses
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-system.cpu0.icache.overall_accesses::total    598306821                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029436                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.029343                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.029389                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029436                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.029343                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.029389                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029436                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.029343                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.029389                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13428.326150                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13576.324990                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13501.966701                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13428.326150                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13576.324990                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13501.966701                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13428.326150                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13576.324990                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13501.966701                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs       128000                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        203303412                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       203303412                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     84627850                       # number of ReadReq hits
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+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116896379852                       # number of ReadReq miss cycles
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+system.cpu0.icache.ReadReq_miss_rate::total     0.093940                       # miss rate for ReadReq accesses
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+system.cpu0.icache.overall_miss_rate::total     0.093940                       # miss rate for overall accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::total 13507.007541                       # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::total 13507.007541                       # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total 13507.007541                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs       128531                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             8615                       # number of cycles access was blocked
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 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.857806                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.052231                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks     16336648                       # number of writebacks
-system.cpu0.icache.writebacks::total         16336648                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       624990                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       621471                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1246461                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       624990                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       621471                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1246461                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       624990                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       621471                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1246461                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8209580                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8127824                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     16337404                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8209580                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      8127824                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     16337404                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8209580                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      8127824                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16337404                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total        20646                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total        20646                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104820770896                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 104795182400                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 209615953296                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104820770896                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 104795182400                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 209615953296                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104820770896                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 104795182400                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 209615953296                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636383000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636383000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027353                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027259                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027306                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027353                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.027259                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.027306                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027353                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.027259                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.027306                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12768.103959                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12893.387258                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12830.432136                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12768.103959                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12893.387258                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12830.432136                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12768.103959                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12893.387258                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12830.432136                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              439037695                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted        344630545                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5789779                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           303336917                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits              265424368                       # Number of BTB hits
+system.cpu0.icache.writebacks::writebacks     16323462                       # number of writebacks
+system.cpu0.icache.writebacks::total         16323462                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       613191                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       627375                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total      1240566                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       613191                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst       627375                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total      1240566                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       613191                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst       627375                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total      1240566                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8088280                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8236045                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     16324325                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      8088280                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      8236045                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     16324325                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      8088280                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      8236045                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     16324325                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        12957                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7688                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total        20645                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        12957                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7688                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total        20645                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103270633406                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 106205385876                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 209476019282                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103270633406                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 106205385876                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 209476019282                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103270633406                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 106205385876                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 209476019282                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1654613000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    981709000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636322000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1654613000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    981709000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636322000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086664                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.087945                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087306                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086664                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.087945                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.087306                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086664                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.087945                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.087306                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12767.935013                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12895.192520                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12832.139723                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12767.935013                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12895.192520                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12832.139723                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12767.935013                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12895.192520                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12832.139723                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127700.316431                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127693.678460                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127697.844514                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127700.316431                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127693.678460                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127697.844514                       # average overall mshr uncacheable latency
+system.cpu1.branchPred.lookups              132207984                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         88587172                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5826495                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            89257950                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               60608223                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            87.501505                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16925953                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            188094                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        4924647                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           2613751                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         2310896                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       404882                       # Number of mispredicted indirect branches.
+system.cpu1.branchPred.BTBHitPct            67.902325                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17136106                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            189382                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4973679                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2647071                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         2326608                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       405619                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1395,87 +1380,94 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   918796                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               918796                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17982                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92529                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       574433                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       344363                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2764.463662                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 16303.117040                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       341501     99.17%     99.17% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1458      0.42%     99.59% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          968      0.28%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          172      0.05%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679          169      0.05%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           19      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           30      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287           39      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       344363                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       435626                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23794.009081                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 19218.933550                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 19692.719928                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       425832     97.75%     97.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7550      1.73%     99.48% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1569      0.36%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          124      0.03%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          287      0.07%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215          141      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           90      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823           14      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       435626                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 784789358776                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.079913                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.520502                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 783688095276     99.86%     99.86% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    587470000      0.07%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    214780500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    128162000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     51938500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     36138500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     30357500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     44039000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      7811000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       500500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        27000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        17000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51        22000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 784789358776                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        92530     83.73%     83.73% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        17982     16.27%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       110512                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       918796                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   905143                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               905143                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17108                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91252                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       560527                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       344616                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2714.976960                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 16407.674532                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       341711     99.16%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1475      0.43%     99.59% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607         1008      0.29%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          155      0.04%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679          168      0.05%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           28      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           24      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287           38      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::655360-720895            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       344616                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       422123                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23405.519244                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.136881                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 20434.088485                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       412646     97.75%     97.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         6891      1.63%     99.39% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1818      0.43%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          156      0.04%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          358      0.08%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          124      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           77      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           40      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::786432-851967            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       422123                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 367737970920                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.152186                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.727251                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 366665366920     99.71%     99.71% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    581252000      0.16%     99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    209708000      0.06%     99.92% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    124789500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     48258000      0.01%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     27968500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     30956000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     41073500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      7796500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       589000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43       122000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47        17500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51        21000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::52-55         3000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::56-59         5000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::60-63        44500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 367737970920                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        91252     84.21%     84.21% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17108     15.79%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       108360                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       905143                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       918796                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       110512                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       905143                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       108360                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       110512                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total      1029308                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       108360                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total      1013503                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   308677787                       # DTB read hits
-system.cpu1.dtb.read_misses                    638033                       # DTB read misses
-system.cpu1.dtb.write_hits                   79810213                       # DTB write hits
-system.cpu1.dtb.write_misses                   280763                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1558                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   104254499                       # DTB read hits
+system.cpu1.dtb.read_misses                    630275                       # DTB read misses
+system.cpu1.dtb.write_hits                   80849259                       # DTB write hits
+system.cpu1.dtb.write_misses                   274868                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1096                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              20842                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   54702                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      194                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8626                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              20902                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   53828                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      197                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  9278                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    52744                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               309315820                       # DTB read accesses
-system.cpu1.dtb.write_accesses               80090976                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    53866                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               104884774                       # DTB read accesses
+system.cpu1.dtb.write_accesses               81124127                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        388488000                       # DTB hits
-system.cpu1.dtb.misses                         918796                       # DTB misses
-system.cpu1.dtb.accesses                    389406796                       # DTB accesses
+system.cpu1.dtb.hits                        185103758                       # DTB hits
+system.cpu1.dtb.misses                         905143                       # DTB misses
+system.cpu1.dtb.accesses                    186008901                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1505,382 +1497,387 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                   101960                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               101960                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3266                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68775                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14205                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        87755                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1682.627770                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 11960.911223                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535        87281     99.46%     99.46% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071          225      0.26%     99.72% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607          206      0.23%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143           30      0.03%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        87755                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        86246                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 29588.885282                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24514.620158                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 24839.457997                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        84146     97.57%     97.57% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          550      0.64%     98.20% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1295      1.50%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           86      0.10%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679          109      0.13%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           30      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::720896-786431            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        86246                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 630168052620                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.901316                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.298682                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    62259907956      9.88%      9.88% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   567845557664     90.11%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       54142000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        7434500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         754500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5         241500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::6          14500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 630168052620                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        68775     95.47%     95.47% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         3266      4.53%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        72041                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                   101154                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               101154                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3005                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68686                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        14200                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        86954                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1608.292890                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 11331.097997                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        85986     98.89%     98.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          520      0.60%     99.48% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303           66      0.08%     99.56% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071          164      0.19%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839          145      0.17%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           40      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375           11      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        86954                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        85891                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29748.012015                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24412.003991                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 25999.467191                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        83578     97.31%     97.31% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          495      0.58%     97.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1521      1.77%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           97      0.11%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679          134      0.16%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           37      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           24      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        85891                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 612540191292                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.893340                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.309134                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    65404482540     10.68%     10.68% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   547076306252     89.31%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       50127000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        7455500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4        1506000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          91500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::6         196000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::7          26500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 612540191292                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        68686     95.81%     95.81% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         3005      4.19%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        71691                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       101960                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       101960                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       101154                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       101154                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72041                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72041                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       174001                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   298391001                       # ITB inst hits
-system.cpu1.itb.inst_misses                    101960                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71691                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71691                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       172845                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    93866720                       # ITB inst hits
+system.cpu1.itb.inst_misses                    101154                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1558                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1096                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              20842                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   40396                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              20902                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   39904                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   187550                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   187991                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               298492961                       # ITB inst accesses
-system.cpu1.itb.hits                        298391001                       # DTB hits
-system.cpu1.itb.misses                         101960                       # DTB misses
-system.cpu1.itb.accesses                    298492961                       # DTB accesses
-system.cpu1.numCycles                      1146540967                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                93967874                       # ITB inst accesses
+system.cpu1.itb.hits                         93866720                       # DTB hits
+system.cpu1.itb.misses                         101154                       # DTB misses
+system.cpu1.itb.accesses                     93967874                       # DTB accesses
+system.cpu1.numCycles                       688149644                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         449143632                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                    1300356824                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  439037695                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches         284964072                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    654346336                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13178215                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2532163                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               23392                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             4389                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      4759392                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       175720                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         3551                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                298182140                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3594914                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  39494                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples        1117577293                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.251423                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.109409                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         246774526                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     586387121                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  132207984                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          80391400                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    398002232                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13247809                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2526813                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               23208                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             3339                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      4746787                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       172822                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         4142                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 93657492                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3619612                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  39280                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         658877500                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.040777                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.297556                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               718189985     64.26%     64.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               120476918     10.78%     75.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                17851977      1.60%     76.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13155756      1.18%     77.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4               181640077     16.25%     94.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 8775776      0.79%     94.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9591150      0.86%     95.71% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8236988      0.74%     96.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                39658666      3.55%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               514943270     78.15%     78.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                17992448      2.73%     80.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                17938734      2.72%     83.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13188969      2.00%     85.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                27941093      4.24%     89.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 8949077      1.36%     91.21% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9653002      1.47%     92.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8287474      1.26%     93.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39983433      6.07%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total          1117577293                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.382924                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.134156                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               403258788                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            335088582                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                360694363                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13294705                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5232856                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            70476298                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1375606                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts            1352424044                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4253100                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5232856                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               410740551                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               28469825                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     258278982                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                366370165                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             48476952                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts            1337170119                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents               127982                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1950398                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1918017                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              29294510                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3829                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands         1310108256                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups           1925124078                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups      1396779335                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           887250                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps           1214507358                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                95600893                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          14870121                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      12952577                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 74043380                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           305276022                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           83874418                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13450040                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14282158                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                1304947133                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           14993052                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued               1304763464                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           862160                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       81029622                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     50869342                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        350473                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples   1117577293                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.167493                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.494205                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           658877500                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.192121                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.852122                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               200321379                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            334897766                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                105062974                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13347316                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5245962                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19411078                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1397694                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             639286066                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4311897                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5245962                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               207822387                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               28109229                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     259552504                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                110777742                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             47367249                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             624073748                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents               113090                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1957012                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1963484                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              28046902                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            3748                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          596057640                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            957465344                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       735885626                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           888832                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            500042308                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                96015332                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          14940728                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      12988345                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 74317967                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           100818071                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           84975729                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13584844                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14513721                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 591824868                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15016632                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                591532545                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           864332                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       81511621                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     51286616                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        358770                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    658877500                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.897788                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.636922                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          477542007     42.73%     42.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          353173077     31.60%     74.33% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           93863937      8.40%     82.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           81886889      7.33%     90.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           73787788      6.60%     96.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           15804378      1.41%     98.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           10888709      0.97%     99.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6347514      0.57%     99.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4282994      0.38%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          427630752     64.90%     64.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           97159571     14.75%     79.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           42910564      6.51%     86.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           30776221      4.67%     90.83% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           22686133      3.44%     94.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           15935700      2.42%     96.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           10990898      1.67%     98.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6446525      0.98%     99.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4341136      0.66%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total     1117577293                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      658877500                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                2956708     25.80%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 26444      0.23%     26.03% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   3429      0.03%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.06% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4659115     40.65%     66.71% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3815684     33.29%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                2999770     25.98%     25.98% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 25009      0.22%     26.19% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   3249      0.03%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4684166     40.56%     66.79% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3835188     33.21%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               86      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            911406413     69.85%     69.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1450716      0.11%     69.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                68809      0.01%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                242      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                  16      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             14      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         74568      0.01%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           310913309     23.83%     93.80% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           80849259      6.20%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            401605558     67.89%     67.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1412010      0.24%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                67658      0.01%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                191      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             14      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         72305      0.01%     68.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           106483903     18.00%     86.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           81890872     13.84%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total            1304763464                       # Type of FU issued
-system.cpu1.iq.rate                          1.138000                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11461380                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.008784                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        3738310574                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes       1401077508                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses   1283063938                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1117187                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            574367                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       497584                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses            1315629411                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 595347                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4624780                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             591532545                       # Type of FU issued
+system.cpu1.iq.rate                          0.859599                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11547382                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019521                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1853248239                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        688458824                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    569767413                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1106065                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            569050                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       490960                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             602490208                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 589717                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4719123                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     16729306                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        20042                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       692952                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      8476645                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     16759885                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        20137                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       685641                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      8616382                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3812143                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      7452647                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3886436                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      7425204                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5232856                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               16688704                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              9539057                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts         1320087759                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1712091                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            305276022                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            83874418                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12664409                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                233480                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              9218245                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        692952                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2475150                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2684103                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             5159253                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts           1297880089                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            308665532                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          5977092                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5245962                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               16637308                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              9398313                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          606988228                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1717377                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            100818071                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            84975729                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12705052                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                239734                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              9069380                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        685641                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2485685                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2694157                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             5179842                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            584642052                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            104243442                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5998727                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       147574                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   388478968                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               415337436                       # Number of branches executed
-system.cpu1.iew.exec_stores                  79813436                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.131996                       # Inst execution rate
-system.cpu1.iew.wb_sent                    1284971111                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                   1283561522                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                586897530                       # num instructions producing a value
-system.cpu1.iew.wb_consumers               1100487939                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      1.119508                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.533307                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       81091096                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14642579                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4433138                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples   1103802352                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.122403                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.555476                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       146728                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   185095226                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               108396618                       # Number of branches executed
+system.cpu1.iew.exec_stores                  80851784                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.849586                       # Inst execution rate
+system.cpu1.iew.wb_sent                     571674985                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    570258373                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                281283764                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                489058083                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.828684                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575154                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       81573069                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14657862                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4448279                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    645042111                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.814412                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.812297                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    502258397     45.50%     45.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    299485709     27.13%     72.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2    134986499     12.23%     84.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3    117786431     10.67%     95.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10837119      0.98%     96.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6401807      0.58%     97.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5917729      0.54%     97.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3800615      0.34%     97.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22328046      2.02%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    452426770     70.14%     70.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     94787874     14.69%     84.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     32819397      5.09%     89.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15329214      2.38%     92.30% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10832611      1.68%     93.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6451723      1.00%     94.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5988175      0.93%     95.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3853316      0.60%     96.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22553031      3.50%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total   1103802352                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts          1161548854                       # Number of instructions committed
-system.cpu1.commit.committedOps            1238910558                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    645042111                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           446955239                       # Number of instructions committed
+system.cpu1.commit.committedOps             525329879                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     363944488                       # Number of memory references committed
-system.cpu1.commit.loads                    288546715                       # Number of loads committed
-system.cpu1.commit.membars                    3671917                       # Number of memory barriers committed
-system.cpu1.commit.branches                 406943707                       # Number of branches committed
-system.cpu1.commit.fp_insts                    477645                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts               1042234207                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13083843                       # Number of function calls committed.
+system.cpu1.commit.refs                     160417533                       # Number of memory references committed
+system.cpu1.commit.loads                     84058186                       # Number of loads committed
+system.cpu1.commit.membars                    3661350                       # Number of memory barriers committed
+system.cpu1.commit.branches                  99963573                       # Number of branches committed
+system.cpu1.commit.fp_insts                    470740                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                482339888                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13268232                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       873720787     70.52%     70.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1128470      0.09%     70.61% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           51728      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        65043      0.01%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead      288546715     23.29%     93.91% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      75397773      6.09%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       363697714     69.23%     69.23% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1101230      0.21%     69.44% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           50710      0.01%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        62650      0.01%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       84058186     16.00%     85.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      76359347     14.54%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total       1238910558                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22328046                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  2397538789                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 2653800851                       # The number of ROB writes
-system.cpu1.timesIdled                        4140984                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       28963674                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 48004396286                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                 1161548854                       # Number of Instructions Simulated
-system.cpu1.committedOps                   1238910558                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              0.987079                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.987079                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.013090                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.013090                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads              1349751752                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              814694732                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   925132                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  580436                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                432060294                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               433189790                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             2477616684                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14758914                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40289                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40289                       # Transaction distribution
+system.cpu1.commit.op_class_0::total        525329879                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22553031                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1225507013                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1227667180                       # The number of ROB writes
+system.cpu1.timesIdled                        4198522                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       29272144                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 46970319294                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  446955239                       # Number of Instructions Simulated
+system.cpu1.committedOps                    525329879                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.539639                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.539639                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.649503                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.649503                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               688608688                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              407764370                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   881042                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  529972                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                124702473                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               125859602                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1202737772                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              14790646                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40305                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40305                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1897,11 +1894,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230936                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230936                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230968                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230968                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353720                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353752                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1916,24 +1913,24 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334304                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334304                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492096                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             47809000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             47810500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               351500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               348000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
@@ -1941,75 +1938,75 @@ system.iobus.reqLayer15.occupancy                9500                       # La
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25705000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25726500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            40136000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            40136500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           566925706                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           566999378                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147696000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147728000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115449                       # number of replacements
-system.iocache.tags.tagsinuse               10.471056                       # Cycle average of tags in use
+system.iocache.tags.replacements               115465                       # number of replacements
+system.iocache.tags.tagsinuse               10.419655                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115465                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13096638509000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.513940                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.957116                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219621                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.434820                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.654441                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13096612113000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.546608                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.873047                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221663                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429565                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651228                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039569                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039569                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039713                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039713                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8804                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8841                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8820                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8857                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8804                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8844                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115484                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115524                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8804                       # number of overall misses
-system.iocache.overall_misses::total             8844                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1671055077                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1676125077                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115484                       # number of overall misses
+system.iocache.overall_misses::total           115524                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1649759369                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1654845369                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13413972629                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13413972629                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1671055077                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1676476077                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1671055077                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1676476077                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13415597009                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13415597009                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15065356378                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15070793378                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15065356378                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15070793378                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8804                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8841                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8820                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8857                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8804                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8844                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115484                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115524                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8804                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8844                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115484                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115524                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2023,55 +2020,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 189806.346774                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 189585.462844                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 187047.547506                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 186840.393926                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125759.137375                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125759.137375                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 189806.346774                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 189560.840909                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 189806.346774                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 189560.840909                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34335                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125774.366319                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125774.366319                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130454.057514                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130455.951820                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130454.057514                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130455.951820                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         33085                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3424                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3398                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.027745                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.736610                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8804                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8841                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8820                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8857                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8804                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8844                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115484                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115524                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8804                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8844                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1230855077                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1234075077                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115484                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115524                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1208759369                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1211995369                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8075705812                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8075705812                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1230855077                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1234276077                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1230855077                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1234276077                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8077336951                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8077336951                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9286096320                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9289533320                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9286096320                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9289533320                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2085,607 +2080,589 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139806.346774                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 139585.462844                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137047.547506                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 136840.393926                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75711.634778                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75711.634778                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 139806.346774                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 139560.840909                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 139806.346774                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 139560.840909                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1328339                       # number of replacements
-system.l2c.tags.tagsinuse                65287.407442                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   50375413                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1391222                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    36.209471                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               4319218500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35575.639274                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   158.468154                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   240.943849                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3221.018830                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11891.666425                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   181.118375                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   261.193191                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3949.386858                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9807.972486                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.542841                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002418                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003677                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.049149                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.181452                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002764                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003985                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.060263                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.149658                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996207                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        62518                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          365                       # Occupied blocks per task id
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75726.927089                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75726.927089                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80410.241419                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80412.150895                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80410.241419                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80412.150895                       # average overall mshr miss latency
+system.l2c.tags.replacements                  1347841                       # number of replacements
+system.l2c.tags.tagsinuse                65324.740261                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   50311393                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1410817                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    35.661176                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               4298396500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   35245.257795                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   161.370291                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   265.309574                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3415.837838                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    12035.721839                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   188.618634                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   273.886836                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3763.840034                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     9974.897420                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_task_id_blocks::1024        62599                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          377                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          534                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2786                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5034                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54062                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005569                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.953949                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                446176670                       # Number of tag accesses
-system.l2c.tags.data_accesses               446176670                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       522071                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       180522                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       538718                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       182834                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1424145                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      8078087                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         8078087                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     16333029                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        16333029                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            5039                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            4982                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               10021                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data             4                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             1                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 5                       # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu1.data           782344                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1596932                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       8166281                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       8076794                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          16243075                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3501095                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::total          6900602                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       361869                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       365570                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           727439                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        522071                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu0.data             4315683                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.inst             8076794                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                26164754                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       522071                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       180522                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            8166281                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4315683                       # number of overall hits
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-system.l2c.overall_hits::total               26164754                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         2382                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2080                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2398                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2211                       # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu0.data         18406                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         17899                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             36305                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         260481                       # number of ReadExReq misses
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-system.l2c.ReadCleanReq_misses::cpu0.inst        43082                       # number of ReadCleanReq misses
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-system.l2c.ReadCleanReq_misses::total           93859                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       146082                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       148220                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         294302                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       208426                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       295532                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         503958                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2382                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu0.inst             43082                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            406563                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.inst             50777                       # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu1.data           408151                       # number of overall misses
-system.l2c.overall_misses::total               917644                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    328467000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    287802500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    333096500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    309339500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1258705500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    720994000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    707940000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   1428934000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data        81000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data        79500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu1.data  39326078500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  78586646500                       # number of ReadExReq miss cycles
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-system.l2c.ReadCleanReq_miss_latency::cpu1.inst   6880458998                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total  12714532498                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  20593358000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  20805919500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  41399277500                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data      4602500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data      4134500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total      8737000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    328467000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    287802500                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu1.dtb.walker    333096500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    309339500                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::total    133959161998                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    328467000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    287802500                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu0.data  59853926000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    333096500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    309339500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   6880458998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  60131998000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   133959161998                       # number of overall miss cycles
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-system.l2c.WritebackDirty_accesses::total      8078087                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.WritebackClean_accesses::total     16333029                       # number of WritebackClean accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data        22881                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           46326                       # number of UpgradeReq accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::total             7                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu0.data      3647177                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.InvalidateReq_accesses::cpu0.data       570295                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       661102                       # number of InvalidateReq accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004542                       # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004432                       # miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.785071                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782265                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.783685                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.200000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.500000                       # miss rate for SCUpgradeReq accesses
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+system.l2c.tags.occ_task_id_percent::1024     0.955185                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                445845701                       # Number of tag accesses
+system.l2c.tags.data_accesses               445845701                       # Number of data accesses
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+system.l2c.InvalidateReq_miss_latency::cpu1.data      4832000                       # number of InvalidateReq miss cycles
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+system.l2c.WritebackDirty_accesses::writebacks      8064911                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      8064911                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks     16319354                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total     16319354                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        23791                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        22707                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           46498                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            7                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data            7                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            14                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data      1063232                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data      1051663                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          2114895                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      8087950                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      8235576                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      16323526                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      3630697                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data      3561990                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      7192687                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       609340                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       622453                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1231793                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       524589                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       184470                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         8087950                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         4693929                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker       534889                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker       181648                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         8235576                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         4613653                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            27056704                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       524589                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       184470                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        8087950                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        4693929                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker       534889                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker       181648                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        8235576                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        4613653                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           27056704                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004529                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011248                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004822                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.006620                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.780968                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784736                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.782808                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.571429                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total     0.285714                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.242292                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.249388                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.245785                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005248                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006248                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005745                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.040053                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.041779                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.040904                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.365471                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.447029                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.409257                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004542                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.011391                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005248                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.086095                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004432                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.011948                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.006248                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.088922                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.033883                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004542                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.011391                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005248                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.086095                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004432                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.011948                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.006248                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.088922                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.033883                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 137895.465995                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138366.586538                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138905.963303                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 139909.317051                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 138761.492669                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39171.683147                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39551.930275                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 39359.151632                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 150723.346424                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 151294.299256                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 151008.521133                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135417.889142                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135503.456250                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 135464.180292                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140971.221643                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140371.876265                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 140669.371938                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    22.082178                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data    13.990025                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total    17.336762                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137895.465995                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138366.586538                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 135417.889142                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 147219.314104                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138905.963303                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139909.317051                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 135503.456250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 147327.822301                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 145981.624680                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137895.465995                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138366.586538                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 135417.889142                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 147219.314104                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138905.963303                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139909.317051                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 135503.456250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 147327.822301                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 145981.624680                       # average overall miss latency
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.246062                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.250402                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.248220                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005255                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006247                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005756                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.043505                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.041200                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.042363                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.406087                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.419053                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.412639                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004529                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.011248                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.005255                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.089386                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004822                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.006247                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.088887                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.034485                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004529                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.011248                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.005255                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.089386                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004822                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.006247                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.088887                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.034485                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 137222.011785                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 136091.807229                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138087.243117                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138758.098007                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 137601.875397                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39286.894510                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39351.085920                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 39318.319185                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79125                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        79125                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 150872.569480                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 150602.856405                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 150737.271863                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135196.668470                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135865.017201                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 135562.668966                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141857.713103                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139653.051003                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 140795.889166                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    20.216614                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data    18.524695                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total    19.348359                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137222.011785                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136091.807229                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 135196.668470                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 147478.846351                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138087.243117                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138758.098007                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 135865.017201                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 146684.382567                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 145829.864810                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137222.011785                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136091.807229                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 135196.668470                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 147478.846351                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138087.243117                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138758.098007                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 135865.017201                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 146684.382567                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 145829.864810                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1125321                       # number of writebacks
-system.l2c.writebacks::total                  1125321                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker            9                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks             1136735                       # number of writebacks
+system.l2c.writebacks::total                  1136735                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker            7                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           22                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           32                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                67                       # number of ReadReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            6                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           23                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                58                       # number of ReadReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            6                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           16                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           11                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           11                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker            9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu0.itb.walker           22                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.itb.walker           32                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 90                       # number of demand (read+write) MSHR hits
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+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  18172131000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  35515442500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    301340001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    259502000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   5321175594                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  57680784346                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    329367513                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    307643002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   6475806664                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  56051158480                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 126726777600                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    301340001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    259502000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   5321175594                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  57680784346                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    329367513                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    307643002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   6475806664                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  56051158480                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 126726777600                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1453779500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2881358000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    862532000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2928681000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8126350500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1453779500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2881358000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    862532000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2928681000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   8126350500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004516                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011129                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004810                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.013130                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.006580                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.785071                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.782265                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.783685                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.200000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.780968                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784736                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.782808                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.571429                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.285714                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.242292                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.249388                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.245785                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005248                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.246062                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.250402                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.248220                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005255                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006247                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005745                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.040052                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041774                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.040901                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.365471                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.447029                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.409257                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004525                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011270                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005248                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.086094                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004424                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011776                       # mshr miss rate for demand accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005756                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.043502                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041197                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042360                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.406087                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.419053                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.412639                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004516                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011129                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005255                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.089384                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004810                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013130                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006247                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.088918                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.033880                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004525                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011270                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005248                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.086094                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004424                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011776                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.088884                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034482                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004516                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011129                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005255                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.089384                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004810                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013130                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006247                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.088918                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.033880                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 128879.999000                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67979.680539                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67988.211632                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67983.886517                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140721.444954                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 141292.125137                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 141006.483482                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125416.464742                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125504.325705                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125463.996420                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130971.517217                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130372.589977                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130669.888113                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69959.052613                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69837.873733                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69887.990666                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125416.464742                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137218.294242                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125504.325705                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137326.969517                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 135982.444677                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125416.464742                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137218.294242                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125504.325705                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137326.969517                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 135982.444677                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172331.931018                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172494.599858                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149535.171451                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180743.451613                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165735.226164                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172636.480895                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 176373.674747                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168993.385810                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 158378.395521                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54348                       # Transaction distribution
-system.membus.trans_dist::ReadResp             460331                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33708                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1231951                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           210742                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            37070                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.088884                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034482                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 127702.826866                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67993.299247                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68001.150457                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67997.142779                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        69125                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69125                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140871.038586                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140600.346714                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 140735.249970                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125198.239942                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125863.572409                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125562.592552                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131859.126889                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129652.622097                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130796.418389                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70089.561317                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69667.464087                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69872.950465                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125198.239942                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137478.571334                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125863.572409                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136682.806073                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 135830.548449                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125198.239942                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137478.571334                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125863.572409                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136682.806073                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 135830.548449                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112200.316431                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170980.180394                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112191.987513                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174056.876263                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149593.183366                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112200.316431                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 88578.130284                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112191.987513                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84048.816186                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 92324.958248                       # average overall mshr uncacheable latency
+system.membus.trans_dist::ReadReq               54323                       # Transaction distribution
+system.membus.trans_dist::ReadResp             471198                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1243365                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           218846                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            37171                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            519762                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           519762                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        405983                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        610510                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            524316                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           524316                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        416875                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        614824                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6930                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3747708                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3877418                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237430                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237430                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4114848                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3802484                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3932122                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237507                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237507                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4169629                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13860                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    132000044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    132171886                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7238592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7238592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               139410478                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3037                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3104114                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    133717932                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    133889630                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7241472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7241472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               141131102                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3009                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3143476                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3104114    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3143476    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3104114                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           114095000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3143476                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           114116000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5418502                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5372500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8237516188                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8328651016                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5046734585                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5128575160                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44568865                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44638442                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2702,11 +2679,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -2739,64 +2716,64 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     54620375                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     27739287                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         4920                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2097                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2097                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     54578445                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     27714706                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         5543                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2124                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2124                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            2026549                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25559589                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33708                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33708                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      9310073                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     16336648                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2676872                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           46329                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          46336                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2117344                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2117344                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      16337404                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7203745                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1338061                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1231397                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     49052277                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31858634                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       875155                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2530262                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              84316328                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2092430528                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1113218798                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2941176                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8524552                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3217115054                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2099522                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         30547038                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.026857                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.161665                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2026220                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25543991                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33696                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33696                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      9308329                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     16323462                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2693882                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           46501                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            14                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          46515                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2114895                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2114895                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      16324325                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7201544                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1338457                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1231793                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     49012603                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31846136                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       876413                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2521080                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              84256232                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2090728512                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1112078430                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2928944                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8475824                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3214211710                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2126745                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         30549096                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.026641                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.161031                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               29726637     97.31%     97.31% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 820401      2.69%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               29735242     97.34%     97.34% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 813854      2.66%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           30547038                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        52365395385                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           30549096                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        52321567856                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1392915                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1445388                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24553415616                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       24533352992                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14664140678                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       14657364738                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         507934109                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         510704141                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1467755168                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1464609307                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16352                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   16351                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index 8a6768cf2..ab74bea7e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.799232                       # Nu
 sim_ticks                                51799232151500                       # Number of ticks simulated
 final_tick                               51799232151500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1085172                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1275227                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            67259328222                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 678040                       # Number of bytes of host memory used
-host_seconds                                   770.14                       # Real time elapsed on the host
+host_inst_rate                                 780767                       # Simulator instruction rate (inst/s)
+host_op_rate                                   917508                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48392163425                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 677024                       # Number of bytes of host memory used
+host_seconds                                  1070.41                       # Real time elapsed on the host
 sim_insts                                   835736802                       # Number of instructions simulated
 sim_ops                                     982105580                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -647,12 +647,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total      3330034
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1801503                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1811825                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      3613328                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    141219995                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    141634455                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       282854450                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    141408447                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    141819876                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      283228323                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data    141394196                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    141792419                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       283186615                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    141582648                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    141977840                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      283560488                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      2455322                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::cpu1.data      2424347                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      4879669                       # number of ReadReq misses
@@ -671,12 +671,12 @@ system.cpu0.dcache.LoadLockedReq_misses::total       284928
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3466251                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      3403542                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6869793                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4046045                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      3952170                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      7998215                       # number of overall misses
+system.cpu0.dcache.demand_misses::cpu0.data      4082188                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      4008411                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       8090599                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4661982                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      4557039                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      9219021                       # number of overall misses
 system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42484250000                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  41555213000                       # number of ReadReq miss cycles
 system.cpu0.dcache.ReadReq_miss_latency::total  84039463000                       # number of ReadReq miss cycles
@@ -692,12 +692,12 @@ system.cpu0.dcache.LoadLockedReq_miss_latency::total   4389496000
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        80000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        82000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total       162000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  76911781000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  76394250500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 153306031500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  76911781000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  76394250500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 153306031500                       # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 101008852500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 100491798500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 201500651000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 101008852500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 100491798500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 201500651000                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     76020372                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu1.data     76099561                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total    152119933                       # number of ReadReq accesses(hits+misses)
@@ -716,12 +716,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total      3614962
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1801504                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1811826                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total      3613330                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    144686246                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    145037997                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    289724243                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    145454492                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    145772046                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    291226538                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data    145476384                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    145800830                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    291277214                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    146244630                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    146534879                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    292779509                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032298                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031858                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.032078                       # miss rate for ReadReq accesses
@@ -740,12 +740,12 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.078819
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023957                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023467                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.023711                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027817                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027112                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.027464                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028061                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.027492                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.027776                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031878                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.031099                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.031488                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17302.924016                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17140.785952                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total 17222.369591                       # average ReadReq miss latency
@@ -761,20 +761,18 @@ system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15405.632300
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        80000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        81000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22188.751190                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22445.514261                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 22315.960830                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19009.126443                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19329.697483                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19167.530693                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24743.802221                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25070.233192                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 24905.529368                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21666.504182                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22051.994398                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21857.055212                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      7311510                       # number of writebacks
 system.cpu0.dcache.writebacks::total          7311510                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        10741                       # number of ReadReq MSHR hits
@@ -810,12 +808,12 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::total       216981
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3445673                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3381196                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      6826869                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4024602                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      3928918                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      7953520                       # number of overall MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4061610                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3986065                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      8047675                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4640539                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4533787                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9174326                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17141                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16563                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33704                       # number of ReadReq MSHR uncacheable
@@ -843,21 +841,18 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2986892000
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        79000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        81000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       160000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  72358790500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  71851840000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 144210630500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  83070723000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  82359591500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 165430314500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  95839925000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  95344519000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 191184444000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106551857500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 105852270500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 212404128000                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3180599500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3018965000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6199564500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3329040000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2888636500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6217676500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6509639500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5907601500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12417241000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3180599500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3018965000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6199564500                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032157                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031714                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031935                       # mshr miss rate for ReadReq accesses
@@ -876,12 +871,12 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060023
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023815                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023312                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023563                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027669                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026952                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.027310                       # mshr miss rate for overall accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027919                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.027339                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027629                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031731                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.030940                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031335                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.940424                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15946.282062                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16033.164972                       # average ReadReq mshr miss latency
@@ -900,22 +895,18 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13765.684553
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        79000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        80000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20999.900600                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21250.421449                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21123.977990                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20640.729941                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20962.410389                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20799.635193                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23596.535610                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23919.459166                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23756.481717                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22961.095144                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23347.429092                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23152.014437                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185555.072633                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182271.629536                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183941.505459                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182713.501647                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 186495.997159                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184451.526299                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184090.933514                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184313.038188                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184196.534793                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89946.537145                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94189.598153                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91963.931289                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements         13311280                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.820918                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          822940675                       # Total number of references to valid blocks.
@@ -995,8 +986,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks     13311280                       # number of writebacks
 system.cpu0.icache.writebacks::total         13311280                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6677414                       # number of ReadReq MSHR misses
@@ -1053,7 +1042,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1393,11 +1381,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8853                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8893                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115517                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115557                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8853                       # number of overall misses
-system.iocache.overall_misses::total             8893                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115517                       # number of overall misses
+system.iocache.overall_misses::total           115557                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1618419141                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1623489641                       # number of ReadReq miss cycles
@@ -1406,11 +1394,11 @@ system.iocache.WriteReq_miss_latency::total       351000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13411968510                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13411968510                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1618419141                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1623840641                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15030387651                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15035809151                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1618419141                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1623840641                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15030387651                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15035809151                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8853                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8890                       # number of ReadReq accesses(hits+misses)
@@ -1419,11 +1407,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8853                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8893                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115517                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115557                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8853                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8893                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115517                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115557                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1445,19 +1433,17 @@ system.iocache.WriteReq_avg_miss_latency::total       117000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125740.348290                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125740.348290                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 182810.249746                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 182597.620713                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130114.075426                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130115.952742                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 182810.249746                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 182597.620713                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130114.075426                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130115.952742                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         31642                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3353                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.436922                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -1468,11 +1454,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8853                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8893                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115517                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115557                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8853                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8893                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115517                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115557                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1175769141                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1178989641                       # number of ReadReq MSHR miss cycles
@@ -1481,11 +1467,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       201000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8073599158                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8073599158                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1175769141                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1179190641                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9249368299                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9252789799                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1175769141                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1179190641                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9249368299                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9252789799                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1507,12 +1493,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        67000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.884403                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.884403                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 132810.249746                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 132597.620713                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80069.325718                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80071.218524                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 132810.249746                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 132597.620713                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80069.325718                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80071.218524                       # average overall mshr miss latency
 system.l2c.tags.replacements                  1026360                       # number of replacements
 system.l2c.tags.tagsinuse                65258.201118                       # Cycle average of tags in use
 system.l2c.tags.total_refs                   41749797                       # Total number of references to valid blocks.
@@ -1807,8 +1792,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              872147                       # number of writebacks
 system.l2c.writebacks::total                   872147                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1170                       # number of ReadReq MSHR misses
@@ -1911,14 +1894,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2965958000
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   2392920500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2811531000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total  10675226000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3119505500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2710506500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5830012000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2504816500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6085463500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2965958000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   2392920500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5522037500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  16505238000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2811531000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10675226000                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005479                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.007656                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.005703                       # mshr miss rate for ReadReq accesses
@@ -2006,15 +1986,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173032.961904
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169747.690636                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138947.871247                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171213.254665                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174995.577507                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172951.199976                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172095.345154                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83876.530641                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172283.710845                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 149317.320740                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87717.802321                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 96575.168720                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               76829                       # Transaction distribution
 system.membus.trans_dist::ReadResp             386652                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33709                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index b4b530730..63eb8fdf2 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.230834                       # Nu
 sim_ticks                                5230834315000                       # Number of ticks simulated
 final_tick                               5230834315000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192642                       # Simulator instruction rate (inst/s)
-host_op_rate                                   380808                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2470040631                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 757076                       # Number of bytes of host memory used
-host_seconds                                  2117.71                       # Real time elapsed on the host
+host_inst_rate                                 185450                       # Simulator instruction rate (inst/s)
+host_op_rate                                   366593                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2377836678                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 757080                       # Number of bytes of host memory used
+host_seconds                                  2199.83                       # Real time elapsed on the host
 sim_insts                                   407959263                       # Number of instructions simulated
 sim_ops                                     806441023                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -698,8 +698,6 @@ system.cpu.dcache.blocked::no_mshrs             52278                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.131681                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    96.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1592887                       # number of writebacks
 system.cpu.dcache.writebacks::total           1592887                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       868287                       # number of ReadReq MSHR hits
@@ -738,10 +736,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40574906244
 system.cpu.dcache.overall_mshr_miss_latency::total  40574906244                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98117221000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98117221000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2788550500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2788550500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  98117221000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  98117221000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.067459                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.067459                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034152                       # mshr miss rate for WriteReq accesses
@@ -764,11 +760,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404                       # average overall mshr uncacheable latency
 system.cpu.dtb_walker_cache.tags.replacements       148390                       # number of replacements
 system.cpu.dtb_walker_cache.tags.tagsinuse    15.865349                       # Cycle average of tags in use
 system.cpu.dtb_walker_cache.tags.total_refs       319136                       # Total number of references to valid blocks.
@@ -827,8 +820,6 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs            0
 system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.dtb_walker_cache.writebacks::writebacks        35466                       # number of writebacks
 system.cpu.dtb_walker_cache.writebacks::total        35466                       # number of writebacks
 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       149314                       # number of ReadReq MSHR misses
@@ -855,7 +846,6 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.5
 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1273398                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.770567                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            11313989                       # Total number of references to valid blocks.
@@ -915,8 +905,6 @@ system.cpu.icache.blocked::no_mshrs               591                       # nu
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    17.786802                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets   233.333333                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1273398                       # number of writebacks
 system.cpu.icache.writebacks::total           1273398                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst       169776                       # number of ReadReq MSHR hits
@@ -949,7 +937,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803
 system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements        15042                       # number of replacements
 system.cpu.itb_walker_cache.tags.tagsinuse     8.049036                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs        49432                       # Total number of references to valid blocks.
@@ -1013,8 +1000,6 @@ system.cpu.itb_walker_cache.blocked::no_mshrs            0
 system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.itb_walker_cache.writebacks::writebacks         3121                       # number of writebacks
 system.cpu.itb_walker_cache.writebacks::total         3121                       # number of writebacks
 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        15914                       # number of ReadReq MSHR misses
@@ -1041,7 +1026,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.3
 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           108236                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        64755.938748                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            5712490                       # Total number of references to valid blocks.
@@ -1202,8 +1186,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        98548                       # number of writebacks
 system.cpu.l2cache.writebacks::total            98548                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
@@ -1266,10 +1248,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19839963508
 system.cpu.l2cache.overall_mshr_miss_latency::total  21832221513                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90948626000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90948626000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2627781000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2627781000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  93576407000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  93576407000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  90948626000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  90948626000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.815016                       # mshr miss rate for UpgradeReq accesses
@@ -1314,11 +1294,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      6286174                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      3130505                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests       100234                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1491,26 +1468,26 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide          907
 system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          907                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               907                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          907                       # number of overall misses
-system.iocache.overall_misses::total              907                       # number of overall misses
+system.iocache.demand_misses::pc.south_bridge.ide        47627                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47627                       # number of overall misses
+system.iocache.overall_misses::total            47627                       # number of overall misses
 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    150838200                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total    150838200                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5868267118                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   5868267118                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    150838200                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    150838200                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    150838200                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    150838200                       # number of overall miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   6019105318                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   6019105318                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   6019105318                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   6019105318                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          907                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          907                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             907                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          907                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            907                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47627                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47627                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1523,36 +1500,34 @@ system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397
 system.iocache.ReadReq_avg_miss_latency::total 166304.520397                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 166304.520397                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 166304.520397                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126380.106200                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126380.106200                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs           266                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   20                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs    13.300000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          907                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          907                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          907                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          907                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          907                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          907                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47627                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47627                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47627                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47627                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    105488200                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total    105488200                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3530357439                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3530357439                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    105488200                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    105488200                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    105488200                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    105488200                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3635845639                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3635845639                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3635845639                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3635845639                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1565,11 +1540,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397
 system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 116304.520397                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 116304.520397                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76340.009637                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76340.009637                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq              573476                       # Transaction distribution
 system.membus.trans_dist::ReadResp             628544                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13974                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 8ec2ac6a9..d05c61c9b 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.140315                       # Nu
 sim_ticks                                5140314861500                       # Number of ticks simulated
 final_tick                               5140314861500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 305571                       # Simulator instruction rate (inst/s)
-host_op_rate                                   607445                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6465827182                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 946272                       # Number of bytes of host memory used
-host_seconds                                   795.00                       # Real time elapsed on the host
+host_inst_rate                                 305956                       # Simulator instruction rate (inst/s)
+host_op_rate                                   608211                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6473981728                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 946268                       # Number of bytes of host memory used
+host_seconds                                   794.00                       # Real time elapsed on the host
 sim_insts                                   242927760                       # Number of instructions simulated
 sim_ops                                     482917054                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -526,8 +526,6 @@ system.cpu0.dcache.blocked::no_mshrs            19401                       # nu
 system.cpu0.dcache.blocked::no_targets              1                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.330550                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          183                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks      1556926                       # number of writebacks
 system.cpu0.dcache.writebacks::total          1556926                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           57                       # number of ReadReq MSHR hits
@@ -584,12 +582,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total  20480553918
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30576787000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32909630500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63486417500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    482381000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    622576500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1104957500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31059168000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33532207000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64591375000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30576787000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  32909630500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  63486417500                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.068076                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.074921                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041660                       # mshr miss rate for ReadReq accesses
@@ -623,13 +618,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21368.366823
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173837.429574                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170281.531671                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171975.808527                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 207475.698925                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 195655.719673                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200645.996005                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174276.268390                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170692.534411                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172397.215120                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171569.577708                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 167523.367507                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 169448.035050                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements           963636                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          510.754232                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          132561753                       # Total number of references to valid blocks.
@@ -723,8 +714,6 @@ system.cpu0.icache.blocked::no_mshrs              445                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.685393                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks       963636                       # number of writebacks
 system.cpu0.icache.writebacks::total           963636                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        59693                       # number of ReadReq MSHR hits
@@ -769,7 +758,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 13438.749848
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13025.550415                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13583.792891                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::total 13438.749848                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                      2608018193                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -1247,26 +1235,26 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide          902
 system.iocache.ReadReq_misses::total              902                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          902                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               902                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          902                       # number of overall misses
-system.iocache.overall_misses::total              902                       # number of overall misses
+system.iocache.demand_misses::pc.south_bridge.ide        47622                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47622                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47622                       # number of overall misses
+system.iocache.overall_misses::total            47622                       # number of overall misses
 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126421308                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total    126421308                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3306334979                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   3306334979                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    126421308                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    126421308                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    126421308                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    126421308                       # number of overall miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   3432756287                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   3432756287                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   3432756287                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   3432756287                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          902                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            902                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          902                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             902                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          902                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            902                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47622                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47622                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47622                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47622                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1279,53 +1267,50 @@ system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 140156.660754
 system.iocache.ReadReq_avg_miss_latency::total 140156.660754                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70769.156229                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 70769.156229                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 140156.660754                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 140156.660754                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 140156.660754                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 140156.660754                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 72083.412855                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 72083.412855                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 72083.412855                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 72083.412855                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs           266                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   20                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs    13.300000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          739                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          739                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        26320                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        26320                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          739                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          739                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          739                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          739                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        27059                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        27059                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        27059                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        27059                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     89471308                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     89471308                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1989257405                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   1989257405                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     89471308                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     89471308                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     89471308                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     89471308                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   2078728713                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2078728713                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   2078728713                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2078728713                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.819290                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.819290                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.563356                       # mshr miss rate for WriteLineReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::total     0.563356                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.819290                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.819290                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.819290                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.819290                       # mshr miss rate for overall accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.568204                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.568204                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.568204                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.568204                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 121070.782138                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75579.688640                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.688640                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 121070.782138                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 121070.782138                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76822.081858                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76822.081858                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76822.081858                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76822.081858                       # average overall mshr miss latency
 system.l2c.tags.replacements                   102044                       # number of replacements
 system.l2c.tags.tagsinuse                64688.139772                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4947315                       # Total number of references to valid blocks.
@@ -1602,8 +1587,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               93953                       # number of writebacks
 system.l2c.writebacks::total                    93953                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            2                       # number of ReadCleanReq MSHR hits
@@ -1676,12 +1659,9 @@ system.l2c.overall_mshr_miss_latency::total   9728021512                       #
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28378124000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30493776000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total  58871900000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    455643500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    585976500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1041620000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28833767500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31079752500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  59913520000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28378124000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30493776000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  58871900000                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000371                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.829091                       # mshr miss rate for UpgradeReq accesses
@@ -1737,13 +1717,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 120088.652981
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161337.426731                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157781.379032                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159475.727261                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 195975.698925                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184153.519799                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189144.724896                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161789.311405                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158208.546282                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 159911.814790                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159232.647656                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 155225.688223                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 157131.685288                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq             5063720                       # Transaction distribution
 system.membus.trans_dist::ReadResp            5112994                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13943                       # Transaction distribution
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index baaf2995a..5afa63b46 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.061235                       # Nu
 sim_ticks                                 61234797500                       # Number of ticks simulated
 final_tick                                61234797500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 274685                       # Simulator instruction rate (inst/s)
-host_op_rate                                   276053                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              185648704                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 404860                       # Number of bytes of host memory used
-host_seconds                                   329.84                       # Real time elapsed on the host
+host_inst_rate                                 283902                       # Simulator instruction rate (inst/s)
+host_op_rate                                   285316                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              191877896                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404856                       # Number of bytes of host memory used
+host_seconds                                   319.13                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -513,8 +513,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       943278                       # number of writebacks
 system.cpu.dcache.writebacks::total            943278                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11500                       # number of ReadReq MSHR hits
@@ -565,7 +563,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 5                       # number of replacements
 system.cpu.icache.tags.tagsinuse           689.102041                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            27766889                       # Total number of references to valid blocks.
@@ -625,8 +622,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            5                       # number of writebacks
 system.cpu.icache.writebacks::total                 5                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          801                       # number of ReadReq MSHR misses
@@ -653,7 +648,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236
 system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        10244.686315                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1833993                       # Total number of references to valid blocks.
@@ -762,8 +756,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            6                       # number of ReadSharedReq MSHR hits
@@ -822,7 +814,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1897096                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       946118                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          150                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index fd8ec81c4..98d82899d 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.058199                       # Nu
 sim_ticks                                 58199030500                       # Number of ticks simulated
 final_tick                                58199030500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 158181                       # Simulator instruction rate (inst/s)
-host_op_rate                                   158969                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              101622775                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 491528                       # Number of bytes of host memory used
-host_seconds                                   572.70                       # Real time elapsed on the host
+host_inst_rate                                 149103                       # Simulator instruction rate (inst/s)
+host_op_rate                                   149846                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               95790656                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 491524                       # Number of bytes of host memory used
+host_seconds                                   607.56                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -786,8 +786,6 @@ system.cpu.dcache.blocked::no_mshrs            121409                       # nu
 system.cpu.dcache.blocked::no_targets           12838                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717385                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     8.479903                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      5470634                       # number of writebacks
 system.cpu.dcache.writebacks::total           5470634                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4338603                       # number of ReadReq MSHR hits
@@ -840,7 +838,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8329.949445
 system.cpu.dcache.demand_avg_mshr_miss_latency::total  8329.949445                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8329.982560                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total  8329.982560                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements               447                       # number of replacements
 system.cpu.icache.tags.tagsinuse           427.448157                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            32273898                       # Total number of references to valid blocks.
@@ -900,8 +897,6 @@ system.cpu.icache.blocked::no_mshrs               219                       # nu
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    86.543379                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    21.400000                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks          447                       # number of writebacks
 system.cpu.icache.writebacks::total               447                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          240                       # number of ReadReq MSHR hits
@@ -934,7 +929,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044
 system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued      4981065                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified      5296247                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit       274020                       # number of redundant prefetches already in prefetch queue
@@ -1063,8 +1057,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches                7                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks          175                       # number of writebacks
 system.cpu.l2cache.writebacks::total              175                       # number of writebacks
@@ -1148,7 +1140,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2697.430895                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3118.582380                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     10943135                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      5471097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 4cc0ff469..c28c5f296 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.361598                       # Nu
 sim_ticks                                361597758500                       # Number of ticks simulated
 final_tick                               361597758500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1193747                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1193796                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1770350920                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 429888                       # Number of bytes of host memory used
-host_seconds                                   204.25                       # Real time elapsed on the host
+host_inst_rate                                1238958                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1239009                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1837400352                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 383872                       # Number of bytes of host memory used
+host_seconds                                   196.80                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -172,8 +172,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       935266                       # number of writebacks
 system.cpu.dcache.writebacks::total            935266                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       892857                       # number of ReadReq MSHR misses
@@ -216,7 +214,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                25                       # number of replacements
 system.cpu.icache.tags.tagsinuse           725.404879                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           244420617                       # Total number of references to valid blocks.
@@ -276,8 +273,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           25                       # number of writebacks
 system.cpu.icache.writebacks::total                25                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          882                       # number of ReadReq MSHR misses
@@ -304,7 +299,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         9729.320449                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1813523                       # Total number of references to valid blocks.
@@ -413,8 +407,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14567                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14567                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          879                       # number of ReadCleanReq MSHR misses
@@ -463,7 +455,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1875953                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       935500                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index d813cd17b..ae7b853ff 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.065987                       # Nu
 sim_ticks                                 65986743500                       # Number of ticks simulated
 final_tick                                65986743500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 126294                       # Simulator instruction rate (inst/s)
-host_op_rate                                   222383                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52748930                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 126228                       # Simulator instruction rate (inst/s)
+host_op_rate                                   222267                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52721316                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 414760                       # Number of bytes of host memory used
-host_seconds                                  1250.96                       # Real time elapsed on the host
+host_seconds                                  1251.61                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -652,8 +652,6 @@ system.cpu.dcache.blocked::no_mshrs             43207                       # nu
 system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.073298                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   124.250000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2066969                       # number of writebacks
 system.cpu.dcache.writebacks::total           2066969                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       698217                       # number of ReadReq MSHR hits
@@ -696,7 +694,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                93                       # number of replacements
 system.cpu.icache.tags.tagsinuse           870.928206                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            29996478                       # Total number of references to valid blocks.
@@ -757,8 +754,6 @@ system.cpu.icache.blocked::no_mshrs                11                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    46.818182                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           93                       # number of writebacks
 system.cpu.icache.writebacks::total                93                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          332                       # number of ReadReq MSHR hits
@@ -791,7 +786,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707
 system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements              650                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        20606.403574                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4037654                       # Total number of references to valid blocks.
@@ -900,8 +894,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks          280                       # number of writebacks
 system.cpu.l2cache.writebacks::total              280                       # number of writebacks
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28982                       # number of ReadExReq MSHR misses
@@ -952,7 +944,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      4152318                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073604                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests           20                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index ff948a783..e4dba065e 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.366199                       # Nu
 sim_ticks                                366199170500                       # Number of ticks simulated
 final_tick                               366199170500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 639917                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1126791                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1483253517                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 455604                       # Number of bytes of host memory used
-host_seconds                                   246.89                       # Real time elapsed on the host
+host_inst_rate                                 703769                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1239225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1631255376                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410416                       # Number of bytes of host memory used
+host_seconds                                   224.49                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -170,8 +170,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2062482                       # number of writebacks
 system.cpu.dcache.writebacks::total           2062482                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1960720                       # number of ReadReq MSHR misses
@@ -206,7 +204,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                24                       # number of replacements
 system.cpu.icache.tags.tagsinuse           665.627299                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           217695356                       # Total number of references to valid blocks.
@@ -265,8 +262,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           24                       # number of writebacks
 system.cpu.icache.writebacks::total                24                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
@@ -293,7 +288,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements              313                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        20037.622351                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3992697                       # Total number of references to valid blocks.
@@ -402,8 +396,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks          102                       # number of writebacks
 system.cpu.l2cache.writebacks::total              102                       # number of writebacks
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29024                       # number of ReadExReq MSHR misses
@@ -454,7 +446,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      4130394                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2062757                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index fcf7ab908..7e8fb1ca2 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.412080                       # Nu
 sim_ticks                                412079966500                       # Number of ticks simulated
 final_tick                               412079966500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 374495                       # Simulator instruction rate (inst/s)
-host_op_rate                                   374495                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              252200387                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254932                       # Number of bytes of host memory used
-host_seconds                                  1633.94                       # Real time elapsed on the host
+host_inst_rate                                 367276                       # Simulator instruction rate (inst/s)
+host_op_rate                                   367276                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              247338871                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254928                       # Number of bytes of host memory used
+host_seconds                                  1666.05                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -446,8 +446,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2339413                       # number of writebacks
 system.cpu.dcache.writebacks::total           2339413                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143957                       # number of ReadReq MSHR hits
@@ -490,7 +488,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              3158                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1117.678366                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           226045682                       # Total number of references to valid blocks.
@@ -551,8 +548,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         3158                       # number of writebacks
 system.cpu.icache.writebacks::total              3158                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4986                       # number of ReadReq MSHR misses
@@ -579,7 +574,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318
 system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           347705                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29504.977164                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3908748                       # Total number of references to valid blocks.
@@ -688,8 +682,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       293607                       # number of writebacks
 system.cpu.l2cache.writebacks::total           293607                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            5                       # number of CleanEvict MSHR misses
@@ -744,7 +736,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5082776                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538426                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 6a1fec128..78ceda494 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.362632                       # Nu
 sim_ticks                                362631828500                       # Number of ticks simulated
 final_tick                               362631828500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 285981                       # Simulator instruction rate (inst/s)
-host_op_rate                                   309756                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              204718125                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275016                       # Number of bytes of host memory used
-host_seconds                                  1771.37                       # Real time elapsed on the host
+host_inst_rate                                 263885                       # Simulator instruction rate (inst/s)
+host_op_rate                                   285822                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188900227                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275012                       # Number of bytes of host memory used
+host_seconds                                  1919.70                       # Real time elapsed on the host
 sim_insts                                   506579366                       # Number of instructions simulated
 sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -550,8 +550,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1069336                       # number of writebacks
 system.cpu.dcache.writebacks::total           1069336                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66650                       # number of ReadReq MSHR hits
@@ -602,7 +600,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             18130                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1186.413401                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           198770599                       # Total number of references to valid blocks.
@@ -663,8 +660,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        18130                       # number of writebacks
 system.cpu.icache.writebacks::total             18130                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20001                       # number of ReadReq MSHR misses
@@ -691,7 +686,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461
 system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           112376                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        27628.930561                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1772118                       # Total number of references to valid blocks.
@@ -800,8 +794,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        97210                       # number of writebacks
 system.cpu.l2cache.writebacks::total            97210                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
@@ -862,7 +854,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      2325181                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 1b2646d9c..8dfa33132 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.232865                       # Nu
 sim_ticks                                232864525000                       # Number of ticks simulated
 final_tick                               232864525000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 164421                       # Simulator instruction rate (inst/s)
-host_op_rate                                   178126                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               75782118                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300244                       # Number of bytes of host memory used
-host_seconds                                  3072.82                       # Real time elapsed on the host
+host_inst_rate                                 163970                       # Simulator instruction rate (inst/s)
+host_op_rate                                   177638                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75574513                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300240                       # Number of bytes of host memory used
+host_seconds                                  3081.26                       # Real time elapsed on the host
 sim_insts                                   505234934                       # Number of instructions simulated
 sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -807,8 +807,6 @@ system.cpu.dcache.blocked::no_mshrs                 5                       # nu
 system.cpu.dcache.blocked::no_targets          221191                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.200000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     4.144201                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2817145                       # number of writebacks
 system.cpu.dcache.writebacks::total           2817145                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2539309                       # number of ReadReq MSHR hits
@@ -861,7 +859,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             76528                       # number of replacements
 system.cpu.icache.tags.tagsinuse           466.435319                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           235186472                       # Total number of references to valid blocks.
@@ -922,8 +919,6 @@ system.cpu.icache.blocked::no_mshrs              6762                       # nu
 system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    23.889382                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    60.333333                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        76528                       # number of writebacks
 system.cpu.icache.writebacks::total             76528                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7901                       # number of ReadReq MSHR hits
@@ -956,7 +951,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793
 system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued      8513492                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified      8514887                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit          402                       # number of redundant prefetches already in prefetch queue
@@ -1087,8 +1081,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches             1977                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks       292354                       # number of writebacks
 system.cpu.l2cache.writebacks::total           292354                       # number of writebacks
@@ -1172,7 +1164,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5788431                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2893715                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23913                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 0a916209d..84569a240 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.708539                       # Nu
 sim_ticks                                708539449500                       # Number of ticks simulated
 final_tick                               708539449500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 318121                       # Simulator instruction rate (inst/s)
-host_op_rate                                   344511                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              446353500                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303968                       # Number of bytes of host memory used
-host_seconds                                  1587.40                       # Real time elapsed on the host
+host_inst_rate                                 973862                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1054649                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1366418821                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273224                       # Number of bytes of host memory used
+host_seconds                                   518.54                       # Real time elapsed on the host
 sim_insts                                   504984064                       # Number of instructions simulated
 sim_ops                                     546875315                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1065708                       # number of writebacks
 system.cpu.dcache.writebacks::total           1065708                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       783863                       # number of ReadReq MSHR misses
@@ -346,7 +344,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9788                       # number of replacements
 system.cpu.icache.tags.tagsinuse           983.198764                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           516597066                       # Total number of references to valid blocks.
@@ -407,8 +404,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         9788                       # number of writebacks
 system.cpu.icache.writebacks::total              9788                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11521                       # number of ReadReq MSHR misses
@@ -435,7 +430,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907
 system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           110394                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        27252.086651                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1747015                       # Total number of references to valid blocks.
@@ -543,8 +537,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        96330                       # number of writebacks
 system.cpu.l2cache.writebacks::total            96330                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
@@ -599,7 +591,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      2297957                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      1146116                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3565                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 139608a38..644125e9d 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.481958                       # Nu
 sim_ticks                                481957625500                       # Number of ticks simulated
 final_tick                               481957625500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 104668                       # Simulator instruction rate (inst/s)
-host_op_rate                                   193689                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61009723                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318640                       # Number of bytes of host memory used
-host_seconds                                  7899.69                       # Real time elapsed on the host
+host_inst_rate                                 100765                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186466                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               58734658                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318636                       # Number of bytes of host memory used
+host_seconds                                  8205.68                       # Real time elapsed on the host
 sim_insts                                   826847303                       # Number of instructions simulated
 sim_ops                                    1530082520                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -665,8 +665,6 @@ system.cpu.dcache.blocked::no_mshrs               875                       # nu
 system.cpu.dcache.blocked::no_targets              14                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.746286                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    92.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2337968                       # number of writebacks
 system.cpu.dcache.writebacks::total           2337968                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       800154                       # number of ReadReq MSHR hits
@@ -709,7 +707,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              4014                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1083.903563                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           216343916                       # Total number of references to valid blocks.
@@ -770,8 +767,6 @@ system.cpu.icache.blocked::no_mshrs                 8                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    43.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         4014                       # number of writebacks
 system.cpu.icache.writebacks::total              4014                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2282                       # number of ReadReq MSHR hits
@@ -804,7 +799,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890
 system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           355161                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29604.694298                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3909300                       # Total number of references to valid blocks.
@@ -925,8 +919,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       294920                       # number of writebacks
 system.cpu.l2cache.writebacks::total           294920                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            9                       # number of CleanEvict MSHR misses
@@ -989,7 +981,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5109049                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2551690                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         8246                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index aee130b35..e69329d5f 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.650501                       # Nu
 sim_ticks                                1650501252500                       # Number of ticks simulated
 final_tick                               1650501252500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 239314                       # Simulator instruction rate (inst/s)
-host_op_rate                                   442851                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              477703969                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314168                       # Number of bytes of host memory used
-host_seconds                                  3455.07                       # Real time elapsed on the host
+host_inst_rate                                 691787                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1280153                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1380901785                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282548                       # Number of bytes of host memory used
+host_seconds                                  1195.23                       # Real time elapsed on the host
 sim_insts                                   826847304                       # Number of instructions simulated
 sim_ops                                    1530082521                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -171,8 +171,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2325221                       # number of writebacks
 system.cpu.dcache.writebacks::total           2325221                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1729742                       # number of ReadReq MSHR misses
@@ -207,7 +205,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           881.361687                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1068307822                       # Total number of references to valid blocks.
@@ -268,8 +265,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         1253                       # number of writebacks
 system.cpu.icache.writebacks::total              1253                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
@@ -296,7 +291,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713
 system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           348438                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29288.734166                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3851952                       # Total number of references to valid blocks.
@@ -404,8 +398,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       293208                       # number of writebacks
 system.cpu.l2cache.writebacks::total           293208                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            6                       # number of CleanEvict MSHR misses
@@ -460,7 +452,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5042195                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2518269                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 19e47bc98..2db84b627 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.223533                       # Nu
 sim_ticks                                223532962500                       # Number of ticks simulated
 final_tick                               223532962500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 354404                       # Simulator instruction rate (inst/s)
-host_op_rate                                   354404                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              198715635                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258580                       # Number of bytes of host memory used
-host_seconds                                  1124.89                       # Real time elapsed on the host
+host_inst_rate                                 349202                       # Simulator instruction rate (inst/s)
+host_op_rate                                   349202                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              195799110                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258576                       # Number of bytes of host memory used
+host_seconds                                  1141.64                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -415,8 +415,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          654                       # number of writebacks
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          214                       # number of ReadReq MSHR hits
@@ -459,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              3190                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1919.630000                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            96785699                       # Total number of references to valid blocks.
@@ -519,8 +516,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         3190                       # number of writebacks
 system.cpu.icache.writebacks::total              3190                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5168                       # number of ReadReq MSHR misses
@@ -547,7 +542,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         4421.902302                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               4798                       # Total number of references to valid blocks.
@@ -655,8 +649,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3137                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3137                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3892                       # number of ReadCleanReq MSHR misses
@@ -705,7 +697,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        13294                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         3961                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index f3497559e..8e400ff51 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.064189                       # Nu
 sim_ticks                                 64188759000                       # Number of ticks simulated
 final_tick                                64188759000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 286389                       # Simulator instruction rate (inst/s)
-host_op_rate                                   286389                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48946118                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 306108                       # Simulator instruction rate (inst/s)
+host_op_rate                                   306108                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52316361                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 260628                       # Number of bytes of host memory used
-host_seconds                                  1311.42                       # Real time elapsed on the host
+host_seconds                                  1226.93                       # Real time elapsed on the host
 sim_insts                                   375574794                       # Number of instructions simulated
 sim_ops                                     375574794                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -666,8 +666,6 @@ system.cpu.dcache.blocked::no_mshrs               740                       # nu
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    68.367568                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets           80                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          655                       # number of writebacks
 system.cpu.dcache.writebacks::total               655                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          838                       # number of ReadReq MSHR hits
@@ -710,7 +708,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2132                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1831.246133                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            46954666                       # Total number of references to valid blocks.
@@ -770,8 +767,6 @@ system.cpu.icache.blocked::no_mshrs                 8                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs           62                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         2132                       # number of writebacks
 system.cpu.icache.writebacks::total              2132                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1585                       # number of ReadReq MSHR hits
@@ -804,7 +799,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384
 system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         4001.708243                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               3078                       # Total number of references to valid blocks.
@@ -912,8 +906,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3128                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3128                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3450                       # number of ReadCleanReq MSHR misses
@@ -962,7 +954,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        11144                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         2908                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 8253a646b..f6de01eb6 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.567385                       # Nu
 sim_ticks                                567385356500                       # Number of ticks simulated
 final_tick                               567385356500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1390819                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1390819                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1979434182                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302276                       # Number of bytes of host memory used
-host_seconds                                   286.64                       # Real time elapsed on the host
+host_inst_rate                                1272231                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1272231                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1810657439                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257040                       # Number of bytes of host memory used
+host_seconds                                   313.36                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -193,8 +193,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          649                       # number of writebacks
 system.cpu.dcache.writebacks::total               649                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          950                       # number of ReadReq MSHR misses
@@ -229,7 +227,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1769                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1795.084430                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           398660993                       # Total number of references to valid blocks.
@@ -290,8 +287,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         1769                       # number of writebacks
 system.cpu.icache.writebacks::total              1769                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3673                       # number of ReadReq MSHR misses
@@ -318,7 +313,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630
 system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         3772.330397                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               2561                       # Total number of references to valid blocks.
@@ -427,8 +421,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3142                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3142                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3205                       # number of ReadCleanReq MSHR misses
@@ -477,7 +469,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        10358                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         2533                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 078507389..5c8f8115d 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.211715                       # Nu
 sim_ticks                                211714953000                       # Number of ticks simulated
 final_tick                               211714953000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192926                       # Simulator instruction rate (inst/s)
-host_op_rate                                   231629                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              149595583                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280180                       # Number of bytes of host memory used
-host_seconds                                  1415.25                       # Real time elapsed on the host
+host_inst_rate                                 196459                       # Simulator instruction rate (inst/s)
+host_op_rate                                   235871                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              152335465                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280176                       # Number of bytes of host memory used
+host_seconds                                  1389.79                       # Real time elapsed on the host
 sim_insts                                   273037857                       # Number of instructions simulated
 sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -515,8 +515,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks         1010                       # number of writebacks
 system.cpu.dcache.writebacks::total              1010                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          421                       # number of ReadReq MSHR hits
@@ -567,7 +565,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             38168                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1923.744161                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            69641436                       # Total number of references to valid blocks.
@@ -628,8 +625,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        38168                       # number of writebacks
 system.cpu.icache.writebacks::total             38168                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        40105                       # number of ReadReq MSHR misses
@@ -656,7 +651,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314
 system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         4199.701287                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              60529                       # Total number of references to valid blocks.
@@ -765,8 +759,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           42                       # number of ReadSharedReq MSHR hits
@@ -825,7 +817,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        84140                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        39625                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15034                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 297ece098..319cdc8ce 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.111754                       # Nu
 sim_ticks                                111753553500                       # Number of ticks simulated
 final_tick                               111753553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152363                       # Simulator instruction rate (inst/s)
-host_op_rate                                   182928                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               62361670                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292096                       # Number of bytes of host memory used
-host_seconds                                  1792.02                       # Real time elapsed on the host
+host_inst_rate                                 153930                       # Simulator instruction rate (inst/s)
+host_op_rate                                   184810                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63003104                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292088                       # Number of bytes of host memory used
+host_seconds                                  1773.78                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -771,8 +771,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets          136770                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     7.892725                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1542955                       # number of writebacks
 system.cpu.dcache.writebacks::total           1542955                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1460236                       # number of ReadReq MSHR hits
@@ -825,7 +823,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            726201                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.803602                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            81470529                       # Total number of references to valid blocks.
@@ -886,8 +883,6 @@ system.cpu.icache.blocked::no_mshrs              3051                       # nu
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    21.069813                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    31.333333                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       726201                       # number of writebacks
 system.cpu.icache.writebacks::total            726201                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         6071                       # number of ReadReq MSHR hits
@@ -920,7 +915,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8406.318013
 system.cpu.icache.demand_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued       402434                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified       402547                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit          102                       # number of redundant prefetches already in prefetch queue
@@ -1052,8 +1046,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           51                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_hits::total           51                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           12                       # number of ReadCleanReq MSHR hits
@@ -1134,7 +1126,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3448.748330                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      4539362                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2269187                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254586                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index f4880fcc0..3e4b0cab1 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.517291                       # Nu
 sim_ticks                                517291025500                       # Number of ticks simulated
 final_tick                               517291025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 222408                       # Simulator instruction rate (inst/s)
-host_op_rate                                   267009                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              421830266                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307072                       # Number of bytes of host memory used
-host_seconds                                  1226.30                       # Real time elapsed on the host
+host_inst_rate                                 647052                       # Simulator instruction rate (inst/s)
+host_op_rate                                   776811                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1227232141                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277364                       # Number of bytes of host memory used
+host_seconds                                   421.51                       # Real time elapsed on the host
 sim_insts                                   272739286                       # Number of instructions simulated
 sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -295,8 +295,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          998                       # number of writebacks
 system.cpu.dcache.writebacks::total               998                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
@@ -345,7 +343,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13796                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1765.948116                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           348644750                       # Total number of references to valid blocks.
@@ -406,8 +403,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        13796                       # number of writebacks
 system.cpu.icache.writebacks::total             13796                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15603                       # number of ReadReq MSHR misses
@@ -434,7 +429,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048
 system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         3487.622109                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              19775                       # Total number of references to valid blocks.
@@ -543,8 +537,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2856                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         2856                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2608                       # number of ReadCleanReq MSHR misses
@@ -593,7 +585,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        35209                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        15221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7665                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index a78600dd4..7428b23f1 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.504258                       # Nu
 sim_ticks                                504258263000                       # Number of ticks simulated
 final_tick                               504258263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 397765                       # Simulator instruction rate (inst/s)
-host_op_rate                                   397765                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              215954385                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262596                       # Number of bytes of host memory used
-host_seconds                                  2335.02                       # Real time elapsed on the host
+host_inst_rate                                 386643                       # Simulator instruction rate (inst/s)
+host_op_rate                                   386643                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              209915985                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262852                       # Number of bytes of host memory used
+host_seconds                                  2402.19                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -443,8 +443,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        88489                       # number of writebacks
 system.cpu.dcache.writebacks::total             88489                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          314                       # number of ReadReq MSHR hits
@@ -487,7 +485,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             10567                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1686.158478                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           285751480                       # Total number of references to valid blocks.
@@ -548,8 +545,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        10567                       # number of writebacks
 system.cpu.icache.writebacks::total             10567                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12310                       # number of ReadReq MSHR misses
@@ -576,7 +571,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526
 system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           259940                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32579.649991                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1218214                       # Total number of references to valid blocks.
@@ -685,8 +679,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
@@ -741,7 +733,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1580033                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       787097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index f6b6cbb05..80519f72d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.174766                       # Nu
 sim_ticks                                174766258500                       # Number of ticks simulated
 final_tick                               174766258500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 293073                       # Simulator instruction rate (inst/s)
-host_op_rate                                   293073                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60802944                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 294264                       # Simulator instruction rate (inst/s)
+host_op_rate                                   294264                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61050004                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 263360                       # Number of bytes of host memory used
-host_seconds                                  2874.31                       # Real time elapsed on the host
+host_seconds                                  2862.67                       # Real time elapsed on the host
 sim_insts                                   842382029                       # Number of instructions simulated
 sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -692,8 +692,6 @@ system.cpu.dcache.blocked::no_mshrs               347                       # nu
 system.cpu.dcache.blocked::no_targets             519                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    64.360231                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   132.400771                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        88604                       # number of writebacks
 system.cpu.dcache.writebacks::total             88604                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842561                       # number of ReadReq MSHR hits
@@ -736,7 +734,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              4617                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1647.904441                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           116209358                       # Total number of references to valid blocks.
@@ -797,8 +794,6 @@ system.cpu.icache.blocked::no_mshrs                12                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    61.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         4617                       # number of writebacks
 system.cpu.icache.writebacks::total              4617                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1927                       # number of ReadReq MSHR hits
@@ -831,7 +826,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858
 system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           259794                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32576.626048                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1207042                       # Total number of references to valid blocks.
@@ -940,8 +934,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66682                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66682                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
@@ -996,7 +988,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1568372                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       781285                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 5e6b1a1be..fa790fe39 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.288319                       # Nu
 sim_ticks                                1288319411500                       # Number of ticks simulated
 final_tick                               1288319411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1465054                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1465054                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2032611527                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306300                       # Number of bytes of host memory used
-host_seconds                                   633.82                       # Real time elapsed on the host
+host_inst_rate                                1388114                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1388114                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1925865262                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260804                       # Number of bytes of host memory used
+host_seconds                                   668.96                       # Real time elapsed on the host
 sim_insts                                   928587629                       # Number of instructions simulated
 sim_ops                                     928587629                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,8 +200,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        88866                       # number of writebacks
 system.cpu.dcache.writebacks::total             88866                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711514                       # number of ReadReq MSHR misses
@@ -236,7 +234,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              4618                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1474.418872                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           928782983                       # Total number of references to valid blocks.
@@ -296,8 +293,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         4618                       # number of writebacks
 system.cpu.icache.writebacks::total              4618                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6168                       # number of ReadReq MSHR misses
@@ -324,7 +319,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995
 system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           258847                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32654.651136                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1207020                       # Total number of references to valid blocks.
@@ -433,8 +427,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
@@ -489,7 +481,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1567746                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       781050                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 35b8ed937..b04619cac 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.489946                       # Nu
 sim_ticks                                489945697500                       # Number of ticks simulated
 final_tick                               489945697500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 199747                       # Simulator instruction rate (inst/s)
-host_op_rate                                   245915                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              152758149                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280032                       # Number of bytes of host memory used
-host_seconds                                  3207.33                       # Real time elapsed on the host
+host_inst_rate                                 235921                       # Simulator instruction rate (inst/s)
+host_op_rate                                   290449                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              180421993                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280028                       # Number of bytes of host memory used
+host_seconds                                  2715.55                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -537,8 +537,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        88712                       # number of writebacks
 system.cpu.dcache.writebacks::total             88712                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          904                       # number of ReadReq MSHR hits
@@ -589,7 +587,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             24859                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1712.892625                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           252585994                       # Total number of references to valid blocks.
@@ -648,8 +645,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        24859                       # number of writebacks
 system.cpu.icache.writebacks::total             24859                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        26613                       # number of ReadReq MSHR misses
@@ -676,7 +671,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395
 system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           258808                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32560.749490                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1247790                       # Total number of references to valid blocks.
@@ -785,8 +779,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
@@ -847,7 +839,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1612172                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       803221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3314                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 4c772ec0f..2624c980a 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.326731                       # Nu
 sim_ticks                                326731324000                       # Number of ticks simulated
 final_tick                               326731324000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133673                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164569                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68173047                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277340                       # Number of bytes of host memory used
-host_seconds                                  4792.68                       # Real time elapsed on the host
+host_inst_rate                                 138534                       # Simulator instruction rate (inst/s)
+host_op_rate                                   170554                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               70652444                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277336                       # Number of bytes of host memory used
+host_seconds                                  4624.49                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -811,8 +811,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets            4812                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    73.103907                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2756452                       # number of writebacks
 system.cpu.dcache.writebacks::total           2756452                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       366436                       # number of ReadReq MSHR hits
@@ -865,7 +863,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1979880                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.626245                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           245759391                       # Total number of references to valid blocks.
@@ -925,8 +922,6 @@ system.cpu.icache.blocked::no_mshrs              2912                       # nu
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    25.917582                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           15                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1979880                       # number of writebacks
 system.cpu.icache.writebacks::total           1979880                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3014                       # number of ReadReq MSHR hits
@@ -959,7 +954,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7623.101721
 system.cpu.icache.demand_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued      1350865                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified      1355053                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit         3664                       # number of redundant prefetches already in prefetch queue
@@ -1084,8 +1078,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches             2695                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks        66334                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66334                       # number of writebacks
@@ -1169,7 +1161,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      9474058                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      4736544                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests       643707                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 92b150303..c2f10176e 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.045756                       # Nu
 sim_ticks                                1045756396500                       # Number of ticks simulated
 final_tick                               1045756396500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 725560                       # Simulator instruction rate (inst/s)
-host_op_rate                                   891395                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1186735876                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 325196                       # Number of bytes of host memory used
-host_seconds                                   881.20                       # Real time elapsed on the host
+host_inst_rate                                 744148                       # Simulator instruction rate (inst/s)
+host_op_rate                                   914231                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1217137628                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277972                       # Number of bytes of host memory used
+host_seconds                                   859.19                       # Real time elapsed on the host
 sim_insts                                   639366787                       # Number of instructions simulated
 sim_ops                                     785501035                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        88995                       # number of writebacks
 system.cpu.dcache.writebacks::total             88995                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
@@ -352,7 +350,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              8769                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1391.385132                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           643367692                       # Total number of references to valid blocks.
@@ -411,8 +408,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         8769                       # number of writebacks
 system.cpu.icache.writebacks::total              8769                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10208                       # number of ReadReq MSHR misses
@@ -439,7 +434,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878
 system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           257772                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32622.591915                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1218050                       # Total number of references to valid blocks.
@@ -548,8 +542,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
@@ -600,7 +592,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1579165                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       786845                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1110                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 7a3a9c70d..c69a77e9f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.059447                       # Nu
 sim_ticks                                 59447065000                       # Number of ticks simulated
 final_tick                                59447065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 412945                       # Simulator instruction rate (inst/s)
-host_op_rate                                   412945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              277576735                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261724                       # Number of bytes of host memory used
-host_seconds                                   214.16                       # Real time elapsed on the host
+host_inst_rate                                 371878                       # Simulator instruction rate (inst/s)
+host_op_rate                                   371878                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              249972170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261720                       # Number of bytes of host memory used
+host_seconds                                   237.81                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -442,8 +442,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168424                       # number of writebacks
 system.cpu.dcache.writebacks::total            168424                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28112                       # number of ReadReq MSHR hits
@@ -486,7 +484,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            152872                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1932.382407                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            25430610                       # Total number of references to valid blocks.
@@ -547,8 +544,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       152872                       # number of writebacks
 system.cpu.icache.writebacks::total            152872                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154921                       # number of ReadReq MSHR misses
@@ -575,7 +570,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334
 system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           133382                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30429.048447                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             403995                       # Total number of references to valid blocks.
@@ -684,8 +678,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114469                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114469                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          115                       # number of CleanEvict MSHR misses
@@ -740,7 +732,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       713421                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       353638                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 8a6383ef9..41c072959 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.022275                       # Nu
 sim_ticks                                 22275010500                       # Number of ticks simulated
 final_tick                                22275010500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 279038                       # Simulator instruction rate (inst/s)
-host_op_rate                                   279038                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               78093188                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 259704                       # Simulator instruction rate (inst/s)
+host_op_rate                                   259704                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               72682241                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 263768                       # Number of bytes of host memory used
-host_seconds                                   285.24                       # Real time elapsed on the host
+host_seconds                                   306.47                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -694,8 +694,6 @@ system.cpu.dcache.blocked::no_mshrs             89218                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.036921                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168806                       # number of writebacks
 system.cpu.dcache.writebacks::total            168806                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207108                       # number of ReadReq MSHR hits
@@ -738,7 +736,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             90292                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1916.963164                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            13622372                       # Total number of references to valid blocks.
@@ -799,8 +796,6 @@ system.cpu.icache.blocked::no_mshrs                12                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    47.750000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        90292                       # number of writebacks
 system.cpu.icache.writebacks::total             90292                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12531                       # number of ReadReq MSHR hits
@@ -833,7 +828,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897
 system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           133082                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30595.837110                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             280630                       # Total number of references to valid blocks.
@@ -942,8 +936,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114419                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114419                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          111                       # number of CleanEvict MSHR misses
@@ -998,7 +990,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       589565                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       291710                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index ec22c8c38..c5d95ec77 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.056803                       # Nu
 sim_ticks                                 56802974500                       # Number of ticks simulated
 final_tick                                56802974500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 208655                       # Simulator instruction rate (inst/s)
-host_op_rate                                   266840                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              167132713                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280072                       # Number of bytes of host memory used
-host_seconds                                   339.87                       # Real time elapsed on the host
+host_inst_rate                                 222036                       # Simulator instruction rate (inst/s)
+host_op_rate                                   283951                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              177850276                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280068                       # Number of bytes of host memory used
+host_seconds                                   319.39                       # Real time elapsed on the host
 sim_insts                                    70915150                       # Number of instructions simulated
 sim_ops                                      90690106                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -542,8 +542,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       128389                       # number of writebacks
 system.cpu.dcache.writebacks::total            128389                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22138                       # number of ReadReq MSHR hits
@@ -594,7 +592,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             43497                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1852.676989                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            24844377                       # Total number of references to valid blocks.
@@ -654,8 +651,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        43497                       # number of writebacks
 system.cpu.icache.writebacks::total             43497                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45540                       # number of ReadReq MSHR misses
@@ -682,7 +677,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144
 system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            96391                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29870.997301                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             163417                       # Total number of references to valid blocks.
@@ -791,8 +785,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        86215                       # number of writebacks
 system.cpu.l2cache.writebacks::total            86215                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
@@ -857,7 +849,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       406029                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       199980                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 5ae3909df..8db6a9814 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.033525                       # Nu
 sim_ticks                                 33524756000                       # Number of ticks simulated
 final_tick                                33524756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 145211                       # Simulator instruction rate (inst/s)
-host_op_rate                                   185708                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68655135                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 282260                       # Number of bytes of host memory used
-host_seconds                                   488.31                       # Real time elapsed on the host
+host_inst_rate                                 160372                       # Simulator instruction rate (inst/s)
+host_op_rate                                   205097                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75822829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282256                       # Number of bytes of host memory used
+host_seconds                                   442.15                       # Real time elapsed on the host
 sim_insts                                    70907652                       # Number of instructions simulated
 sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -796,8 +796,6 @@ system.cpu.dcache.blocked::no_mshrs                 6                       # nu
 system.cpu.dcache.blocked::no_targets          131418                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    22.123925                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       486293                       # number of writebacks
 system.cpu.dcache.writebacks::total            486293                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       267392                       # number of ReadReq MSHR hits
@@ -850,7 +848,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            325000                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.229072                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            22083387                       # Total number of references to valid blocks.
@@ -911,8 +908,6 @@ system.cpu.icache.blocked::no_mshrs             16495                       # nu
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    16.015580                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       325000                       # number of writebacks
 system.cpu.icache.writebacks::total            325000                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9178                       # number of ReadReq MSHR hits
@@ -945,7 +940,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037
 system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued       822902                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified       826054                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit         2760                       # number of redundant prefetches already in prefetch queue
@@ -1070,8 +1064,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches              424                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks        97140                       # number of writebacks
 system.cpu.l2cache.writebacks::total            97140                       # number of writebacks
@@ -1155,7 +1147,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1623643                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       811337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        80260                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index a0ce19406..cc971b1f8 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.208778                       # Nu
 sim_ticks                                1208777694500                       # Number of ticks simulated
 final_tick                               1208777694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 395749                       # Simulator instruction rate (inst/s)
-host_op_rate                                   395749                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              261924296                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 390102                       # Simulator instruction rate (inst/s)
+host_op_rate                                   390102                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              258186532                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 253640                       # Number of bytes of host memory used
-host_seconds                                  4614.99                       # Real time elapsed on the host
+host_seconds                                  4681.80                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -457,8 +457,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3686603                       # number of writebacks
 system.cpu.dcache.writebacks::total           3686603                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50808                       # number of ReadReq MSHR hits
@@ -501,7 +499,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
 system.cpu.icache.tags.tagsinuse           750.173547                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           597988654                       # Total number of references to valid blocks.
@@ -559,8 +556,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            3                       # number of writebacks
 system.cpu.icache.writebacks::total                 3                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
@@ -587,7 +582,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916
 system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1920891                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30765.315888                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14409692                       # Total number of references to valid blocks.
@@ -692,8 +686,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1022139                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1022139                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
@@ -748,7 +740,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18249005                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121977                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index f0b14c5aa..f667a67d9 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.669588                       # Nu
 sim_ticks                                669587683000                       # Number of ticks simulated
 final_tick                               669587683000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 206275                       # Simulator instruction rate (inst/s)
-host_op_rate                                   206275                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               79559671                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 207572                       # Simulator instruction rate (inst/s)
+host_op_rate                                   207572                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               80060022                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 254664                       # Number of bytes of host memory used
-host_seconds                                  8416.17                       # Real time elapsed on the host
+host_seconds                                  8363.57                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -730,8 +730,6 @@ system.cpu.dcache.blocked::no_mshrs           1104455                       # nu
 system.cpu.dcache.blocked::no_targets           68040                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.190667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   140.706805                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3727750                       # number of writebacks
 system.cpu.dcache.writebacks::total           3727750                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5562625                       # number of ReadReq MSHR hits
@@ -782,7 +780,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           753.790798                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           420611422                       # Total number of references to valid blocks.
@@ -841,8 +838,6 @@ system.cpu.icache.blocked::no_mshrs                 4                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    68.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.icache.writebacks::total                 1                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          540                       # number of ReadReq MSHR hits
@@ -875,7 +870,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782
 system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1929018                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        31408.626842                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14580161                       # Total number of references to valid blocks.
@@ -980,8 +974,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1024304                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1024304                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          240                       # number of CleanEvict MSHR misses
@@ -1036,7 +1028,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18419450                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207203                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 2fb4a6971..86be7ae28 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.636720                       # Nu
 sim_ticks                                2636719559500                       # Number of ticks simulated
 final_tick                               2636719559500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1488641                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1488641                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2156924734                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297352                       # Number of bytes of host memory used
-host_seconds                                  1222.44                       # Real time elapsed on the host
+host_inst_rate                                1392133                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1392132                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2017091448                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252104                       # Number of bytes of host memory used
+host_seconds                                  1307.19                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,8 +200,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3679426                       # number of writebacks
 system.cpu.dcache.writebacks::total           3679426                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222414                       # number of ReadReq MSHR misses
@@ -236,7 +234,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           612.605858                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1826377708                       # Total number of references to valid blocks.
@@ -295,8 +292,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.icache.writebacks::total                 1                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
@@ -323,7 +318,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339
 system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1919525                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30540.825713                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14380256                       # Total number of references to valid blocks.
@@ -428,8 +422,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1021962                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1021962                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
@@ -484,7 +476,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18220175                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9107639                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 0b0903e3c..80a1c9ff6 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.116866                       # Nu
 sim_ticks                                1116865668500                       # Number of ticks simulated
 final_tick                               1116865668500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 315195                       # Simulator instruction rate (inst/s)
-host_op_rate                                   339575                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              227915704                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 272300                       # Number of bytes of host memory used
-host_seconds                                  4900.35                       # Real time elapsed on the host
+host_inst_rate                                 304077                       # Simulator instruction rate (inst/s)
+host_op_rate                                   327597                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              219876370                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272296                       # Number of bytes of host memory used
+host_seconds                                  5079.52                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -548,8 +548,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3684567                       # number of writebacks
 system.cpu.dcache.writebacks::total           3684567                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          215                       # number of ReadReq MSHR hits
@@ -600,7 +598,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                29                       # number of replacements
 system.cpu.icache.tags.tagsinuse           660.385482                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           465281510                       # Total number of references to valid blocks.
@@ -659,8 +656,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           29                       # number of writebacks
 system.cpu.icache.writebacks::total                29                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          819                       # number of ReadReq MSHR misses
@@ -687,7 +682,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694
 system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          2013919                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        31258.258362                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14509191                       # Total number of references to valid blocks.
@@ -796,8 +790,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1050123                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1050123                       # number of writebacks
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            5                       # number of ReadSharedReq MSHR hits
@@ -858,7 +850,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18447026                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9221082                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index ad14d9d64..c43dbec03 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.767804                       # Nu
 sim_ticks                                767803843500                       # Number of ticks simulated
 final_tick                               767803843500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 188017                       # Simulator instruction rate (inst/s)
-host_op_rate                                   202560                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               93463451                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313392                       # Number of bytes of host memory used
-host_seconds                                  8215.02                       # Real time elapsed on the host
+host_inst_rate                                 224780                       # Simulator instruction rate (inst/s)
+host_op_rate                                   242166                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              111738196                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312364                       # Number of bytes of host memory used
+host_seconds                                  6871.45                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -809,8 +809,6 @@ system.cpu.dcache.blocked::no_mshrs            943594                       # nu
 system.cpu.dcache.blocked::no_targets           67194                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.757654                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    50.564678                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks     17003710                       # number of writebacks
 system.cpu.dcache.writebacks::total          17003710                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3151672                       # number of ReadReq MSHR hits
@@ -863,7 +861,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements               589                       # number of replacements
 system.cpu.icache.tags.tagsinuse           444.836642                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           656966815                       # Total number of references to valid blocks.
@@ -922,8 +919,6 @@ system.cpu.icache.blocked::no_mshrs               183                       # nu
 system.cpu.icache.blocked::no_targets               8                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    94.316940                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    54.875000                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks          589                       # number of writebacks
 system.cpu.icache.writebacks::total               589                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          544                       # number of ReadReq MSHR hits
@@ -956,7 +951,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825
 system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued     11611376                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified     11640224                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit        19566                       # number of redundant prefetches already in prefetch queue
@@ -1086,8 +1080,6 @@ system.cpu.l2cache.blocked::no_mshrs                1                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs           53                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches            56900                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks      1635896                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1635896                       # number of writebacks
@@ -1171,7 +1163,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     34009604                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     17004315                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 232fe8b45..af0dd5de2 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.377030                       # Nu
 sim_ticks                                2377029670500                       # Number of ticks simulated
 final_tick                               2377029670500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 872363                       # Simulator instruction rate (inst/s)
-host_op_rate                                   940093                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1347600333                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317216                       # Number of bytes of host memory used
-host_seconds                                  1763.90                       # Real time elapsed on the host
+host_inst_rate                                1034140                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1114431                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1597508455                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269992                       # Number of bytes of host memory used
+host_seconds                                  1487.96                       # Real time elapsed on the host
 sim_insts                                  1538759602                       # Number of instructions simulated
 sim_ops                                    1658228915                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -300,8 +300,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3681379                       # number of writebacks
 system.cpu.dcache.writebacks::total           3681379                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226086                       # number of ReadReq MSHR misses
@@ -344,7 +342,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 7                       # number of replacements
 system.cpu.icache.tags.tagsinuse           515.144337                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1544564953                       # Total number of references to valid blocks.
@@ -403,8 +400,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            7                       # number of writebacks
 system.cpu.icache.writebacks::total                 7                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                       # number of ReadReq MSHR misses
@@ -431,7 +426,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511
 system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1919027                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        31012.105366                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14386231                       # Total number of references to valid blocks.
@@ -540,8 +534,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1021127                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1021127                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          219                       # number of CleanEvict MSHR misses
@@ -596,7 +588,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18227021                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9111154                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1151                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index d16f022eb..aea63bd4a 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.895948                       # Nu
 sim_ticks                                5895947852500                       # Number of ticks simulated
 final_tick                               5895947852500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 730138                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1137621                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1431096811                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317400                       # Number of bytes of host memory used
-host_seconds                                  4119.88                       # Real time elapsed on the host
+host_inst_rate                                 781389                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1217475                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1531550481                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272448                       # Number of bytes of host memory used
+host_seconds                                  3849.66                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -171,8 +171,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      3682716                       # number of writebacks
 system.cpu.dcache.writebacks::total           3682716                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                       # number of ReadReq MSHR misses
@@ -207,7 +205,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                10                       # number of replacements
 system.cpu.icache.tags.tagsinuse           555.751337                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          4013232207                       # Total number of references to valid blocks.
@@ -265,8 +262,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           10                       # number of writebacks
 system.cpu.icache.writebacks::total                10                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
@@ -293,7 +288,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074
 system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1919169                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        31137.283983                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14382005                       # Total number of references to valid blocks.
@@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1022289                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1022289                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          212                       # number of CleanEvict MSHR misses
@@ -454,7 +446,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18221943                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9108591                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index 6eb6b8f50..db5b9481a 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.051906                       # Nu
 sim_ticks                                 51905634500                       # Number of ticks simulated
 final_tick                                51905634500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 327219                       # Simulator instruction rate (inst/s)
-host_op_rate                                   327219                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              184808729                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257300                       # Number of bytes of host memory used
-host_seconds                                   280.86                       # Real time elapsed on the host
+host_inst_rate                                 330127                       # Simulator instruction rate (inst/s)
+host_op_rate                                   330127                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              186451175                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257296                       # Number of bytes of host memory used
+host_seconds                                   278.39                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -415,8 +415,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           36                       # number of ReadReq MSHR hits
@@ -459,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13853                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1642.330146                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            22935687                       # Total number of references to valid blocks.
@@ -520,8 +517,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        13853                       # number of writebacks
 system.cpu.icache.writebacks::total             13853                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15819                       # number of ReadReq MSHR misses
@@ -548,7 +543,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269
 system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2479.710860                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              26619                       # Total number of references to valid blocks.
@@ -657,8 +651,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1719                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3169                       # number of ReadCleanReq MSHR misses
@@ -707,7 +699,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        32058                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        14010                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 5ce51dae8..96bd3631d 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.021909                       # Nu
 sim_ticks                                 21909208500                       # Number of ticks simulated
 final_tick                                21909208500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 236201                       # Simulator instruction rate (inst/s)
-host_op_rate                                   236201                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61475451                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258056                       # Number of bytes of host memory used
-host_seconds                                   356.39                       # Real time elapsed on the host
+host_inst_rate                                 220296                       # Simulator instruction rate (inst/s)
+host_op_rate                                   220296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57335863                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258312                       # Number of bytes of host memory used
+host_seconds                                   382.12                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -672,8 +672,6 @@ system.cpu.dcache.blocked::no_mshrs               392                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.017857                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          559                       # number of ReadReq MSHR hits
@@ -724,7 +722,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9515                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1600.928709                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            15918297                       # Total number of references to valid blocks.
@@ -785,8 +782,6 @@ system.cpu.icache.blocked::no_mshrs                 4                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          159                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         9515                       # number of writebacks
 system.cpu.icache.writebacks::total              9515                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2951                       # number of ReadReq MSHR hits
@@ -819,7 +814,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858
 system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2407.364249                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              18027                       # Total number of references to valid blocks.
@@ -928,8 +922,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1703                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1703                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3062                       # number of ReadCleanReq MSHR misses
@@ -978,7 +970,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        23372                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         9673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index 21492b1f0..aa163eec8 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.130383                       # Nu
 sim_ticks                                130382890500                       # Number of ticks simulated
 final_tick                               130382890500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 248644                       # Simulator instruction rate (inst/s)
-host_op_rate                                   262111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              188134778                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275596                       # Number of bytes of host memory used
-host_seconds                                   693.03                       # Real time elapsed on the host
+host_inst_rate                                 248771                       # Simulator instruction rate (inst/s)
+host_op_rate                                   262245                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188230845                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275588                       # Number of bytes of host memory used
+host_seconds                                   692.68                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -515,8 +515,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           82                       # number of ReadReq MSHR hits
@@ -567,7 +565,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2881                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1423.942746                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            70779397                       # Total number of references to valid blocks.
@@ -628,8 +625,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         2881                       # number of writebacks
 system.cpu.icache.writebacks::total              2881                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4678                       # number of ReadReq MSHR misses
@@ -656,7 +651,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055
 system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         1999.548128                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               5178                       # Total number of references to valid blocks.
@@ -765,8 +759,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
@@ -825,7 +817,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests         9412                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         3057                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          328                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 7b9f789c6..be1a4308b 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.084938                       # Nu
 sim_ticks                                 84937723500                       # Number of ticks simulated
 final_tick                                84937723500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 146803                       # Simulator instruction rate (inst/s)
-host_op_rate                                   154755                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               72367413                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 152098                       # Simulator instruction rate (inst/s)
+host_op_rate                                   160337                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               74977715                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 271624                       # Number of bytes of host memory used
-host_seconds                                  1173.70                       # Real time elapsed on the host
+host_seconds                                  1132.84                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -772,8 +772,6 @@ system.cpu.dcache.blocked::no_mshrs                 2                       # nu
 system.cpu.dcache.blocked::no_targets             864                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    12.428241                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        72581                       # number of writebacks
 system.cpu.dcache.writebacks::total             72581                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24802                       # number of ReadReq MSHR hits
@@ -826,7 +824,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             53623                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.594536                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78269055                       # Total number of references to valid blocks.
@@ -887,8 +884,6 @@ system.cpu.icache.blocked::no_mshrs              3246                       # nu
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    22.549291                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        53623                       # number of writebacks
 system.cpu.icache.writebacks::total             53623                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3399                       # number of ReadReq MSHR hits
@@ -921,7 +916,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853
 system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued         9269                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified         9269                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
@@ -1040,8 +1034,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
@@ -1114,7 +1106,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       253433                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       126224                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10473                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index f0a8cbf5a..d2b7d14ce 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.103324                       # Nu
 sim_ticks                                103324153500                       # Number of ticks simulated
 final_tick                               103324153500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72241                       # Simulator instruction rate (inst/s)
-host_op_rate                                   121082                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56516511                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307592                       # Number of bytes of host memory used
-host_seconds                                  1828.21                       # Real time elapsed on the host
+host_inst_rate                                  75581                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126680                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59129521                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307596                       # Number of bytes of host memory used
+host_seconds                                  1747.42                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -632,8 +632,6 @@ system.cpu.dcache.blocked::no_mshrs                 8                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.125000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    36.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
 system.cpu.dcache.writebacks::total                18                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          661                       # number of ReadReq MSHR hits
@@ -676,7 +674,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              6515                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1663.291735                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            41248897                       # Total number of references to valid blocks.
@@ -737,8 +734,6 @@ system.cpu.icache.blocked::no_mshrs                30                       # nu
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    69.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          305                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         6515                       # number of writebacks
 system.cpu.icache.writebacks::total              6515                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4088                       # number of ReadReq MSHR hits
@@ -771,7 +766,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640
 system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2796.844278                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              11471                       # Total number of references to valid blocks.
@@ -888,8 +882,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          500                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total          500                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1507                       # number of ReadExReq MSHR misses
@@ -946,7 +938,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        18206                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         7138                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          549                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 41f61bd3d..90f1f17e3 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.869358                       # Nu
 sim_ticks                                1869357988000                       # Number of ticks simulated
 final_tick                               1869357988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1993950                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1993950                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            57344769220                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 333724                       # Number of bytes of host memory used
-host_seconds                                    32.60                       # Real time elapsed on the host
+host_inst_rate                                1670594                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1670593                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48045239456                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 332628                       # Number of bytes of host memory used
+host_seconds                                    38.91                       # Real time elapsed on the host
 sim_insts                                    64999904                       # Number of instructions simulated
 sim_ops                                      64999904                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -301,11 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       633127                       # number of writebacks
 system.cpu0.dcache.writebacks::total           633127                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements           618292                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.240644                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs           48866947                       # Total number of references to valid blocks.
@@ -352,11 +349,8 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks       618292                       # number of writebacks
 system.cpu0.icache.writebacks::total           618292                       # number of writebacks
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
@@ -589,11 +583,8 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       144536                       # number of writebacks
 system.cpu1.dcache.writebacks::total           144536                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements           380647                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          453.133719                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs           15144687                       # Total number of references to valid blocks.
@@ -639,11 +630,8 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks       380647                       # number of writebacks
 system.cpu1.icache.writebacks::total           380647                       # number of writebacks
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -704,18 +692,18 @@ system.iocache.ReadReq_misses::tsunami.ide          179                       #
 system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          179                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               179                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          179                       # number of overall misses
-system.iocache.overall_misses::total              179                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41731                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41731                       # number of overall misses
+system.iocache.overall_misses::total            41731                       # number of overall misses
 system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          179                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             179                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          179                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            179                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41731                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41731                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41731                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41731                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -730,11 +718,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   999922                       # number of replacements
 system.l2c.tags.tagsinuse                65337.856722                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4259784                       # Total number of references to valid blocks.
@@ -875,11 +860,8 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               80923                       # number of writebacks
 system.l2c.writebacks::total                    80923                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7449                       # Transaction distribution
 system.membus.trans_dist::ReadResp             948784                       # Transaction distribution
 system.membus.trans_dist::WriteReq              14588                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 25be00c51..84bdf9ee5 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829331993500                       # Number of ticks simulated
 final_tick                               1829331993500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1828258                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1828257                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            55705727715                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 331420                       # Number of bytes of host memory used
-host_seconds                                    32.84                       # Real time elapsed on the host
+host_inst_rate                                1840131                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1840130                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            56067507873                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 330836                       # Number of bytes of host memory used
+host_seconds                                    32.63                       # Real time elapsed on the host
 sim_insts                                    60038469                       # Number of instructions simulated
 sim_ops                                      60038469                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -282,11 +282,8 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       833475                       # number of writebacks
 system.cpu.dcache.writebacks::total            833475                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            919603                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.215257                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            59130077                       # Total number of references to valid blocks.
@@ -333,11 +330,8 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       919603                       # number of writebacks
 system.cpu.icache.writebacks::total            919603                       # number of writebacks
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           992419                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65424.374401                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4560132                       # Total number of references to valid blocks.
@@ -430,11 +424,8 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        74359                       # number of writebacks
 system.cpu.l2cache.writebacks::total            74359                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5925776                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2962432                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1834                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -532,18 +523,18 @@ system.iocache.ReadReq_misses::tsunami.ide          174                       #
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          174                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               174                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          174                       # number of overall misses
-system.iocache.overall_misses::total              174                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
+system.iocache.overall_misses::total            41726                       # number of overall misses
 system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          174                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             174                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          174                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            174                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -558,11 +549,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7184                       # Transaction distribution
 system.membus.trans_dist::ReadResp             948291                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 3cac0b91e..e58364a4b 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.982593                       # Nu
 sim_ticks                                1982592736000                       # Number of ticks simulated
 final_tick                               1982592736000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 753764                       # Simulator instruction rate (inst/s)
-host_op_rate                                   753764                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            24497172234                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320072                       # Number of bytes of host memory used
-host_seconds                                    80.93                       # Real time elapsed on the host
+host_inst_rate                                1178528                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1178528                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38301918928                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 332884                       # Number of bytes of host memory used
+host_seconds                                    51.76                       # Real time elapsed on the host
 sim_insts                                    61003209                       # Number of instructions simulated
 sim_ops                                      61003209                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -580,8 +580,6 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       672790                       # number of writebacks
 system.cpu0.dcache.writebacks::total           672790                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       934179                       # number of ReadReq MSHR misses
@@ -616,10 +614,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  58495510500
 system.cpu0.dcache.overall_mshr_miss_latency::total  58495510500                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1566902000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1566902000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2451870500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2451870500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4018772500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4018772500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1566902000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1566902000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.128375                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.128375                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051354                       # mshr miss rate for WriteReq accesses
@@ -646,11 +642,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements           686545                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          506.490868                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs           46637883                       # Total number of references to valid blocks.
@@ -708,8 +701,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks       686545                       # number of writebacks
 system.cpu0.icache.writebacks::total           686545                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       687179                       # number of ReadReq MSHR misses
@@ -736,7 +727,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971
 system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
@@ -989,8 +979,6 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       119726                       # number of writebacks
 system.cpu1.dcache.writebacks::total           119726                       # number of writebacks
 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       123491                       # number of ReadReq MSHR misses
@@ -1025,10 +1013,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3237985000
 system.cpu1.dcache.overall_mshr_miss_latency::total   3237985000                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     25051000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     25051000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    789482500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    789482500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    814533500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    814533500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     25051000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total     25051000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.050137                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.050137                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036996                       # mshr miss rate for WriteReq accesses
@@ -1055,11 +1041,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data  7227.639931                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total  7227.639931                       # average overall mshr uncacheable latency
 system.cpu1.icache.tags.replacements           331529                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          442.932822                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs           13358029                       # Total number of references to valid blocks.
@@ -1119,8 +1102,6 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks       331529                       # number of writebacks
 system.cpu1.icache.writebacks::total           331529                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       332081                       # number of ReadReq MSHR misses
@@ -1147,7 +1128,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283
 system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1232,26 +1212,26 @@ system.iocache.ReadReq_misses::tsunami.ide          175                       #
 system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
-system.iocache.overall_misses::total              175                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41727                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
+system.iocache.overall_misses::total            41727                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21956883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21956883                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245146529                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   5245146529                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21956883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21956883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21956883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21956883                       # number of overall miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5267103412                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5267103412                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5267103412                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5267103412                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41727                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1264,36 +1244,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857
 system.iocache.ReadReq_avg_miss_latency::total 125467.902857                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125467.902857                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125467.902857                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126227.704172                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126227.704172                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41727                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41727                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41727                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41727                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13206883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13206883                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165739741                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3165739741                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13206883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13206883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13206883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13206883                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3178946624                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3178946624                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3178946624                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3178946624                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1306,11 +1284,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857
 system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76184.403959                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76184.403959                       # average overall mshr miss latency
 system.l2c.tags.replacements                   342136                       # number of replacements
 system.l2c.tags.tagsinuse                65163.366749                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    3685387                       # Total number of references to valid blocks.
@@ -1501,8 +1478,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               79408                       # number of writebacks
 system.l2c.writebacks::total                    79408                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           11                       # number of ReadCleanReq MSHR hits
@@ -1575,12 +1550,9 @@ system.l2c.overall_mshr_miss_latency::total  47046710502                       #
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1478327000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     23575500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total   1501902500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2327774501                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    750967500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   3078742001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3806101501                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    774543000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4580644501                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1478327000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data     23575500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1501902500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941997                       # mshr miss rate for UpgradeReq accesses
@@ -1636,13 +1608,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 115267.622116
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data  6801.933064                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq                7201                       # Transaction distribution
 system.membus.trans_dist::ReadResp             292681                       # Transaction distribution
 system.membus.trans_dist::WriteReq              14131                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 04e45bbeb..b4533a137 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.941276                       # Nu
 sim_ticks                                1941275996000                       # Number of ticks simulated
 final_tick                               1941275996000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1255554                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1255553                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            43383023327                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 332188                       # Number of bytes of host memory used
-host_seconds                                    44.75                       # Real time elapsed on the host
+host_inst_rate                                1048317                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1048317                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            36222399744                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 330588                       # Number of bytes of host memory used
+host_seconds                                    53.59                       # Real time elapsed on the host
 sim_insts                                    56182685                       # Number of instructions simulated
 sim_ops                                      56182685                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -560,8 +560,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       834944                       # number of writebacks
 system.cpu.dcache.writebacks::total            834944                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069359                       # number of ReadReq MSHR misses
@@ -592,10 +590,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61034127000
 system.cpu.dcache.overall_mshr_miss_latency::total  61034127000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1526978500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1526978500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2172486500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2172486500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3699465000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3699465000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1526978500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1526978500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120373                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120373                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049431                       # mshr miss rate for WriteReq accesses
@@ -618,11 +614,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements            928931                       # number of replacements
 system.cpu.icache.tags.tagsinuse           506.355616                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            55264917                       # Total number of references to valid blocks.
@@ -682,8 +675,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       928931                       # number of writebacks
 system.cpu.icache.writebacks::total            928931                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929602                       # number of ReadReq MSHR misses
@@ -710,7 +701,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459
 system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           336393                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65234.360001                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3930403                       # Total number of references to valid blocks.
@@ -831,8 +821,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        74281                       # number of writebacks
 system.cpu.l2cache.writebacks::total            74281                       # number of writebacks
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
@@ -871,10 +859,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44734676000
 system.cpu.l2cache.overall_mshr_miss_latency::total  46329472000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1440322500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1440322500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2061396500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2061396500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3501719000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3501719000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1440322500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1440322500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383885                       # mshr miss rate for ReadExReq accesses
@@ -905,11 +891,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      4639867                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319499                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1502                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1040,26 +1023,26 @@ system.iocache.ReadReq_misses::tsunami.ide          173                       #
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
+system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21742883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21742883                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::tsunami.ide   5244713284                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   5244713284                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21742883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21742883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21742883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21742883                       # number of overall miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5266456167                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5266456167                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5266456167                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5266456167                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1072,36 +1055,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624
 system.iocache.ReadReq_avg_miss_latency::total 125681.404624                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125681.404624                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125681.404624                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126218.242469                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126218.242469                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs            29                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs    14.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13092883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13092883                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165314984                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3165314984                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13092883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13092883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13092883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13092883                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3178407867                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3178407867                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3178407867                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3178407867                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1114,11 +1095,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624
 system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75681.404624                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75681.404624                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76175.143607                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76175.143607                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
 system.membus.trans_dist::ReadResp             292274                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9653                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
index f7d0d7b39..b93cd163b 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783855                       # Nu
 sim_ticks                                2783854535000                       # Number of ticks simulated
 final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1852974                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2255698                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            36130480826                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 581484                       # Number of bytes of host memory used
-host_seconds                                    77.05                       # Real time elapsed on the host
+host_inst_rate                                1211130                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1474356                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23615387886                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 581436                       # Number of bytes of host memory used
+host_seconds                                   117.88                       # Real time elapsed on the host
 sim_insts                                   142771651                       # Number of instructions simulated
 sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       682017                       # number of writebacks
 system.cpu.dcache.writebacks::total            682017                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1698998                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.663679                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           145341757                       # Total number of references to valid blocks.
@@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1698998                       # number of writebacks
 system.cpu.icache.writebacks::total           1698998                       # number of writebacks
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           109913                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65155.314985                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4524855                       # Total number of references to valid blocks.
@@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       101950                       # number of writebacks
 system.cpu.l2cache.writebacks::total           101950                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5059903                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540486                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39261                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide          240                       #
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          240                       # number of overall misses
-system.iocache.overall_misses::total              240                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36464                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36464                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36464                       # number of overall misses
+system.iocache.overall_misses::total            36464                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36464                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36464                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36464                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36464                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index df10533fc..4464ff885 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.802883                       # Nu
 sim_ticks                                2802882879000                       # Number of ticks simulated
 final_tick                               2802882879000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1272297                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1550275                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            24287502010                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 596572                       # Number of bytes of host memory used
-host_seconds                                   115.40                       # Real time elapsed on the host
+host_inst_rate                                1338296                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1630694                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25547394462                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 592020                       # Number of bytes of host memory used
+host_seconds                                   109.71                       # Real time elapsed on the host
 sim_insts                                   146828562                       # Number of instructions simulated
 sim_ops                                     178908371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -365,11 +365,8 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       693475                       # number of writebacks
 system.cpu0.dcache.writebacks::total           693475                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements          1109624                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.809991                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs           96331795                       # Total number of references to valid blocks.
@@ -416,11 +413,8 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      1109624                       # number of writebacks
 system.cpu0.icache.writebacks::total          1109624                       # number of writebacks
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
 system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
@@ -555,11 +549,8 @@ system.cpu0.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu0.l2cache.writebacks::writebacks       193020                       # number of writebacks
 system.cpu0.l2cache.writebacks::total          193020                       # number of writebacks
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
 system.cpu0.toL2Bus.snoop_filter.tot_requests      3720001                       # Total number of requests made to the snoop filter.
 system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1860202                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27865                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -876,11 +867,8 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       191946                       # number of writebacks
 system.cpu1.dcache.writebacks::total           191946                       # number of writebacks
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements           523401                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          499.711077                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs           53148863                       # Total number of references to valid blocks.
@@ -926,11 +914,8 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks       523401                       # number of writebacks
 system.cpu1.icache.writebacks::total           523401                       # number of writebacks
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
@@ -1064,11 +1049,8 @@ system.cpu1.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu1.l2cache.writebacks::writebacks        32706                       # number of writebacks
 system.cpu1.l2cache.writebacks::total           32706                       # number of writebacks
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
 system.cpu1.toL2Bus.snoop_filter.tot_requests      1533509                       # Total number of requests made to the snoop filter.
 system.cpu1.toL2Bus.snoop_filter.hit_single_requests       773310                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11158                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1178,18 +1160,18 @@ system.iocache.ReadReq_misses::realview.ide          252                       #
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          252                       # number of overall misses
-system.iocache.overall_misses::total              252                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36476                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36476                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36476                       # number of overall misses
+system.iocache.overall_misses::total            36476                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36476                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36476                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36476                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36476                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1204,11 +1186,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   107729                       # number of replacements
 system.l2c.tags.tagsinuse                62410.633039                       # Cycle average of tags in use
 system.l2c.tags.total_refs                     243914                       # Total number of references to valid blocks.
@@ -1384,11 +1363,8 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               96268                       # number of writebacks
 system.l2c.writebacks::total                    96268                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               43996                       # Transaction distribution
 system.membus.trans_dist::ReadResp              75724                       # Transaction distribution
 system.membus.trans_dist::WriteReq              30846                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index ef75cc834..d5c7e4211 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783855                       # Nu
 sim_ticks                                2783854535000                       # Number of ticks simulated
 final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1173204                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1428188                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            22875895912                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 581200                       # Number of bytes of host memory used
-host_seconds                                   121.69                       # Real time elapsed on the host
+host_inst_rate                                1225194                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1491477                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23889629831                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 578692                       # Number of bytes of host memory used
+host_seconds                                   116.53                       # Real time elapsed on the host
 sim_insts                                   142771651                       # Number of instructions simulated
 sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       682017                       # number of writebacks
 system.cpu.dcache.writebacks::total            682017                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1698998                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.663679                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           145341757                       # Total number of references to valid blocks.
@@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1698998                       # number of writebacks
 system.cpu.icache.writebacks::total           1698998                       # number of writebacks
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           109913                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65155.314985                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4524855                       # Total number of references to valid blocks.
@@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       101950                       # number of writebacks
 system.cpu.l2cache.writebacks::total           101950                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5059903                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540486                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39261                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide          240                       #
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          240                       # number of overall misses
-system.iocache.overall_misses::total              240                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36464                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36464                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36464                       # number of overall misses
+system.iocache.overall_misses::total            36464                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36464                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36464                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36464                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36464                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index abcd4eac1..28d366488 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.871806                       # Nu
 sim_ticks                                2871806231000                       # Number of ticks simulated
 final_tick                               2871806231000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 937604                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1134083                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            20478123685                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 614632                       # Number of bytes of host memory used
-host_seconds                                   140.24                       # Real time elapsed on the host
+host_inst_rate                                 717242                       # Simulator instruction rate (inst/s)
+host_op_rate                                   867543                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15665668571                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 616200                       # Number of bytes of host memory used
+host_seconds                                   183.32                       # Real time elapsed on the host
 sim_insts                                   131483712                       # Number of instructions simulated
 sim_ops                                     159036662                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -687,8 +687,6 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       733230                       # number of writebacks
 system.cpu0.dcache.writebacks::total           733230                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25285                       # number of ReadReq MSHR hits
@@ -739,10 +737,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13170657000
 system.cpu0.dcache.overall_mshr_miss_latency::total  13170657000                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6628843000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6628843000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5400920500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5400920500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12029763500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12029763500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6628843000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6628843000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015824                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015824                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017926                       # mshr miss rate for WriteReq accesses
@@ -775,11 +771,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements          1147026                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.321434                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          120430031                       # Total number of references to valid blocks.
@@ -838,8 +831,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      1147026                       # number of writebacks
 system.cpu0.icache.writebacks::total          1147026                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1147547                       # number of ReadReq MSHR misses
@@ -878,7 +869,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued      1935584                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified      1935659                       # number of prefetch candidates identified
 system.cpu0.l2cache.prefetcher.pfBufferHit           66                       # number of redundant prefetches already in prefetch queue
@@ -1080,8 +1070,6 @@ system.cpu0.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu0.l2cache.unused_prefetches           10692                       # number of HardPF blocks evicted w/o reference
 system.cpu0.l2cache.writebacks::writebacks       231848                       # number of writebacks
 system.cpu0.l2cache.writebacks::total          231848                       # number of writebacks
@@ -1160,11 +1148,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total  28461338140
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6373893500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7560105000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5187056500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5187056500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11560950000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12747161500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6373893500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7560105000                       # number of overall MSHR uncacheable cycles
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.013766                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.014908                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.014117                       # mshr miss rate for ReadReq accesses
@@ -1224,12 +1210,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226                       # average overall mshr uncacheable latency
 system.cpu0.toL2Bus.snoop_filter.tot_requests      3905427                       # Total number of requests made to the snoop filter.
 system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1969134                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        28903                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1629,8 +1612,6 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks::writebacks       148452                       # number of writebacks
 system.cpu1.dcache.writebacks::total           148452                       # number of writebacks
 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          223                       # number of ReadReq MSHR hits
@@ -1679,10 +1660,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4699929000
 system.cpu1.dcache.overall_mshr_miss_latency::total   4699929000                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    439527500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    439527500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    303136500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    303136500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    742664000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    742664000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    439527500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    439527500                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035447                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035447                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028102                       # mshr miss rate for WriteReq accesses
@@ -1715,11 +1694,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295                       # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720                       # average overall mshr uncacheable latency
 system.cpu1.icache.tags.replacements           463484                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          498.310914                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs           13457758                       # Total number of references to valid blocks.
@@ -1778,8 +1754,6 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks       463484                       # number of writebacks
 system.cpu1.icache.writebacks::total           463484                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463996                       # number of ReadReq MSHR misses
@@ -1818,7 +1792,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446                       # average overall mshr uncacheable latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued       117918                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified       117936                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit           16                       # number of redundant prefetches already in prefetch queue
@@ -2015,8 +1988,6 @@ system.cpu1.l2cache.blocked::no_mshrs               0                       # nu
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
-system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
 system.cpu1.l2cache.unused_prefetches             502                       # number of HardPF blocks evicted w/o reference
 system.cpu1.l2cache.writebacks::writebacks        26072                       # number of writebacks
 system.cpu1.l2cache.writebacks::total           26072                       # number of writebacks
@@ -2093,11 +2064,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total   3906024043
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    414523000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    436742000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    284955500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    284955500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    699478500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    721697500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    414523000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    436742000                       # number of overall MSHR uncacheable cycles
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.124642                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.166480                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.140986                       # mshr miss rate for ReadReq accesses
@@ -2157,12 +2126,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348                       # average overall mshr uncacheable latency
 system.cpu1.toL2Bus.snoop_filter.tot_requests      1324952                       # Total number of requests made to the snoop filter.
 system.cpu1.toL2Bus.snoop_filter.hit_single_requests       669028                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10089                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -2333,26 +2299,26 @@ system.iocache.ReadReq_misses::realview.ide          255                       #
 system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          255                       # number of overall misses
-system.iocache.overall_misses::total              255                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36479                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36479                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36479                       # number of overall misses
+system.iocache.overall_misses::total            36479                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     32883377                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     32883377                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::realview.ide   4577110345                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   4577110345                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32883377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32883377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32883377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32883377                       # number of overall miss cycles
+system.iocache.demand_miss_latency::realview.ide   4609993722                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4609993722                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4609993722                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4609993722                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36479                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36479                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36479                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36479                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2365,36 +2331,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608
 system.iocache.ReadReq_avg_miss_latency::total 128954.419608                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 128954.419608                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 128954.419608                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 128954.419608                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 128954.419608                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126373.906138                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126373.906138                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126373.906138                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126373.906138                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs            24                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs           12                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36206                       # number of writebacks
 system.iocache.writebacks::total                36206                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        36479                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36479                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36479                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36479                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     20133377                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     20133377                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2764215832                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   2764215832                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     20133377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     20133377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     20133377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     20133377                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2784349209                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2784349209                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2784349209                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2784349209                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2407,11 +2371,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608
 system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 78954.419608                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 78954.419608                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76327.454398                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76327.454398                       # average overall mshr miss latency
 system.l2c.tags.replacements                   124374                       # number of replacements
 system.l2c.tags.tagsinuse                62971.222447                       # Cycle average of tags in use
 system.l2c.tags.total_refs                     421293                       # Total number of references to valid blocks.
@@ -2693,8 +2656,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               97172                       # number of writebacks
 system.l2c.writebacks::total                    97172                       # number of writebacks
 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            4                       # number of ReadSharedReq MSHR hits
@@ -2798,14 +2759,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5801182501
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    359054501                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total   7203084502                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4702546001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    243701000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4946247001                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10503728502                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5801182501                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    602755501                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12149331503                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    359054501                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   7203084502                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.224375                       # mshr miss rate for UpgradeReq accesses
@@ -2885,15 +2843,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               44095                       # Transaction distribution
 system.membus.trans_dist::ReadResp             214453                       # Transaction distribution
 system.membus.trans_dist::WriteReq              30922                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 913ae877a..da0ada0fc 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.909587                       # Nu
 sim_ticks                                2909586837500                       # Number of ticks simulated
 final_tick                               2909586837500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 929184                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1120306                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            24040663881                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 581600                       # Number of bytes of host memory used
-host_seconds                                   121.03                       # Real time elapsed on the host
+host_inst_rate                                 812558                       # Simulator instruction rate (inst/s)
+host_op_rate                                   979692                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            21023218607                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 578440                       # Number of bytes of host memory used
+host_seconds                                   138.40                       # Real time elapsed on the host
 sim_insts                                   112457033                       # Number of instructions simulated
 sim_ops                                     135588117                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -651,8 +651,6 @@ system.cpu.dcache.blocked::no_mshrs                20                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       683846                       # number of writebacks
 system.cpu.dcache.writebacks::total            683846                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          929                       # number of ReadReq MSHR hits
@@ -699,10 +697,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26477503500
 system.cpu.dcache.overall_mshr_miss_latency::total  26477503500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6278149500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6278149500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5089976500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5089976500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11368126000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11368126000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6278149500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6278149500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016969                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016969                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015620                       # mshr miss rate for WriteReq accesses
@@ -733,11 +729,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements           1695721                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.436852                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           113858019                       # Total number of references to valid blocks.
@@ -797,8 +790,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1695721                       # number of writebacks
 system.cpu.icache.writebacks::total           1695721                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1696239                       # number of ReadReq MSHR misses
@@ -837,7 +828,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            87565                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        64865.223598                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4544536                       # Total number of references to valid blocks.
@@ -1017,8 +1007,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        81185                       # number of writebacks
 system.cpu.l2cache.writebacks::total            81185                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
@@ -1078,11 +1066,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total  18759768500
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888804000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6918570000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4772572500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4772572500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10661376500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11691142500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5888804000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6918570000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000759                       # mshr miss rate for ReadReq accesses
@@ -1132,12 +1118,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      5052863                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2536887                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38132                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1305,26 +1288,26 @@ system.iocache.ReadReq_misses::realview.ide          228                       #
 system.iocache.ReadReq_misses::total              228                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          228                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          228                       # number of overall misses
-system.iocache.overall_misses::total              228                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36452                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36452                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36452                       # number of overall misses
+system.iocache.overall_misses::total            36452                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     28180377                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     28180377                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::realview.ide   4549133150                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   4549133150                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28180377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28180377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28180377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28180377                       # number of overall miss cycles
+system.iocache.demand_miss_latency::realview.ide   4577313527                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4577313527                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4577313527                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4577313527                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          228                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             228                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          228                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            228                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36452                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36452                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36452                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36452                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1337,36 +1320,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737
 system.iocache.ReadReq_avg_miss_latency::total 123598.144737                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123598.144737                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123598.144737                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125570.984500                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125570.984500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125570.984500                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125570.984500                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          228                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          228                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        36452                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36452                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36452                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36452                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     16780377                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     16780377                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736521626                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   2736521626                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16780377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16780377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16780377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16780377                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2753302003                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2753302003                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2753302003                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2753302003                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1379,11 +1360,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737
 system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75532.261687                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75532.261687                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
 system.membus.trans_dist::ReadResp              70548                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index e0084d588..254a8cf36 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783855                       # Nu
 sim_ticks                                2783854535000                       # Number of ticks simulated
 final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1278958                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1556926                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            24937950041                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 579412                       # Number of bytes of host memory used
-host_seconds                                   111.63                       # Real time elapsed on the host
+host_inst_rate                                1181524                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1438316                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23038118447                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 579724                       # Number of bytes of host memory used
+host_seconds                                   120.84                       # Real time elapsed on the host
 sim_insts                                   142771651                       # Number of instructions simulated
 sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -391,11 +391,8 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       682241                       # number of writebacks
 system.cpu0.dcache.writebacks::total           682241                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements          1698998                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.663679                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          145341757                       # Total number of references to valid blocks.
@@ -457,11 +454,8 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      1698998                       # number of writebacks
 system.cpu0.icache.writebacks::total          1698998                       # number of writebacks
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -728,18 +722,18 @@ system.iocache.ReadReq_misses::realview.ide          240                       #
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          240                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               240                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          240                       # number of overall misses
-system.iocache.overall_misses::total              240                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36464                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36464                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36464                       # number of overall misses
+system.iocache.overall_misses::total            36464                       # number of overall misses
 system.iocache.ReadReq_accesses::realview.ide          240                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            240                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          240                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             240                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          240                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            240                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36464                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36464                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36464                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36464                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -754,11 +748,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   109907                       # number of replacements
 system.l2c.tags.tagsinuse                65155.314985                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4528037                       # Total number of references to valid blocks.
@@ -948,11 +939,8 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks              101944                       # number of writebacks
 system.l2c.writebacks::total                   101944                       # number of writebacks
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74196                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index cd3a72dfc..e91a37dbe 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.909645                       # Nu
 sim_ticks                                2909644861500                       # Number of ticks simulated
 final_tick                               2909644861500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 955579                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1152126                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            24724694945                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 580436                       # Number of bytes of host memory used
-host_seconds                                   117.68                       # Real time elapsed on the host
+host_inst_rate                                 753896                       # Simulator instruction rate (inst/s)
+host_op_rate                                   908960                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19506336140                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 580236                       # Number of bytes of host memory used
+host_seconds                                   149.16                       # Real time elapsed on the host
 sim_insts                                   112454211                       # Number of instructions simulated
 sim_ops                                     135584166                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -721,8 +721,6 @@ system.cpu0.dcache.blocked::no_mshrs               22                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs     6.727273                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks       683901                       # number of writebacks
 system.cpu0.dcache.writebacks::total           683901                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          477                       # number of ReadReq MSHR hits
@@ -789,12 +787,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total  26462029000
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3048418500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3229696000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6278114500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2495078000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2594854500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5089932500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5543496500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5824550500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11368047000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3048418500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3229696000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6278114500                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017211                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016733                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016968                       # mshr miss rate for ReadReq accesses
@@ -838,13 +833,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186338.909634                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182749.102049                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.373373                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195262.293061                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191994.940172                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.454680                       # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 107376.488200                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106460.625639                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106903.374938                       # average overall mshr uncacheable latency
 system.cpu0.icache.tags.replacements          1695677                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          510.436645                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          113855199                       # Total number of references to valid blocks.
@@ -924,8 +915,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks      1695677                       # number of writebacks
 system.cpu0.icache.writebacks::total          1695677                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       840174                       # number of ReadReq MSHR misses
@@ -982,7 +971,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671                       # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1315,26 +1303,26 @@ system.iocache.ReadReq_misses::realview.ide          228                       #
 system.iocache.ReadReq_misses::total              228                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          228                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          228                       # number of overall misses
-system.iocache.overall_misses::total              228                       # number of overall misses
+system.iocache.demand_misses::realview.ide        36452                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36452                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36452                       # number of overall misses
+system.iocache.overall_misses::total            36452                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     28181877                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     28181877                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::realview.ide   4548907143                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   4548907143                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28181877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28181877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28181877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28181877                       # number of overall miss cycles
+system.iocache.demand_miss_latency::realview.ide   4577089020                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4577089020                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4577089020                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4577089020                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          228                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             228                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          228                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            228                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36452                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36452                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36452                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36452                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1347,36 +1335,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684
 system.iocache.ReadReq_avg_miss_latency::total 123604.723684                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123604.723684                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123604.723684                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123604.723684                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123604.723684                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125564.825524                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125564.825524                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125564.825524                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125564.825524                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          228                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          228                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        36452                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36452                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36452                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36452                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     16781877                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     16781877                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736290629                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   2736290629                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16781877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16781877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16781877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16781877                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2753072506                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2753072506                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2753072506                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2753072506                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1389,11 +1375,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684
 system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 73604.723684                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 73604.723684                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 73604.723684                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 73604.723684                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75525.965818                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75525.965818                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75525.965818                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75525.965818                       # average overall mshr miss latency
 system.l2c.tags.replacements                    87562                       # number of replacements
 system.l2c.tags.tagsinuse                64865.213908                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4551019                       # Total number of references to valid blocks.
@@ -1651,8 +1636,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.writebacks::writebacks               81183                       # number of writebacks
 system.l2c.writebacks::total                    81183                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4                       # number of ReadReq MSHR misses
@@ -1741,14 +1724,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2860870000
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3027916000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::total   6918904000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2341022000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2431506500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4772528500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5201892000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2860870000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5459422500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11691432500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3027916000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6918904000                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000687                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000287                       # mshr miss rate for ReadReq accesses
@@ -1822,15 +1802,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174833.607170                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171244.911613                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.643227                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183229.728778                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 100770.341670                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179959.208228                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 172569.816529                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99809.341728                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 102125.551669                       # average overall mshr uncacheable latency
 system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
 system.membus.trans_dist::ReadResp              70546                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 926ea5f21..422618199 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.112152                       # Nu
 sim_ticks                                5112151729000                       # Number of ticks simulated
 final_tick                               5112151729000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1266983                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2593792                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32374197845                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 659352                       # Number of bytes of host memory used
-host_seconds                                   157.91                       # Real time elapsed on the host
+host_inst_rate                                1369712                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2804100                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            34999130987                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 614748                       # Number of bytes of host memory used
+host_seconds                                   146.07                       # Real time elapsed on the host
 sim_insts                                   200067055                       # Number of instructions simulated
 sim_ops                                     409581065                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -174,11 +174,8 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1535790                       # number of writebacks
 system.cpu.dcache.writebacks::total           1535790                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.tags.replacements         7749                       # number of replacements
 system.cpu.dtb_walker_cache.tags.tagsinuse     5.014001                       # Cycle average of tags in use
 system.cpu.dtb_walker_cache.tags.total_refs        12936                       # Total number of references to valid blocks.
@@ -225,11 +222,8 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs            0
 system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.dtb_walker_cache.writebacks::writebacks         2897                       # number of writebacks
 system.cpu.dtb_walker_cache.writebacks::total         2897                       # number of writebacks
-system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            792340                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.662956                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           243675443                       # Total number of references to valid blocks.
@@ -277,11 +271,8 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       792340                       # number of writebacks
 system.cpu.icache.writebacks::total            792340                       # number of writebacks
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements         3586                       # number of replacements
 system.cpu.itb_walker_cache.tags.tagsinuse     3.026555                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs         7763                       # Total number of references to valid blocks.
@@ -332,11 +323,8 @@ system.cpu.itb_walker_cache.blocked::no_mshrs            0
 system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.itb_walker_cache.writebacks::writebacks          700                       # number of writebacks
 system.cpu.itb_walker_cache.writebacks::total          700                       # number of writebacks
-system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           106202                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        64823.935074                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4340729                       # Total number of references to valid blocks.
@@ -457,11 +445,8 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        98175                       # number of writebacks
 system.cpu.l2cache.writebacks::total            98175                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      4856494                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425336                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        11672                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -575,18 +560,18 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide          903
 system.iocache.ReadReq_misses::total              903                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          903                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               903                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          903                       # number of overall misses
-system.iocache.overall_misses::total              903                       # number of overall misses
+system.iocache.demand_misses::pc.south_bridge.ide        47623                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47623                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47623                       # number of overall misses
+system.iocache.overall_misses::total            47623                       # number of overall misses
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          903                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            903                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          903                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             903                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          903                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            903                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47623                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47623                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47623                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47623                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -601,11 +586,8 @@ system.iocache.blocked::no_mshrs                    0                       # nu
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq            13857337                       # Transaction distribution
 system.membus.trans_dist::ReadResp           13903644                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13943                       # Transaction distribution
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 38633f47f..94a3f35b5 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.194946                       # Nu
 sim_ticks                                5194946000500                       # Number of ticks simulated
 final_tick                               5194946000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 842553                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1624008                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            34079125299                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 659848                       # Number of bytes of host memory used
-host_seconds                                   152.44                       # Real time elapsed on the host
+host_inst_rate                                 910377                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1754736                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            36822413305                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 616280                       # Number of bytes of host memory used
+host_seconds                                   141.08                       # Real time elapsed on the host
 sim_insts                                   128436892                       # Number of instructions simulated
 sim_ops                                     247560077                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -451,8 +451,6 @@ system.cpu.dcache.blocked::no_mshrs               514                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    37.521401                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1540773                       # number of writebacks
 system.cpu.dcache.writebacks::total           1540773                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          285                       # number of ReadReq MSHR hits
@@ -491,10 +489,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36311500467
 system.cpu.dcache.overall_mshr_miss_latency::total  36311500467                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  95132085000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  95132085000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2786349500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2786349500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  97918434500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  97918434500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  95132085000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  95132085000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070257                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070257                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037690                       # mshr miss rate for WriteReq accesses
@@ -517,11 +513,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131                       # average overall mshr uncacheable latency
 system.cpu.dtb_walker_cache.tags.replacements         7581                       # number of replacements
 system.cpu.dtb_walker_cache.tags.tagsinuse     5.052199                       # Cycle average of tags in use
 system.cpu.dtb_walker_cache.tags.total_refs        13343                       # Total number of references to valid blocks.
@@ -581,8 +574,6 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs            0
 system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.dtb_walker_cache.writebacks::writebacks         2983                       # number of writebacks
 system.cpu.dtb_walker_cache.writebacks::total         2983                       # number of writebacks
 system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8791                       # number of ReadReq MSHR misses
@@ -609,7 +600,6 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9971.5
 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9971.504948                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9971.504948                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9971.504948                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            790489                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.213579                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           144635934                       # Total number of references to valid blocks.
@@ -669,8 +659,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       790489                       # number of writebacks
 system.cpu.icache.writebacks::total            790489                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791008                       # number of ReadReq MSHR misses
@@ -697,7 +685,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406
 system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements         3383                       # number of replacements
 system.cpu.itb_walker_cache.tags.tagsinuse     3.069456                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs         7971                       # Total number of references to valid blocks.
@@ -761,8 +748,6 @@ system.cpu.itb_walker_cache.blocked::no_mshrs            0
 system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
 system.cpu.itb_walker_cache.writebacks::writebacks          773                       # number of writebacks
 system.cpu.itb_walker_cache.writebacks::total          773                       # number of writebacks
 system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4247                       # number of ReadReq MSHR misses
@@ -789,7 +774,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9561.8
 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9561.808335                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9561.808335                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9561.808335                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            87287                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        64590.438483                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4366272                       # Total number of references to valid blocks.
@@ -950,8 +934,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        80702                       # number of writebacks
 system.cpu.l2cache.writebacks::total            80702                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
@@ -1004,10 +986,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16768538500
 system.cpu.l2cache.overall_mshr_miss_latency::total  18328972000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88302755000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88302755000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2626267500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2626267500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  90929022500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  90929022500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  88302755000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  88302755000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.814600                       # mshr miss rate for UpgradeReq accesses
@@ -1052,11 +1032,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      4855602                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425060                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        11070                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1228,26 +1205,26 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide          842
 system.iocache.ReadReq_misses::total              842                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          842                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               842                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          842                       # number of overall misses
-system.iocache.overall_misses::total              842                       # number of overall misses
+system.iocache.demand_misses::pc.south_bridge.ide        47562                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47562                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47562                       # number of overall misses
+system.iocache.overall_misses::total            47562                       # number of overall misses
 system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    138525690                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total    138525690                       # number of ReadReq miss cycles
 system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5867864184                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total   5867864184                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    138525690                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    138525690                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    138525690                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    138525690                       # number of overall miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   6006389874                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   6006389874                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   6006389874                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   6006389874                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          842                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            842                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          842                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             842                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          842                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            842                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47562                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47562                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47562                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47562                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1260,36 +1237,34 @@ system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853
 system.iocache.ReadReq_avg_miss_latency::total 164519.821853                       # average ReadReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 164519.821853                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 164519.821853                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126285.477356                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126285.477356                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs           428                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   33                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs    12.969697                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          842                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          842                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          842                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          842                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          842                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          842                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47562                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47562                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47562                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47562                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96425690                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     96425690                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3530059456                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   3530059456                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     96425690                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     96425690                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     96425690                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     96425690                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3626485146                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3626485146                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3626485146                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3626485146                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1302,11 +1277,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853
 system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853                       # average ReadReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 114519.821853                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 114519.821853                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76247.532610                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76247.532610                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq              546346                       # Transaction distribution
 system.membus.trans_dist::ReadResp             588523                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13920                       # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 39184c503..0faba0dc5 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000037                       # Nu
 sim_ticks                                    37494000                       # Number of ticks simulated
 final_tick                                   37494000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 257461                       # Simulator instruction rate (inst/s)
-host_op_rate                                   257361                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1504149892                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 141195                       # Simulator instruction rate (inst/s)
+host_op_rate                                   141164                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              825166364                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 252900                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        6413                       # Number of instructions simulated
 sim_ops                                          6413                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -412,8 +412,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
@@ -454,7 +452,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           175.312988                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                2323                       # Total number of references to valid blocks.
@@ -512,8 +509,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          364                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          364                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          364                       # number of demand (read+write) MSHR misses
@@ -538,7 +533,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780
 system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          233.336913                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -628,8 +622,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          363                       # number of ReadCleanReq MSHR misses
@@ -678,7 +670,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          533                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index c617feb20..c082db4f6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000022                       # Nu
 sim_ticks                                    22019000                       # Number of ticks simulated
 final_tick                                   22019000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66596                       # Simulator instruction rate (inst/s)
-host_op_rate                                    66584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              229093695                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228860                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                 140516                       # Simulator instruction rate (inst/s)
+host_op_rate                                   140486                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              484379589                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253664                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        6385                       # Number of instructions simulated
 sim_ops                                          6385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -656,8 +656,6 @@ system.cpu.dcache.blocked::no_mshrs                43                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    56.348837                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           79                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          287                       # number of WriteReq MSHR hits
@@ -698,7 +696,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           158.432951                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1836                       # Total number of references to valid blocks.
@@ -756,8 +753,6 @@ system.cpu.icache.blocked::no_mshrs                 1                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs           54                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          144                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          144                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst          144                       # number of demand (read+write) MSHR hits
@@ -788,7 +783,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182
 system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          220.994877                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -878,8 +872,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           72                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           72                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          312                       # number of ReadCleanReq MSHR misses
@@ -928,7 +920,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          486                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 9846d6881..1dfe1dcb3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000036                       # Nu
 sim_ticks                                    35682500                       # Number of ticks simulated
 final_tick                                   35682500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  44587                       # Simulator instruction rate (inst/s)
-host_op_rate                                    44581                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              248411942                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226904                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                 421865                       # Simulator instruction rate (inst/s)
+host_op_rate                                   421312                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2345119890                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251096                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        6403                       # Number of instructions simulated
 sim_ops                                          6403                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -190,8 +190,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
@@ -224,7 +222,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           127.232065                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6135                       # Total number of references to valid blocks.
@@ -282,8 +279,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          279                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
@@ -308,7 +303,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          184.000496                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
@@ -448,7 +440,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          447                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 8e060c84e..165263111 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    20320000                       # Number of ticks simulated
 final_tick                                   20320000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31344                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31334                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              243267003                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230348                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                 183657                       # Simulator instruction rate (inst/s)
+host_op_rate                                   183501                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1441333472                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251592                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -412,8 +412,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            3                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           16                       # number of WriteReq MSHR hits
@@ -454,7 +452,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        76000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        76000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        76000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        76000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           119.123012                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 750                       # Total number of references to valid blocks.
@@ -512,8 +509,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          225                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          225                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          225                       # number of demand (read+write) MSHR misses
@@ -538,7 +533,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75457.777778
 system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          147.162900                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
@@ -622,8 +616,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          225                       # number of ReadCleanReq MSHR misses
@@ -672,7 +664,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64103.225806
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63957.777778                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64488.235294                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64103.225806                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          310                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 619c657d2..86178d83d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12409500                       # Number of ticks simulated
 final_tick                                   12409500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  12168                       # Simulator instruction rate (inst/s)
-host_op_rate                                    12166                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63007670                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231556                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  67215                       # Simulator instruction rate (inst/s)
+host_op_rate                                    67181                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              349098234                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252356                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -655,8 +655,6 @@ system.cpu.dcache.blocked::no_mshrs                 6                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    42.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           40                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
@@ -697,7 +695,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse            90.399218                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 625                       # Total number of references to valid blocks.
@@ -755,8 +752,6 @@ system.cpu.icache.blocked::no_mshrs                 2                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    62.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           66                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst           66                       # number of demand (read+write) MSHR hits
@@ -787,7 +782,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583
 system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          119.261302                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
@@ -871,8 +865,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           24                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           24                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          187                       # number of ReadCleanReq MSHR misses
@@ -921,7 +913,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          272                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 42abe9c49..3011688bd 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    18239500                       # Number of ticks simulated
 final_tick                                   18239500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29160                       # Simulator instruction rate (inst/s)
-host_op_rate                                    29152                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              206272099                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229424                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                 277034                       # Simulator instruction rate (inst/s)
+host_op_rate                                   276552                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1954350939                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249792                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -190,8 +190,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           27                       # number of WriteReq MSHR misses
@@ -224,7 +222,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse            79.677134                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                2423                       # Total number of references to valid blocks.
@@ -282,8 +279,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          163                       # number of demand (read+write) MSHR misses
@@ -308,7 +303,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485
 system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          106.649585                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
@@ -392,8 +386,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          163                       # number of ReadCleanReq MSHR misses
@@ -442,7 +434,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          245                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 02dbcdc04..cb66660d4 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000030                       # Nu
 sim_ticks                                    29977500                       # Number of ticks simulated
 final_tick                                   29977500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 167534                       # Simulator instruction rate (inst/s)
-host_op_rate                                   196036                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1088591965                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269228                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  89930                       # Simulator instruction rate (inst/s)
+host_op_rate                                   105235                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              584953104                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 268772                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -504,8 +504,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           24                       # number of WriteReq MSHR hits
@@ -546,7 +544,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 4                       # number of replacements
 system.cpu.icache.tags.tagsinuse           162.122030                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1926                       # Total number of references to valid blocks.
@@ -604,8 +601,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            4                       # number of writebacks
 system.cpu.icache.writebacks::total                 4                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          323                       # number of ReadReq MSHR misses
@@ -632,7 +627,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214
 system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          195.781809                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 43                       # Total number of references to valid blocks.
@@ -730,8 +724,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            8                       # number of demand (read+write) MSHR hits
@@ -786,7 +778,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          473                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           51                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index b78b358b1..58e5912c9 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    17232500                       # Number of ticks simulated
 final_tick                                   17232500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   9367                       # Simulator instruction rate (inst/s)
-host_op_rate                                    10970                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35022410                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245324                       # Number of bytes of host memory used
-host_seconds                                     0.49                       # Real time elapsed on the host
+host_inst_rate                                  43939                       # Simulator instruction rate (inst/s)
+host_op_rate                                    51450                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              164826819                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269540                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -878,8 +878,6 @@ system.cpu.dcache.blocked::no_mshrs                 3                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.333333                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           78                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          274                       # number of WriteReq MSHR hits
@@ -922,7 +920,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 2                       # number of replacements
 system.cpu.icache.tags.tagsinuse           150.405898                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1577                       # Total number of references to valid blocks.
@@ -980,8 +977,6 @@ system.cpu.icache.blocked::no_mshrs                 5                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    84.600000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            2                       # number of writebacks
 system.cpu.icache.writebacks::total                 2                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           90                       # number of ReadReq MSHR hits
@@ -1014,7 +1009,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388
 system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          187.999052                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 39                       # Total number of references to valid blocks.
@@ -1112,8 +1106,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            6                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
@@ -1168,7 +1160,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        69000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          443                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           45                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index a846c7a0c..d43357405 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18821000                       # Number of ticks simulated
 final_tick                                   18821000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   9099                       # Simulator instruction rate (inst/s)
-host_op_rate                                    10656                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               37131488                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241712                       # Number of bytes of host memory used
-host_seconds                                     0.50                       # Real time elapsed on the host
+host_inst_rate                                  49791                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58299                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              203978556                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266084                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -759,8 +759,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets              18                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    45.444444                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.dcache.writebacks::total                 1                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           64                       # number of ReadReq MSHR hits
@@ -805,7 +803,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                44                       # number of replacements
 system.cpu.icache.tags.tagsinuse           137.890102                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                3540                       # Total number of references to valid blocks.
@@ -863,8 +860,6 @@ system.cpu.icache.blocked::no_mshrs                95                       # nu
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    88.568421                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           33                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           44                       # number of writebacks
 system.cpu.icache.writebacks::total                44                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           62                       # number of ReadReq MSHR hits
@@ -897,7 +892,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472
 system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued          112                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified          112                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
@@ -1007,8 +1001,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            5                       # number of ReadSharedReq MSHR hits
@@ -1079,7 +1071,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          488                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           74                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests           12                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 83487a6ff..facfa8248 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28298500                       # Number of ticks simulated
 final_tick                                   28298500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 286813                       # Simulator instruction rate (inst/s)
-host_op_rate                                   333728                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1769783602                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267436                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 441317                       # Simulator instruction rate (inst/s)
+host_op_rate                                   514292                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2726097982                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267744                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4566                       # Number of instructions simulated
 sim_ops                                          5330                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -284,8 +284,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           98                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           98                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
@@ -318,7 +316,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           114.043293                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4365                       # Total number of references to valid blocks.
@@ -376,8 +373,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.icache.writebacks::total                 1                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          241                       # number of ReadReq MSHR misses
@@ -404,7 +399,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585
 system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          153.328645                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 32                       # Total number of references to valid blocks.
@@ -498,8 +492,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          225                       # number of ReadCleanReq MSHR misses
@@ -548,7 +540,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          383                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           32                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 69eab7f94..815eb0bfe 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000023                       # Nu
 sim_ticks                                    22532000                       # Number of ticks simulated
 final_tick                                   22532000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 106399                       # Simulator instruction rate (inst/s)
-host_op_rate                                   106364                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              479269632                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251364                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  65525                       # Simulator instruction rate (inst/s)
+host_op_rate                                    65509                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              295199371                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251356                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4999                       # Number of instructions simulated
 sim_ops                                          4999                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -640,8 +640,6 @@ system.cpu.dcache.blocked::no_mshrs                10                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    59.200000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           77                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          295                       # number of WriteReq MSHR hits
@@ -682,7 +680,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                17                       # number of replacements
 system.cpu.icache.tags.tagsinuse           158.780297                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1610                       # Total number of references to valid blocks.
@@ -740,8 +737,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           17                       # number of writebacks
 system.cpu.icache.writebacks::total                17                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          105                       # number of ReadReq MSHR hits
@@ -774,7 +769,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687
 system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          218.003826                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 20                       # Total number of references to valid blocks.
@@ -868,8 +862,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          329                       # number of ReadCleanReq MSHR misses
@@ -918,7 +910,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          489                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           17                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index dc14a2b12..f975f616d 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000034                       # Nu
 sim_ticks                                    33932500                       # Number of ticks simulated
 final_tick                                   33932500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42153                       # Simulator instruction rate (inst/s)
-host_op_rate                                    42149                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              253513577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224784                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                 442497                       # Simulator instruction rate (inst/s)
+host_op_rate                                   441783                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2653552582                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249064                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -176,8 +176,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
@@ -210,7 +208,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                13                       # number of replacements
 system.cpu.icache.tags.tagsinuse           128.953338                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5348                       # Total number of references to valid blocks.
@@ -268,8 +265,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           13                       # number of writebacks
 system.cpu.icache.writebacks::total                13                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          295                       # number of ReadReq MSHR misses
@@ -296,7 +291,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          183.490494                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 15                       # Total number of references to valid blocks.
@@ -390,8 +384,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          293                       # number of ReadCleanReq MSHR misses
@@ -440,7 +432,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          445                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           13                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 70134ae11..2c6934aef 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19908000                       # Number of ticks simulated
 final_tick                                   19908000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56421                       # Simulator instruction rate (inst/s)
-host_op_rate                                    56413                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              194020204                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225060                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                 130311                       # Simulator instruction rate (inst/s)
+host_op_rate                                   130281                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              447700777                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249300                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -641,8 +641,6 @@ system.cpu.dcache.blocked::no_mshrs                 6                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    99.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          277                       # number of WriteReq MSHR hits
@@ -683,7 +681,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           169.073673                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1420                       # Total number of references to valid blocks.
@@ -741,8 +738,6 @@ system.cpu.icache.blocked::no_mshrs                 5                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    99.400000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           86                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst           86                       # number of demand (read+write) MSHR hits
@@ -773,7 +768,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286
 system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          199.665471                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  8                       # Total number of references to valid blocks.
@@ -867,8 +861,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           47                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           47                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          344                       # number of ReadCleanReq MSHR misses
@@ -917,7 +909,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          454                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            8                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index a5edc52b5..ddd387c47 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30526500                       # Number of ticks simulated
 final_tick                                   30526500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  33063                       # Simulator instruction rate (inst/s)
-host_op_rate                                    33056                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              189395194                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228956                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                 608531                       # Simulator instruction rate (inst/s)
+host_op_rate                                   607803                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3479427932                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249516                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -158,8 +158,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           54                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           81                       # number of WriteReq MSHR misses
@@ -192,7 +190,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           116.865384                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5114                       # Total number of references to valid blocks.
@@ -250,8 +247,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          257                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          257                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          257                       # number of demand (read+write) MSHR misses
@@ -276,7 +271,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          141.950442                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
@@ -370,8 +364,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           81                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           81                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          255                       # number of ReadCleanReq MSHR misses
@@ -420,7 +412,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          392                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            3                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 9accffb70..3c1544f1d 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21273500                       # Number of ticks simulated
 final_tick                                   21273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39176                       # Simulator instruction rate (inst/s)
-host_op_rate                                    70969                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              151562567                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245924                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  70008                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126817                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              276755373                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271684                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -625,8 +625,6 @@ system.cpu.dcache.blocked::no_mshrs                 3                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    40.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           51                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           51                       # number of ReadReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.data           51                       # number of demand (read+write) MSHR hits
@@ -665,7 +663,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           130.801873                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1651                       # Total number of references to valid blocks.
@@ -723,8 +720,6 @@ system.cpu.icache.blocked::no_mshrs                 3                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    47.333333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          107                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          107                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst          107                       # number of demand (read+write) MSHR hits
@@ -755,7 +750,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065
 system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          163.058861                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -845,8 +839,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           75                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           75                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          277                       # number of ReadCleanReq MSHR misses
@@ -895,7 +887,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          417                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 79b38ccd2..b345a9c01 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30886500                       # Number of ticks simulated
 final_tick                                   30886500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  79759                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144442                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              457524996                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247116                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 235920                       # Simulator instruction rate (inst/s)
+host_op_rate                                   427054                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1352150005                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266824                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -161,8 +161,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           79                       # number of WriteReq MSHR misses
@@ -195,7 +193,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           105.267613                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6636                       # Total number of references to valid blocks.
@@ -253,8 +250,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          228                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          228                       # number of demand (read+write) MSHR misses
@@ -279,7 +274,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          133.672095                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -369,8 +363,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           79                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           79                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          227                       # number of ReadCleanReq MSHR misses
@@ -419,7 +411,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          362                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
index ffcf45f3b..fcca5b721 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    25580500                       # Number of ticks simulated
 final_tick                                   25580500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  50796                       # Simulator instruction rate (inst/s)
-host_op_rate                                    50792                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               98611945                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229596                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
+host_inst_rate                                  85448                       # Simulator instruction rate (inst/s)
+host_op_rate                                    85436                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              171120344                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253996                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                       12770                       # Number of instructions simulated
 sim_ops                                         12770                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -799,8 +799,6 @@ system.cpu.dcache.blocked::no_mshrs               130                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.976923                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          103                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          103                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          566                       # number of WriteReq MSHR hits
@@ -841,7 +839,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements::0              7                       # number of replacements
 system.cpu.icache.tags.replacements::1              0                       # number of replacements
 system.cpu.icache.tags.replacements::total            7                       # number of replacements
@@ -901,8 +898,6 @@ system.cpu.icache.blocked::no_mshrs                55                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    56.054545                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            7                       # number of writebacks
 system.cpu.icache.writebacks::total                 7                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          280                       # number of ReadReq MSHR hits
@@ -935,7 +930,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061
 system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
@@ -1031,8 +1025,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          620                       # number of ReadCleanReq MSHR misses
@@ -1081,7 +1073,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          972                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            9                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index d7b61e924..e76497684 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000029                       # Nu
 sim_ticks                                    28845500                       # Number of ticks simulated
 final_tick                                   28845500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  12271                       # Simulator instruction rate (inst/s)
-host_op_rate                                    12271                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               22902062                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227268                       # Number of bytes of host memory used
-host_seconds                                     1.18                       # Real time elapsed on the host
+host_inst_rate                                  68981                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68975                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              137812851                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251992                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -621,8 +621,6 @@ system.cpu.dcache.blocked::no_mshrs                23                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    57.086957                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           75                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
@@ -663,7 +661,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           206.414108                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6949                       # Total number of references to valid blocks.
@@ -721,8 +718,6 @@ system.cpu.icache.blocked::no_mshrs                 2                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs           95                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          216                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          216                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst          216                       # number of demand (read+write) MSHR hits
@@ -753,7 +748,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219
 system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          240.923513                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
@@ -843,8 +837,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          363                       # number of ReadCleanReq MSHR misses
@@ -893,7 +885,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          513                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            2                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 256c5877f..457c52bd3 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000044                       # Nu
 sim_ticks                                    44282500                       # Number of ticks simulated
 final_tick                                   44282500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  17930                       # Simulator instruction rate (inst/s)
-host_op_rate                                    17930                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52364992                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228848                       # Number of bytes of host memory used
-host_seconds                                     0.85                       # Real time elapsed on the host
+host_inst_rate                                 298703                       # Simulator instruction rate (inst/s)
+host_op_rate                                   298583                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              871748609                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249440                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -162,8 +162,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
@@ -196,7 +194,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           151.748662                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs               14928                       # Total number of references to valid blocks.
@@ -254,8 +251,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          280                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          280                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          280                       # number of demand (read+write) MSHR misses
@@ -280,7 +275,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          182.297739                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
@@ -370,8 +364,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
@@ -420,7 +412,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          418                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            2                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
index b37d8b5b7..3c13d46b0 100644
--- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000061                       # Nu
 sim_ticks                                    61470000                       # Number of ticks simulated
 final_tick                                   61470000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  62593                       # Simulator instruction rate (inst/s)
-host_op_rate                                    62569                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              595804848                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 614668                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                 583425                       # Simulator instruction rate (inst/s)
+host_op_rate                                   580281                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5518802940                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 637904                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        6453                       # Number of instructions simulated
 sim_ops                                          6453                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -409,8 +409,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
@@ -443,7 +441,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                62                       # number of replacements
 system.cpu.icache.tags.tagsinuse           113.715440                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6183                       # Total number of references to valid blocks.
@@ -501,8 +498,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          281                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          281                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          281                       # number of demand (read+write) MSHR misses
@@ -527,7 +522,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609
 system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.l2bus.snoop_filter.tot_requests            511                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           63                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -647,8 +641,6 @@ system.l2cache.blocked::no_mshrs                    0                       # nu
 system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2cache.fast_writes                          0                       # number of fast writes performed
-system.l2cache.cache_copies                         0                       # number of cache copies performed
 system.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
 system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          278                       # number of ReadSharedReq MSHR misses
@@ -693,7 +685,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408
 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408                       # average overall mshr miss latency
-system.l2cache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                373                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
index f933f7176..60d51d141 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000050                       # Nu
 sim_ticks                                    49855000                       # Number of ticks simulated
 final_tick                                   49855000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 411650                       # Simulator instruction rate (inst/s)
-host_op_rate                                   475781                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4107877451                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 655016                       # Number of bytes of host memory used
+host_inst_rate                                 523400                       # Simulator instruction rate (inst/s)
+host_op_rate                                   604831                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5220928914                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 655332                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
@@ -503,8 +503,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           99                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           99                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
@@ -537,7 +535,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                70                       # number of replacements
 system.cpu.icache.tags.tagsinuse            96.468360                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4779                       # Total number of references to valid blocks.
@@ -595,8 +592,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          249                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          249                       # number of demand (read+write) MSHR misses
@@ -621,7 +616,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321
 system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.l2bus.snoop_filter.tot_requests            461                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           94                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests           10                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -744,8 +738,6 @@ system.l2cache.blocked::no_mshrs                    0                       # nu
 system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2cache.fast_writes                          0                       # number of fast writes performed
-system.l2cache.cache_copies                         0                       # number of cache copies performed
 system.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
 system.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
 system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          225                       # number of ReadSharedReq MSHR misses
@@ -790,7 +782,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114
 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114                       # average overall mshr miss latency
-system.l2cache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                308                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
index c1870ce65..2c65c222a 100644
--- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000059                       # Nu
 sim_ticks                                    58892000                       # Number of ticks simulated
 final_tick                                   58892000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  44023                       # Simulator instruction rate (inst/s)
-host_op_rate                                    44007                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              459268108                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 612532                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                 350541                       # Simulator instruction rate (inst/s)
+host_op_rate                                   350101                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3650563038                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 636120                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5641                       # Number of instructions simulated
 sim_ops                                          5641                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -395,8 +395,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
@@ -429,7 +427,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                94                       # number of replacements
 system.cpu.icache.tags.tagsinuse           110.145403                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5346                       # Total number of references to valid blocks.
@@ -487,8 +484,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          297                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          297                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          297                       # number of demand (read+write) MSHR misses
@@ -513,7 +508,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785
 system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.l2bus.snoop_filter.tot_requests            528                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           94                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -633,8 +627,6 @@ system.l2cache.blocked::no_mshrs                    0                       # nu
 system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2cache.fast_writes                          0                       # number of fast writes performed
-system.l2cache.cache_copies                         0                       # number of cache copies performed
 system.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
 system.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
 system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          293                       # number of ReadSharedReq MSHR misses
@@ -679,7 +671,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814
 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814                       # average overall mshr miss latency
-system.l2cache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                380                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
index 010db5b17..718f7b51e 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000053                       # Nu
 sim_ticks                                    53334000                       # Number of ticks simulated
 final_tick                                   53334000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 486070                       # Simulator instruction rate (inst/s)
-host_op_rate                                   485474                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4661655450                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 680524                       # Number of bytes of host memory used
+host_inst_rate                                 388058                       # Simulator instruction rate (inst/s)
+host_op_rate                                   387570                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3721714769                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 636836                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
@@ -382,8 +382,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           56                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           56                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           82                       # number of WriteReq MSHR misses
@@ -416,7 +414,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                71                       # number of replacements
 system.cpu.icache.tags.tagsinuse            98.062907                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                5333                       # Total number of references to valid blocks.
@@ -474,8 +471,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          259                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          259                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          259                       # number of demand (read+write) MSHR misses
@@ -500,7 +495,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154
 system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.l2bus.snoop_filter.tot_requests            468                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           73                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -623,8 +617,6 @@ system.l2cache.blocked::no_mshrs                    0                       # nu
 system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2cache.fast_writes                          0                       # number of fast writes performed
-system.l2cache.cache_copies                         0                       # number of cache copies performed
 system.l2cache.ReadExReq_mshr_misses::cpu.data           82                       # number of ReadExReq MSHR misses
 system.l2cache.ReadExReq_mshr_misses::total           82                       # number of ReadExReq MSHR misses
 system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          257                       # number of ReadSharedReq MSHR misses
@@ -669,7 +661,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325
 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325                       # average overall mshr miss latency
-system.l2cache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                312                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                82                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               82                       # Transaction distribution
diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
index 5f983df7d..e0706d7d4 100644
--- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000056                       # Nu
 sim_ticks                                    55844000                       # Number of ticks simulated
 final_tick                                   55844000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  84620                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152747                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              826790083                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 634592                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 250477                       # Simulator instruction rate (inst/s)
+host_op_rate                                   451948                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2445398371                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 655164                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5712                       # Number of instructions simulated
 sim_ops                                         10314                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -381,8 +381,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           56                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           56                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           79                       # number of WriteReq MSHR misses
@@ -415,7 +413,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                58                       # number of replacements
 system.cpu.icache.tags.tagsinuse            91.239705                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                7048                       # Total number of references to valid blocks.
@@ -473,8 +470,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          235                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          235                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          235                       # number of demand (read+write) MSHR misses
@@ -499,7 +494,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468
 system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.l2bus.snoop_filter.tot_requests            428                       # Total number of requests made to the snoop filter.
 system.l2bus.snoop_filter.hit_single_requests           59                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -619,8 +613,6 @@ system.l2cache.blocked::no_mshrs                    0                       # nu
 system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2cache.fast_writes                          0                       # number of fast writes performed
-system.l2cache.cache_copies                         0                       # number of cache copies performed
 system.l2cache.ReadExReq_mshr_misses::cpu.data           79                       # number of ReadExReq MSHR misses
 system.l2cache.ReadExReq_mshr_misses::total           79                       # number of ReadExReq MSHR misses
 system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          229                       # number of ReadSharedReq MSHR misses
@@ -665,7 +657,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374
 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074                       # average overall mshr miss latency
 system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374                       # average overall mshr miss latency
-system.l2cache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                285                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                79                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               79                       # Transaction distribution
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 7b63e03f4..93c64ae72 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.147149                       # Nu
 sim_ticks                                147148719500                       # Number of ticks simulated
 final_tick                               147148719500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1174056                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1179890                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1907338487                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 402756                       # Number of bytes of host memory used
-host_seconds                                    77.15                       # Real time elapsed on the host
+host_inst_rate                                1067474                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1072778                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1734188097                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 402040                       # Number of bytes of host memory used
+host_seconds                                    84.85                       # Real time elapsed on the host
 sim_insts                                    90576862                       # Number of instructions simulated
 sim_ops                                      91026991                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -294,8 +294,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       942334                       # number of writebacks
 system.cpu.dcache.writebacks::total            942334                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
@@ -344,7 +342,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 2                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.111710                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           107830173                       # Total number of references to valid blocks.
@@ -404,8 +401,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            2                       # number of writebacks
 system.cpu.icache.writebacks::total                 2                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
@@ -432,7 +427,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710
 system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         9564.658425                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1827433                       # Total number of references to valid blocks.
@@ -541,8 +535,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14548                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14548                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          577                       # number of ReadCleanReq MSHR misses
@@ -591,7 +583,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1890101                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       942715                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          114                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index a8bc405b3..d612f6415 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000126                       # Nu
 sim_ticks                                   125889000                       # Number of ticks simulated
 final_tick                                  125889000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 271253                       # Simulator instruction rate (inst/s)
-host_op_rate                                   271253                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               29155299                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267160                       # Number of bytes of host memory used
-host_seconds                                     4.32                       # Real time elapsed on the host
+host_inst_rate                                 196054                       # Simulator instruction rate (inst/s)
+host_op_rate                                   196054                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               21072637                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267156                       # Number of bytes of host memory used
+host_seconds                                     5.97                       # Real time elapsed on the host
 sim_insts                                     1171234                       # Number of instructions simulated
 sim_ops                                       1171234                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -666,8 +666,6 @@ system.cpu0.dcache.blocked::no_mshrs               22                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs    37.181818                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          380                       # number of ReadReq MSHR hits
@@ -718,7 +716,6 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227
 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227                       # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              403                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          251.059263                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs               7130                       # Total number of references to valid blocks.
@@ -777,8 +774,6 @@ system.cpu0.icache.blocked::no_mshrs                4                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs    28.250000                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks          403                       # number of writebacks
 system.cpu0.icache.writebacks::total              403                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          215                       # number of ReadReq MSHR hits
@@ -811,7 +806,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932
 system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.branchPred.lookups                  75929                       # Number of BP lookups
 system.cpu1.branchPred.condPredicted            68631                       # Number of conditional branches predicted
 system.cpu1.branchPred.condIncorrect             2222                       # Number of conditional branches incorrect
@@ -1193,8 +1187,6 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          362                       # number of ReadReq MSHR hits
 system.cpu1.dcache.ReadReq_mshr_hits::total          362                       # number of ReadReq MSHR hits
 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           43                       # number of WriteReq MSHR hits
@@ -1243,7 +1235,6 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985
 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985                       # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              548                       # number of replacements
 system.cpu1.icache.tags.tagsinuse           97.609803                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs              21265                       # Total number of references to valid blocks.
@@ -1302,8 +1293,6 @@ system.cpu1.icache.blocked::no_mshrs                1                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks          548                       # number of writebacks
 system.cpu1.icache.writebacks::total              548                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst          144                       # number of ReadReq MSHR hits
@@ -1336,7 +1325,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191
 system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.branchPred.lookups                  65577                       # Number of BP lookups
 system.cpu2.branchPred.condPredicted            57724                       # Number of conditional branches predicted
 system.cpu2.branchPred.condIncorrect             2464                       # Number of conditional branches incorrect
@@ -1721,8 +1709,6 @@ system.cpu2.dcache.blocked::no_mshrs                0                       # nu
 system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          298                       # number of ReadReq MSHR hits
 system.cpu2.dcache.ReadReq_mshr_hits::total          298                       # number of ReadReq MSHR hits
 system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           47                       # number of WriteReq MSHR hits
@@ -1773,7 +1759,6 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074
 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074                       # average overall mshr miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074                       # average overall mshr miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074                       # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.icache.tags.replacements              555                       # number of replacements
 system.cpu2.icache.tags.tagsinuse          101.261159                       # Cycle average of tags in use
 system.cpu2.icache.tags.total_refs              26702                       # Total number of references to valid blocks.
@@ -1832,8 +1817,6 @@ system.cpu2.icache.blocked::no_mshrs                7                       # nu
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_mshrs    31.428571                       # average number of cycles each access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.writebacks::writebacks          555                       # number of writebacks
 system.cpu2.icache.writebacks::total              555                       # number of writebacks
 system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst          149                       # number of ReadReq MSHR hits
@@ -1866,7 +1849,6 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331
 system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331                       # average overall mshr miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331                       # average overall mshr miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331                       # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.branchPred.lookups                  57182                       # Number of BP lookups
 system.cpu3.branchPred.condPredicted            48797                       # Number of conditional branches predicted
 system.cpu3.branchPred.condIncorrect             2586                       # Number of conditional branches incorrect
@@ -2248,8 +2230,6 @@ system.cpu3.dcache.blocked::no_mshrs                0                       # nu
 system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          291                       # number of ReadReq MSHR hits
 system.cpu3.dcache.ReadReq_mshr_hits::total          291                       # number of ReadReq MSHR hits
 system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           35                       # number of WriteReq MSHR hits
@@ -2300,7 +2280,6 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209
 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209                       # average overall mshr miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209                       # average overall mshr miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209                       # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.icache.tags.replacements              608                       # number of replacements
 system.cpu3.icache.tags.tagsinuse           93.738869                       # Cycle average of tags in use
 system.cpu3.icache.tags.total_refs              33506                       # Total number of references to valid blocks.
@@ -2359,8 +2338,6 @@ system.cpu3.icache.blocked::no_mshrs                0                       # nu
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.writebacks::writebacks          608                       # number of writebacks
 system.cpu3.icache.writebacks::total              608                       # number of writebacks
 system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst          128                       # number of ReadReq MSHR hits
@@ -2393,7 +2370,6 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428
 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428                       # average overall mshr miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428                       # average overall mshr miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428                       # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
 system.l2c.tags.tagsinuse                  458.562207                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       3097                       # Total number of references to valid blocks.
@@ -2650,8 +2626,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            8                       # number of ReadCleanReq MSHR hits
@@ -2819,7 +2793,6 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619
 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        77375                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::total 70071.328671                       # average overall mshr miss latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                583                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              286                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               182                       # Transaction distribution
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 1d3cbd064..f2280533e 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1830828                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1830758                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              237054275                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306784                       # Number of bytes of host memory used
-host_seconds                                     0.37                       # Real time elapsed on the host
+host_inst_rate                                1039500                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1039462                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              134594380                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262812                       # Number of bytes of host memory used
+host_seconds                                     0.65                       # Real time elapsed on the host
 sim_insts                                      677333                       # Number of instructions simulated
 sim_ops                                        677333                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -180,11 +180,8 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              215                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          222.772732                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs             174921                       # Total number of references to valid blocks.
@@ -230,11 +227,8 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks          215                       # number of writebacks
 system.cpu0.icache.writebacks::total              215                       # number of writebacks
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                          173297                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -353,9 +347,6 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              278                       # number of replacements
 system.cpu1.icache.tags.tagsinuse           76.752158                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs             167074                       # Total number of references to valid blocks.
@@ -401,11 +392,8 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks          278                       # number of writebacks
 system.cpu1.icache.writebacks::total              278                       # number of writebacks
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.numCycles                          173296                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -525,9 +513,6 @@ system.cpu2.dcache.blocked::no_mshrs                0                       # nu
 system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.icache.tags.replacements              278                       # number of replacements
 system.cpu2.icache.tags.tagsinuse           74.781471                       # Cycle average of tags in use
 system.cpu2.icache.tags.total_refs             167009                       # Total number of references to valid blocks.
@@ -573,11 +558,8 @@ system.cpu2.icache.blocked::no_mshrs                0                       # nu
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.writebacks::writebacks          278                       # number of writebacks
 system.cpu2.icache.writebacks::total              278                       # number of writebacks
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.numCycles                          173297                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -696,9 +678,6 @@ system.cpu3.dcache.blocked::no_mshrs                0                       # nu
 system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.icache.tags.replacements              279                       # number of replacements
 system.cpu3.icache.tags.tagsinuse           72.874953                       # Cycle average of tags in use
 system.cpu3.icache.tags.total_refs             166945                       # Total number of references to valid blocks.
@@ -744,11 +723,8 @@ system.cpu3.icache.blocked::no_mshrs                0                       # nu
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.writebacks::writebacks          279                       # number of writebacks
 system.cpu3.icache.writebacks::total              279                       # number of writebacks
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
 system.l2c.tags.tagsinuse                  367.545675                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1716                       # Total number of references to valid blocks.
@@ -938,9 +914,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                423                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              273                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp              80                       # Transaction distribution
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index eb0bc0573..22d94928b 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000264                       # Nu
 sim_ticks                                   263565500                       # Number of ticks simulated
 final_tick                                  263565500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 798172                       # Simulator instruction rate (inst/s)
-host_op_rate                                   798158                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              317271660                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306776                       # Number of bytes of host memory used
-host_seconds                                     0.83                       # Real time elapsed on the host
+host_inst_rate                                 821706                       # Simulator instruction rate (inst/s)
+host_op_rate                                   821692                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              326627282                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262816                       # Number of bytes of host memory used
+host_seconds                                     0.81                       # Real time elapsed on the host
 sim_insts                                      663039                       # Number of instructions simulated
 sim_ops                                        663039                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,8 +200,6 @@ system.cpu0.dcache.blocked::no_mshrs                0                       # nu
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          168                       # number of ReadReq MSHR misses
@@ -244,7 +242,6 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627
 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627                       # average overall mshr miss latency
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              215                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          211.380247                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs             157792                       # Total number of references to valid blocks.
@@ -302,8 +299,6 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks::writebacks          215                       # number of writebacks
 system.cpu0.icache.writebacks::total              215                       # number of writebacks
 system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
@@ -330,7 +325,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994
 system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994                       # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                          527130                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -470,8 +464,6 @@ system.cpu1.dcache.blocked::no_mshrs                0                       # nu
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          167                       # number of ReadReq MSHR misses
 system.cpu1.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
 system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          105                       # number of WriteReq MSHR misses
@@ -512,7 +504,6 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059
 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059                       # average overall mshr miss latency
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              280                       # number of replacements
 system.cpu1.icache.tags.tagsinuse           66.953040                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs             170457                       # Total number of references to valid blocks.
@@ -571,8 +562,6 @@ system.cpu1.icache.blocked::no_mshrs                0                       # nu
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks          280                       # number of writebacks
 system.cpu1.icache.writebacks::total              280                       # number of writebacks
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
@@ -599,7 +588,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727
 system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727                       # average overall mshr miss latency
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.numCycles                          527130                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -739,8 +727,6 @@ system.cpu2.dcache.blocked::no_mshrs                0                       # nu
 system.cpu2.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          170                       # number of ReadReq MSHR misses
 system.cpu2.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          104                       # number of WriteReq MSHR misses
@@ -781,7 +767,6 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248
 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248                       # average overall mshr miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248                       # average overall mshr miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248                       # average overall mshr miss latency
-system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.icache.tags.replacements              280                       # number of replacements
 system.cpu2.icache.tags.tagsinuse           69.363893                       # Cycle average of tags in use
 system.cpu2.icache.tags.total_refs             167911                       # Total number of references to valid blocks.
@@ -840,8 +825,6 @@ system.cpu2.icache.blocked::no_mshrs                0                       # nu
 system.cpu2.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.writebacks::writebacks          280                       # number of writebacks
 system.cpu2.icache.writebacks::total              280                       # number of writebacks
 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
@@ -868,7 +851,6 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776
 system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776                       # average overall mshr miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776                       # average overall mshr miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776                       # average overall mshr miss latency
-system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.numCycles                          527131                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -1008,8 +990,6 @@ system.cpu3.dcache.blocked::no_mshrs                0                       # nu
 system.cpu3.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          150                       # number of ReadReq MSHR misses
 system.cpu3.dcache.ReadReq_mshr_misses::total          150                       # number of ReadReq MSHR misses
 system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          109                       # number of WriteReq MSHR misses
@@ -1050,7 +1030,6 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946
 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946                       # average overall mshr miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946                       # average overall mshr miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946                       # average overall mshr miss latency
-system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.icache.tags.replacements              281                       # number of replacements
 system.cpu3.icache.tags.tagsinuse           64.942208                       # Cycle average of tags in use
 system.cpu3.icache.tags.total_refs             165475                       # Total number of references to valid blocks.
@@ -1109,8 +1088,6 @@ system.cpu3.icache.blocked::no_mshrs                0                       # nu
 system.cpu3.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.writebacks::writebacks          281                       # number of writebacks
 system.cpu3.icache.writebacks::total              281                       # number of writebacks
 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
@@ -1137,7 +1114,6 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937
 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937                       # average overall mshr miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average overall mshr miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937                       # average overall mshr miss latency
-system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
 system.l2c.tags.tagsinuse                  347.185045                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1714                       # Total number of references to valid blocks.
@@ -1393,8 +1369,6 @@ system.l2c.blocked::no_mshrs                        0                       # nu
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst           11                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            5                       # number of ReadCleanReq MSHR hits
@@ -1566,7 +1540,6 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818
 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        49500                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::total 49562.937063                       # average overall mshr miss latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                430                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              271                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 64e77dffe..30ddbd92e 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,1816 +1,1739 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000535                       # Number of seconds simulated
-sim_ticks                                   535115500                       # Number of ticks simulated
-final_tick                                  535115500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000502                       # Number of seconds simulated
+sim_ticks                                   501584000                       # Number of ticks simulated
+final_tick                                  501584000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              114251239                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237088                       # Number of bytes of host memory used
-host_seconds                                     4.68                       # Real time elapsed on the host
+host_tick_rate                              112049096                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235328                       # Number of bytes of host memory used
+host_seconds                                     4.48                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 81574                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 80110                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 79121                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 81238                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 80899                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 79820                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 79202                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 79066                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               641030                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       406208                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5473                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5509                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5540                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5388                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5404                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5375                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5435                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5475                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            449807                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  11077                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  10999                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10829                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  10993                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  11032                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  10961                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10910                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  11026                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 87827                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6347                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5473                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5509                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5540                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5388                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5404                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5375                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5435                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5475                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                49946                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                152441856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                149705998                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                147857799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                151813954                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                151180446                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                149164059                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                148009168                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                147755017                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1197928298                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         759103409                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                10227699                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                10294974                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                10352905                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                10068854                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                10098754                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                10044560                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                10156686                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                10231436                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              840579277                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         759103409                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               162669555                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               160000972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               158210704                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               161882808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               161279200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               159208619                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               158165854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               157986453                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2038507575                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 77173                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 79943                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 80467                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 80557                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 77449                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 81573                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 79541                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 76446                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               633149                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       399616                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5376                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5525                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5482                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5537                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5496                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5409                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5437                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5416                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            443294                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  10960                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10958                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  11104                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  10879                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  10858                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10887                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  10871                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10989                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87506                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6244                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5376                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5525                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5482                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5537                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5496                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5409                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5437                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5416                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                49922                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                153858576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                159381081                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                160425771                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                160605203                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                154408833                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                162630786                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                158579620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                152409168                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1262299037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         796708029                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                10718045                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                11015104                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                10929376                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                11039028                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                10957287                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                10783837                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                10839660                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                10797793                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              883788159                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         796708029                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               164576621                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               170396185                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               171355147                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               171644231                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               165366120                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               173414622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               169419280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               163206960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2146087196                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                          100000                       # number of read accesses completed
-system.cpu0.num_writes                          55271                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22387                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             391.751313                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13331                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22793                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.584873                       # Average number of references to valid blocks.
+system.cpu0.num_reads                           99682                       # number of read accesses completed
+system.cpu0.num_writes                          55240                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22392                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             393.390751                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13565                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22785                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.595348                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      391.751313                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.765139                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.765139                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          406                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          389                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              338274                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             338274                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8660                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8660                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1174                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1174                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9834                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9834                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9834                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9834                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36517                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36517                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23979                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23979                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60496                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60496                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60496                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60496                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    647463503                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    647463503                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    554640697                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    554640697                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1202104200                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1202104200                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1202104200                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1202104200                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          45177                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         45177                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         25153                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        25153                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           70330                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          70330                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          70330                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         70330                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.808310                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.808310                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.953326                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.953326                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.860173                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.860173                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.860173                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.860173                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17730.468083                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 17730.468083                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23130.268026                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 23130.268026                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 19870.804681                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 19870.804681                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 19870.804681                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 19870.804681                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs       749854                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      393.390751                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.768341                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.768341                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              339133                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             339133                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8847                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8847                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1120                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1120                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9967                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9967                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9967                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9967                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36618                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36618                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23969                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23969                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60587                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60587                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60587                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60587                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    672506192                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    672506192                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    563028530                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    563028530                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1235534722                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1235534722                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1235534722                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1235534722                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          45465                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         45465                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         25089                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        25089                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           70554                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          70554                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          70554                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         70554                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.805411                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.805411                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.955359                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.955359                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.858732                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.858732                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.858732                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.858732                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18365.453930                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 18365.453930                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23489.863157                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 23489.863157                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 20392.736429                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 20392.736429                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 20392.736429                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 20392.736429                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs       823442                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               59820                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               66357                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.535172                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.409271                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9840                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9840                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36517                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36517                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23979                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23979                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60496                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60496                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60496                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60496                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9959                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9959                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5475                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5475                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15434                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15434                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    610946503                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    610946503                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    530662697                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    530662697                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1141609200                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1141609200                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1141609200                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1141609200                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    751203683                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    751203683                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    933372844                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    933372844                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1684576527                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1684576527                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.808310                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.808310                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.953326                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.953326                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.860173                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.860173                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.860173                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.860173                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16730.468083                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16730.468083                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22130.309729                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22130.309729                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18870.821211                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18870.821211                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18870.821211                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18870.821211                       # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75429.629782                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75429.629782                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 170479.058265                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170479.058265                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109147.112025                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109147.112025                       # average overall mshr uncacheable latency
-system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           99085                       # number of read accesses completed
-system.cpu1.num_writes                          54836                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               22258                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             391.296117                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13378                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22654                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.590536                       # Average number of references to valid blocks.
+system.cpu0.l1c.writebacks::writebacks           9844                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9844                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36618                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36618                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23969                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23969                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60587                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60587                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60587                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60587                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9910                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9910                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5376                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5376                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15286                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15286                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    635888192                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    635888192                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    539061530                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    539061530                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1174949722                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1174949722                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1174949722                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1174949722                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    753971133                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    753971133                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0    753971133                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total    753971133                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.805411                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.805411                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.955359                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.955359                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.858732                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.858732                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.858732                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.858732                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17365.453930                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17365.453930                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22489.946598                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22489.946598                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19392.769439                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19392.769439                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19392.769439                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19392.769439                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 76081.849950                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76081.849950                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 49324.292359                       # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 49324.292359                       # average overall mshr uncacheable latency
+system.cpu1.num_reads                           99541                       # number of read accesses completed
+system.cpu1.num_writes                          55028                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22314                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             393.210618                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13573                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22722                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.597351                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      391.296117                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.764250                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.764250                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          396                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              336817                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             336817                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8647                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8647                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1131                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1131                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9778                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9778                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9778                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9778                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36589                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36589                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           23685                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          23685                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60274                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60274                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60274                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60274                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    652011208                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    652011208                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    548619495                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    548619495                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1200630703                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1200630703                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1200630703                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1200630703                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          45236                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         45236                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         24816                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        24816                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           70052                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          70052                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          70052                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         70052                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.808847                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.808847                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954425                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.954425                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.860418                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.860418                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.860418                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.860418                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17819.869578                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 17819.869578                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23163.162128                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 23163.162128                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 19919.545791                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 19919.545791                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 19919.545791                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 19919.545791                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs       748495                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      393.210618                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.767989                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.767989                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          408                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          399                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.796875                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              338638                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             338638                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8704                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8704                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1149                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1149                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9853                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9853                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9853                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9853                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36652                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36652                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23946                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23946                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60598                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60598                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60598                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60598                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    672762640                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    672762640                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    564762705                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    564762705                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1237525345                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1237525345                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1237525345                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1237525345                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45356                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45356                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         25095                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        25095                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70451                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70451                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70451                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70451                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.808096                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.808096                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954214                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.954214                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.860144                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.860144                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.860144                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.860144                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18355.414166                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 18355.414166                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23584.845277                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 23584.845277                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 20421.884303                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 20421.884303                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 20421.884303                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 20421.884303                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs       822356                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               59422                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               66159                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.596261                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.429994                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9809                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9809                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36589                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36589                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23685                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        23685                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60274                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60274                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60274                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60274                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9902                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9902                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5511                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5511                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15413                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15413                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    615423208                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    615423208                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    524934495                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    524934495                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1140357703                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1140357703                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1140357703                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1140357703                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    747152224                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    747152224                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    944376752                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    944376752                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1691528976                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1691528976                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.808847                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.808847                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954425                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954425                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860418                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.860418                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860418                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.860418                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16819.896909                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16819.896909                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22163.162128                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22163.162128                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18919.562382                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18919.562382                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18919.562382                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18919.562382                       # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 75454.678247                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75454.678247                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 171362.139721                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171362.139721                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 109746.900409                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 109746.900409                       # average overall mshr uncacheable latency
-system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99705                       # number of read accesses completed
-system.cpu2.num_writes                          55132                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22489                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             393.363987                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13472                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22889                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.588580                       # Average number of references to valid blocks.
+system.cpu1.l1c.writebacks::writebacks           9894                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9894                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36652                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36652                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23946                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23946                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60598                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60598                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60598                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60598                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9864                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9864                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5527                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5527                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15391                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15391                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    636111640                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    636111640                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    540817705                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    540817705                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1176929345                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1176929345                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1176929345                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1176929345                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    750538193                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    750538193                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1    750538193                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total    750538193                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.808096                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.808096                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954214                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954214                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860144                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.860144                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860144                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.860144                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17355.441449                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17355.441449                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22584.887038                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22584.887038                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19421.917308                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19421.917308                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19421.917308                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19421.917308                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 76088.624594                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76088.624594                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48764.745176                       # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48764.745176                       # average overall mshr uncacheable latency
+system.cpu2.num_reads                           99993                       # number of read accesses completed
+system.cpu2.num_writes                          55211                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22333                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             392.533782                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13552                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22757                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.595509                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      393.363987                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.768289                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.768289                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          387                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              339330                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             339330                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8744                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8744                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1142                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1142                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9886                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9886                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9886                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9886                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36705                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36705                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           23982                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          23982                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             60687                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            60687                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            60687                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           60687                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    655863609                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    655863609                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    555301116                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    555301116                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1211164725                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1211164725                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1211164725                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1211164725                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45449                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45449                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         25124                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        25124                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70573                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70573                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70573                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70573                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.807609                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.807609                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954545                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.954545                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.859918                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.859918                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.859918                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.859918                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17868.508623                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 17868.508623                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23154.912685                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 23154.912685                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 19957.564635                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 19957.564635                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 19957.564635                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 19957.564635                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs       744784                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2      392.533782                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.766668                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.766668                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          424                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          419                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.828125                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              338842                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             338842                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8700                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8700                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1131                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1131                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9831                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9831                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9831                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9831                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36743                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36743                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           23917                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          23917                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60660                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60660                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60660                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60660                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    667892138                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    667892138                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    561829218                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    561829218                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1229721356                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1229721356                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1229721356                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1229721356                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45443                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45443                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         25048                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        25048                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70491                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70491                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70491                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70491                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.808551                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.808551                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954847                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.954847                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.860535                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.860535                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.860535                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.860535                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18177.398089                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 18177.398089                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23490.789731                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 23490.789731                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 20272.359974                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 20272.359974                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 20272.359974                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 20272.359974                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs       824101                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               59741                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               66507                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.466882                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.391192                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9941                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9941                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36705                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36705                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23982                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        23982                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        60687                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        60687                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        60687                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        60687                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9745                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9745                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5541                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5541                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15286                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15286                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    619160609                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    619160609                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    531319116                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    531319116                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1150479725                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1150479725                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1150479725                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1150479725                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    736103391                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    736103391                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    958643718                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    958643718                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1694747109                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1694747109                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.807609                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.807609                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954545                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954545                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.859918                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.859918                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.859918                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.859918                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16868.563111                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16868.563111                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22154.912685                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22154.912685                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18957.597591                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18957.597591                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18957.597591                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18957.597591                       # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75536.520369                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75536.520369                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 173009.153221                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173009.153221                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 110869.233874                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 110869.233874                       # average overall mshr uncacheable latency
-system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           99493                       # number of read accesses completed
-system.cpu3.num_writes                          55186                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22493                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             393.330553                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13483                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22894                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.588932                       # Average number of references to valid blocks.
+system.cpu2.l1c.writebacks::writebacks           9742                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9742                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36743                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36743                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23917                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        23917                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60660                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60660                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60660                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60660                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2        10005                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadReq_mshr_uncacheable::total        10005                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5482                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5482                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15487                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15487                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    631149138                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    631149138                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    537912218                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    537912218                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1169061356                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1169061356                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1169061356                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1169061356                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    759988155                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    759988155                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2    759988155                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total    759988155                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.808551                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.808551                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954847                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954847                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.860535                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.860535                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.860535                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.860535                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17177.398089                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17177.398089                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22490.789731                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22490.789731                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19272.359974                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19272.359974                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19272.359974                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19272.359974                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75960.835082                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75960.835082                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 49072.651579                       # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 49072.651579                       # average overall mshr uncacheable latency
+system.cpu3.num_reads                           99085                       # number of read accesses completed
+system.cpu3.num_writes                          55606                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22528                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             391.624901                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13493                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22909                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.588982                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      393.330553                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.768224                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.768224                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          390                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              338296                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             338296                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8738                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8738                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1110                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1110                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9848                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9848                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9848                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9848                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36582                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36582                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23939                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23939                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60521                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60521                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60521                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60521                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    654319900                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    654319900                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    552232159                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    552232159                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1206552059                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1206552059                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1206552059                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1206552059                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45320                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45320                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         25049                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        25049                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70369                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70369                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70369                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70369                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.807193                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.807193                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.955687                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.955687                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.860052                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.860052                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.860052                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.860052                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17886.389481                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 17886.389481                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23068.305234                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 23068.305234                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 19936.089275                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 19936.089275                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 19936.089275                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 19936.089275                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs       748969                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      391.624901                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.764892                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.764892                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          381                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          374                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.744141                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              339302                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             339302                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8770                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8770                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1134                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1134                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9904                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9904                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9904                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9904                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36439                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36439                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           24225                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          24225                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60664                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60664                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60664                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60664                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    671429109                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    671429109                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    572133441                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    572133441                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1243562550                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1243562550                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1243562550                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1243562550                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45209                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45209                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         25359                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        25359                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70568                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70568                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70568                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70568                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.806012                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.806012                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.955282                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.955282                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.859653                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.859653                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.859653                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.859653                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18426.112380                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 18426.112380                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23617.479505                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 23617.479505                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 20499.184854                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 20499.184854                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 20499.184854                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 20499.184854                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs       821290                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               59958                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               66174                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.491561                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.411068                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9953                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9953                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36582                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36582                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23939                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23939                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60521                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60521                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60521                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60521                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9878                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9878                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5388                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5388                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15266                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15266                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    617737900                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    617737900                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    528295159                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    528295159                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1146033059                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1146033059                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1146033059                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1146033059                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    746486832                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    746486832                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    927844496                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    927844496                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1674331328                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1674331328                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.807193                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.807193                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.955687                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.955687                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860052                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.860052                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860052                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.860052                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16886.389481                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16886.389481                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22068.388780                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22068.388780                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18936.122321                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18936.122321                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18936.122321                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18936.122321                       # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75570.645070                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75570.645070                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 172205.734224                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172205.734224                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109677.147124                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109677.147124                       # average overall mshr uncacheable latency
-system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           99921                       # number of read accesses completed
-system.cpu4.num_writes                          55196                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               22380                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             392.777413                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13581                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22786                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.596024                       # Average number of references to valid blocks.
+system.cpu3.l1c.writebacks::writebacks          10017                       # number of writebacks
+system.cpu3.l1c.writebacks::total               10017                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36439                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36439                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        24225                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        24225                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60664                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60664                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60664                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60664                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9773                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9773                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5538                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5538                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15311                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15311                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    634992109                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    634992109                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    547908441                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    547908441                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1182900550                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1182900550                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1182900550                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1182900550                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    743773245                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    743773245                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3    743773245                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total    743773245                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.806012                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.806012                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.955282                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.955282                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.859653                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.859653                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.859653                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.859653                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17426.167266                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17426.167266                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22617.479505                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22617.479505                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19499.217823                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19499.217823                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19499.217823                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19499.217823                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 76104.905863                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76104.905863                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 48577.705245                       # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 48577.705245                       # average overall mshr uncacheable latency
+system.cpu4.num_reads                           99978                       # number of read accesses completed
+system.cpu4.num_writes                          55474                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22223                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             391.899958                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13858                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22628                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.612427                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      392.777413                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.767143                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.767143                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          406                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          394                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              339211                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             339211                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8862                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8862                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1132                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1132                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9994                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9994                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9994                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9994                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36800                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36800                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23778                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23778                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             60578                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            60578                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            60578                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           60578                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    655197570                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    655197570                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    548908934                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    548908934                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1204106504                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1204106504                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1204106504                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1204106504                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          45662                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         45662                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         24910                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        24910                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           70572                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          70572                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          70572                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         70572                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.805922                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.805922                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.954556                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.954556                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.858386                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.858386                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.858386                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.858386                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17804.281793                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 17804.281793                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23084.739423                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 23084.739423                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 19876.960349                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 19876.960349                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 19876.960349                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 19876.960349                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs       750268                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      391.899958                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.765430                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.765430                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          405                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          396                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.791016                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              340964                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             340964                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8890                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8890                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1171                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1171                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4               10061                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total              10061                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4              10061                       # number of overall hits
+system.cpu4.l1c.overall_hits::total             10061                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36725                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36725                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           24186                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          24186                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60911                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60911                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60911                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60911                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    668441602                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    668441602                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    573535032                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    573535032                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1241976634                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1241976634                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1241976634                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1241976634                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45615                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45615                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25357                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25357                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70972                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70972                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70972                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70972                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.805108                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.805108                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.953819                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.953819                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.858240                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.858240                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.858240                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.858240                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18201.268945                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 18201.268945                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23713.513272                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 23713.513272                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 20390.022065                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 20390.022065                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 20390.022065                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 20390.022065                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs       823668                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               59848                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               66629                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.536225                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.362005                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9770                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9770                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36800                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36800                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23778                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23778                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        60578                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        60578                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        60578                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        60578                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9925                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9925                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5406                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5406                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15331                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15331                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    618398570                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    618398570                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    525131934                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    525131934                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1143530504                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1143530504                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1143530504                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1143530504                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    750294225                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    750294225                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    944567825                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    944567825                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1694862050                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1694862050                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.805922                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.805922                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.954556                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.954556                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858386                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.858386                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858386                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.858386                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16804.308967                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16804.308967                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22084.781479                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22084.781479                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18876.993364                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18876.993364                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18876.993364                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18876.993364                       # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 75596.395466                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75596.395466                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174725.827784                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174725.827784                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 110551.304546                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 110551.304546                       # average overall mshr uncacheable latency
-system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99482                       # number of read accesses completed
-system.cpu5.num_writes                          55607                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22456                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             392.242325                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13457                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22866                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.588516                       # Average number of references to valid blocks.
+system.cpu4.l1c.writebacks::writebacks           9699                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9699                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36725                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36725                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        24186                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        24186                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60911                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60911                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60911                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60911                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9801                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9801                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5498                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5498                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15299                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15299                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    631717602                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    631717602                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    549351032                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    549351032                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1181068634                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1181068634                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1181068634                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1181068634                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    748050214                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    748050214                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4    748050214                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total    748050214                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.805108                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.805108                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.953819                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.953819                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858240                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.858240                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858240                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.858240                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17201.296174                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17201.296174                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22713.595965                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22713.595965                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19390.071317                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19390.071317                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19390.071317                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19390.071317                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 76323.866340                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76323.866340                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48895.366625                       # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48895.366625                       # average overall mshr uncacheable latency
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          55110                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22358                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             391.816568                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13630                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22751                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.599095                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      392.242325                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.766098                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.766098                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          410                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          397                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.800781                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              338143                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             338143                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8578                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8578                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1205                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1205                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9783                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9783                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9783                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9783                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36239                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36239                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           24308                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          24308                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             60547                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            60547                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            60547                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           60547                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    647043171                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    647043171                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    559180438                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    559180438                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1206223609                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1206223609                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1206223609                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1206223609                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          44817                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         44817                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         25513                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        25513                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           70330                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          70330                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          70330                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         70330                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808599                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.808599                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952769                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.952769                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.860899                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.860899                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.860899                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.860899                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17854.884820                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 17854.884820                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23003.967336                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 23003.967336                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 19922.103638                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 19922.103638                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 19922.103638                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 19922.103638                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs       749399                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      391.816568                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.765267                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.765267                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              340100                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             340100                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8821                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8821                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1107                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1107                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9928                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9928                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9928                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9928                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36801                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36801                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           24029                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          24029                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60830                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60830                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60830                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60830                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    677475643                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    677475643                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    566244558                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    566244558                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1243720201                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1243720201                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1243720201                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1243720201                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          45622                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         45622                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25136                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25136                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           70758                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          70758                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          70758                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         70758                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.806650                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.806650                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.955960                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.955960                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.859691                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.859691                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.859691                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.859691                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18409.163963                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 18409.163963                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23565.048816                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 23565.048816                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 20445.835953                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 20445.835953                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 20445.835953                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 20445.835953                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs       821580                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               59952                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               66406                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.499983                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.372075                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks          10051                       # number of writebacks
-system.cpu5.l1c.writebacks::total               10051                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36239                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36239                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        24308                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        24308                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        60547                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        60547                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        60547                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        60547                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9869                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9869                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5375                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5375                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15244                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15244                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    610804171                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    610804171                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    534872438                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    534872438                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1145676609                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1145676609                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1145676609                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1145676609                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    745114179                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    745114179                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    938602875                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    938602875                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1683717054                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1683717054                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808599                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808599                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952769                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952769                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.860899                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.860899                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.860899                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.860899                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16854.884820                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16854.884820                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22003.967336                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22003.967336                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18922.103638                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18922.103638                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18922.103638                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18922.103638                       # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 75500.474111                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75500.474111                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 174623.790698                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174623.790698                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 110451.131855                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 110451.131855                       # average overall mshr uncacheable latency
-system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                           99231                       # number of read accesses completed
-system.cpu6.num_writes                          55266                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22476                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             393.210816                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13488                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22863                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.589949                       # Average number of references to valid blocks.
+system.cpu5.l1c.writebacks::writebacks          10004                       # number of writebacks
+system.cpu5.l1c.writebacks::total               10004                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36801                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36801                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        24029                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        24029                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60830                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60830                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60830                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60830                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9765                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9765                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5412                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5412                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15177                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15177                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    640675643                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    640675643                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    542215558                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    542215558                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1182891201                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1182891201                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1182891201                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1182891201                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    744215663                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    744215663                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5    744215663                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total    744215663                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.806650                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.806650                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.955960                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.955960                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.859691                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.859691                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.859691                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.859691                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17409.191136                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17409.191136                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22565.048816                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22565.048816                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19445.852392                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19445.852392                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19445.852392                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19445.852392                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 76212.561495                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76212.561495                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 49035.755617                       # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 49035.755617                       # average overall mshr uncacheable latency
+system.cpu6.num_reads                           99774                       # number of read accesses completed
+system.cpu6.num_writes                          55185                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22542                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             391.726459                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13419                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22929                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.585241                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      393.210816                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.767990                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.767990                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_blocks::cpu6      391.726459                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.765091                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.765091                       # Average percentage of cache occupancy
 system.cpu6.l1c.tags.occ_task_id_blocks::1024          387                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          374                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
 system.cpu6.l1c.tags.occ_task_id_percent::1024     0.755859                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              339081                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             339081                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8703                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8703                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1207                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1207                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9910                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9910                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9910                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9910                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36605                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36605                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           24011                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          24011                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60616                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60616                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60616                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60616                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    653690176                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    653690176                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    554778070                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    554778070                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1208468246                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1208468246                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1208468246                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1208468246                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45308                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45308                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         25218                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        25218                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70526                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70526                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70526                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70526                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807915                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.807915                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.952137                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.952137                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.859484                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.859484                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.859484                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.859484                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17857.947712                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 17857.947712                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23105.163050                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 23105.163050                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 19936.456480                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 19936.456480                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 19936.456480                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 19936.456480                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs       748048                       # number of cycles access was blocked
+system.cpu6.l1c.tags.tag_accesses              339673                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             339673                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8710                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8710                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1147                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1147                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9857                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9857                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9857                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9857                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36696                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36696                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           24079                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          24079                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60775                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60775                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60775                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60775                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    672502171                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    672502171                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    571063447                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    571063447                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1243565618                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1243565618                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1243565618                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1243565618                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45406                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45406                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         25226                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        25226                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70632                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70632                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70632                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70632                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.808175                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.808175                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.954531                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.954531                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.860446                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.860446                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.860446                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.860446                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18326.307254                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 18326.307254                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23716.244321                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 23716.244321                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 20461.795442                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 20461.795442                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 20461.795442                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 20461.795442                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs       822508                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               59929                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               66430                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.482237                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.381575                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9811                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9811                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36605                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36605                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        24011                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        24011                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60616                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60616                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60616                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60616                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9828                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9828                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5436                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5436                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15264                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15264                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    617085176                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    617085176                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    530767070                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    530767070                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1147852246                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1147852246                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1147852246                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1147852246                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    743889866                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    743889866                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    938428736                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    938428736                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1682318602                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1682318602                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807915                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807915                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.952137                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.952137                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859484                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.859484                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859484                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.859484                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16857.947712                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16857.947712                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22105.163050                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22105.163050                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18936.456480                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18936.456480                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18936.456480                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18936.456480                       # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 75690.869556                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75690.869556                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 172632.217807                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172632.217807                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 110214.793108                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 110214.793108                       # average overall mshr uncacheable latency
-system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99956                       # number of read accesses completed
-system.cpu7.num_writes                          55531                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22312                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             393.161929                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13691                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22714                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.602756                       # Average number of references to valid blocks.
+system.cpu6.l1c.writebacks::writebacks           9969                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9969                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36696                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36696                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        24079                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        24079                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60775                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60775                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60775                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60775                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9782                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9782                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5438                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5438                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15220                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15220                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    635806171                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    635806171                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    546984447                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    546984447                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1182790618                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1182790618                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1182790618                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1182790618                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    745377162                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    745377162                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6    745377162                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total    745377162                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.808175                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.808175                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.954531                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.954531                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.860446                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.860446                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.860446                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.860446                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17326.307254                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17326.307254                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22716.244321                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22716.244321                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19461.795442                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19461.795442                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19461.795442                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19461.795442                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 76198.851155                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76198.851155                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 48973.532326                       # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 48973.532326                       # average overall mshr uncacheable latency
+system.cpu7.num_reads                           99703                       # number of read accesses completed
+system.cpu7.num_writes                          55656                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22447                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             392.675740                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13542                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22845                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.592777                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      393.161929                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.767894                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.767894                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              338939                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             338939                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8916                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8916                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1165                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1165                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7               10081                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total              10081                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7              10081                       # number of overall hits
-system.cpu7.l1c.overall_hits::total             10081                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36493                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36493                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23963                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23963                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60456                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60456                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60456                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60456                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    649044669                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    649044669                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    555516702                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    555516702                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1204561371                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1204561371                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1204561371                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1204561371                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45409                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45409                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         25128                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        25128                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70537                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70537                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70537                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70537                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.803651                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.803651                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953637                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.953637                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.857082                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.857082                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.857082                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.857082                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17785.456636                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 17785.456636                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23182.268581                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 23182.268581                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 19924.595921                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 19924.595921                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 19924.595921                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 19924.595921                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs       753584                       # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7      392.675740                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.766945                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.766945                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          391                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              338950                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             338950                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8682                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8682                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1173                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1173                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9855                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9855                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9855                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9855                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36511                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36511                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           24145                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          24145                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60656                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60656                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60656                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60656                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    668215285                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    668215285                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    564137498                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    564137498                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1232352783                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1232352783                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1232352783                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1232352783                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45193                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45193                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         25318                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        25318                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70511                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70511                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70511                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70511                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807891                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.807891                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953669                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.953669                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.860235                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.860235                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.860235                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.860235                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18301.752486                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 18301.752486                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23364.568151                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 23364.568151                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 20317.079646                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 20317.079646                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 20317.079646                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 20317.079646                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs       824059                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               60106                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               66592                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.537584                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.374745                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9825                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9825                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36493                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36493                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23963                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23963                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60456                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60456                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60456                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60456                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9946                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9946                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5477                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5477                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15423                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15423                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    612553669                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    612553669                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    531553702                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    531553702                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1144107371                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1144107371                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1144107371                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1144107371                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    750008205                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    750008205                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    931574803                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    931574803                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1681583008                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1681583008                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.803651                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.803651                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953637                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953637                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.857082                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.857082                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.857082                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.857082                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16785.511441                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16785.511441                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22182.268581                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22182.268581                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18924.629003                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18924.629003                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18924.629003                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18924.629003                       # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75408.023829                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75408.023829                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 170088.516158                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170088.516158                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 109030.863516                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 109030.863516                       # average overall mshr uncacheable latency
-system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    13679                       # number of replacements
-system.l2c.tags.tagsinuse                  785.030982                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     164295                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    14481                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    11.345556                       # Average number of references to valid blocks.
+system.cpu7.l1c.writebacks::writebacks           9889                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9889                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36511                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36511                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        24145                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        24145                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60656                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60656                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60656                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60656                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9951                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9951                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5417                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5417                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15368                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15368                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    631704285                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    631704285                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    539994498                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    539994498                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1171698783                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1171698783                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1171698783                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1171698783                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    757938041                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    757938041                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7    757938041                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total    757938041                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807891                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807891                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953669                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953669                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.860235                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.860235                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.860235                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.860235                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17301.752486                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17301.752486                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22364.650984                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22364.650984                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19317.112619                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19317.112619                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19317.112619                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19317.112619                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 76167.022510                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76167.022510                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49319.237441                       # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49319.237441                       # average overall mshr uncacheable latency
+system.l2c.tags.replacements                    13600                       # number of replacements
+system.l2c.tags.tagsinuse                  785.994901                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     164496                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14391                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    11.430477                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     728.912576                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             7.109869                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             7.264593                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             7.067016                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             7.280147                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             6.468572                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             6.873708                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             6.969066                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             7.085434                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.711829                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.006943                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.007094                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.006901                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.007110                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.006317                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.006713                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.006806                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.006919                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.766632                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          802                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          674                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  2100989                       # Number of tag accesses
-system.l2c.tags.data_accesses                 2100989                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks        77660                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total           77660                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0                  265                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  275                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  255                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  290                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  283                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  292                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  297                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  302                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2259                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1784                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1764                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1831                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  1735                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1757                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1864                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1767                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1780                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                14282                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0             10784                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1             10837                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2             10882                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3             10814                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4             10969                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5             10782                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6             10825                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7             10836                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total            86729                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0                    12568                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12601                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu3                    12549                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12726                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12646                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12592                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                  101011                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12568                       # number of overall hits
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-system.l2c.overall_hits::cpu3                   12549                       # number of overall hits
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-system.l2c.overall_hits::cpu5                   12646                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12592                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12616                       # number of overall hits
-system.l2c.overall_hits::total                 101011                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0               1935                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               2063                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               2062                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2061                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               2025                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               2056                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               1973                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               2050                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             16225                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4717                       # number of ReadExReq misses
+system.l2c.tags.occ_blocks::writebacks     730.947637                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             6.698781                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             6.684981                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             7.056959                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             6.865777                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             6.833706                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             7.577663                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             6.826515                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             6.502881                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.713816                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1            0.006528                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1024::0          651                       # Occupied blocks per task id
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+system.l2c.tags.tag_accesses                  2102241                       # Number of tag accesses
+system.l2c.tags.data_accesses                 2102241                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks        77703                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total           77703                       # number of WritebackDirty hits
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+system.l2c.UpgradeReq_hits::cpu1                  290                       # number of UpgradeReq hits
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+system.l2c.UpgradeReq_hits::cpu4                  279                       # number of UpgradeReq hits
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+system.l2c.UpgradeReq_hits::cpu6                  268                       # number of UpgradeReq hits
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+system.l2c.ReadExReq_hits::total                14182                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0             10810                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::cpu7             10910                       # number of ReadSharedReq hits
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+system.l2c.demand_hits::total                  100997                       # number of demand (read+write) hits
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+system.l2c.overall_hits::cpu2                   12717                       # number of overall hits
+system.l2c.overall_hits::cpu3                   12669                       # number of overall hits
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+system.l2c.overall_hits::cpu5                   12470                       # number of overall hits
+system.l2c.overall_hits::cpu6                   12621                       # number of overall hits
+system.l2c.overall_hits::cpu7                   12672                       # number of overall hits
+system.l2c.overall_hits::total                 100997                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0               1987                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1               2133                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2               2089                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3               2051                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4               2132                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu5               2090                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu6               2082                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu7               2039                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             16603                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0                4589                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1                4573                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4643                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4618                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4604                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4681                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4664                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4698                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              37198                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0             701                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1             741                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2             707                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3             750                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu4             700                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu5             714                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu6             696                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu7             703                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total           5712                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0                   5418                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5314                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5350                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5368                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5304                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5395                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   5360                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5401                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 42910                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5418                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5314                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5350                       # number of overall misses
-system.l2c.overall_misses::cpu3                  5368                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5304                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5395                       # number of overall misses
-system.l2c.overall_misses::cpu6                  5360                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5401                       # number of overall misses
-system.l2c.overall_misses::total                42910                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0     33570299                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     36327486                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     35657979                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     35008978                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     34589470                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     34691475                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     32410475                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     35465977                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    277722139                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     161829189                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     155335873                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     157770030                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     156623200                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     158516385                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     158789879                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     159063367                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     159738542                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1267666465                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0     49231417                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1     51778912                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2     49960071                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3     52497915                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu4     48409406                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu5     49972406                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu6     48755897                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu7     49161911                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total    399767935                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0        211060606                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        207114785                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu3        209121115                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu5        208762285                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        207819264                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        208900453                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      1667434400                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       211060606                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu2       207730101                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       209121115                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       206925791                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       208762285                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       207819264                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       208900453                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     1667434400                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks        77660                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total        77660                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2200                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2338                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2317                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2351                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2308                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2348                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2270                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2352                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18484                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6501                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1              6337                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::cpu3              6353                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu3         11564                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu4         11669                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu5         11496                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu6         11521                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu7         11539                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total        92441                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.demand_accesses::total              143921                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu4               18030                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu6               17952                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               18017                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             143921                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.879545                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.882378                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.889944                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.876648                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.877383                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.875639                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.869163                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.871599                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.877786                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.725581                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.721635                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.717176                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.726901                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.723786                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.715202                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.725237                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.725224                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.722572                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0     0.061036                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1     0.064001                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2     0.061006                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3     0.064856                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu4     0.059988                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu5     0.062109                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu6     0.060411                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu7     0.060924                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.061791                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0            0.301234                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.296623                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.296186                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.299604                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.294176                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.299041                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.298574                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.299772                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.298150                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.301234                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.296623                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.296186                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.299604                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.294176                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.299041                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.298574                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.299772                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.298150                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 17348.991731                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 17609.057683                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 17292.909311                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 16986.403688                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 17081.219753                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 16873.285506                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 16427.002027                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 17300.476585                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 17116.926903                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 34307.650837                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 33968.045703                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 33980.191686                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 33915.807709                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 34430.144440                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 33922.212989                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 34104.495497                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 34001.392507                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 34078.887709                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70230.266762                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69877.074224                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2 70664.881188                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69997.220000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69156.294286                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69989.364146                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70051.576149                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69931.594595                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 69987.383578                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 38955.445921                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 38975.307678                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 38828.056262                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 38956.988636                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 39013.158183                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 38695.511585                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 38772.250746                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 38678.106462                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 38858.876719                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 38955.445921                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 38975.307678                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 38828.056262                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 38956.988636                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 39013.158183                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 38695.511585                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 38772.250746                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 38678.106462                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 38858.876719                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             15775                       # number of cycles access was blocked
+system.l2c.ReadExReq_misses::cpu2                4653                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3                4696                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu4                4757                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu5                4526                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu6                4651                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu7                4580                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              37025                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0             704                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1             708                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2             710                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3             726                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu4             671                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu5             758                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu6             689                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu7             675                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           5641                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0                   5293                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1                   5281                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2                   5363                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3                   5422                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu4                   5428                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu5                   5284                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu6                   5340                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu7                   5255                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                 42666                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0                  5293                       # number of overall misses
+system.l2c.overall_misses::cpu1                  5281                       # number of overall misses
+system.l2c.overall_misses::cpu2                  5363                       # number of overall misses
+system.l2c.overall_misses::cpu3                  5422                       # number of overall misses
+system.l2c.overall_misses::cpu4                  5428                       # number of overall misses
+system.l2c.overall_misses::cpu5                  5284                       # number of overall misses
+system.l2c.overall_misses::cpu6                  5340                       # number of overall misses
+system.l2c.overall_misses::cpu7                  5255                       # number of overall misses
+system.l2c.overall_misses::total                42666                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0     33033499                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1     37073999                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2     35504000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3     34167500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu4     35922999                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu5     36683500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu6     35141499                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu7     35012999                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    282539995                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0     156097931                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1     156545440                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2     159419095                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3     159741454                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu4     162402934                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu5     154349443                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu6     159730395                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu7     156156442                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1264443134                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0     50090895                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1     50336063                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2     50437231                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3     51704240                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu4     47729417                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu5     53673691                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu6     48908906                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu7     47302737                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total    400183180                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0        206188826                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1        206881503                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2        209856326                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3        211445694                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu4        210132351                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu5        208023134                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu6        208639301                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu7        203459179                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      1664626314                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0       206188826                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1       206881503                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2       209856326                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3       211445694                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu4       210132351                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu5       208023134                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu6       208639301                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu7       203459179                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     1664626314                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks        77703                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total        77703                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0             2277                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1             2423                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2             2383                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3             2315                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu4             2411                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu5             2379                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu6             2350                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu7             2364                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           18902                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0              6405                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1              6292                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2              6362                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3              6536                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu4              6545                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu5              6280                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu6              6445                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu7              6342                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            51207                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0         11514                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1         11548                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2         11718                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3         11555                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu4         11546                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu5         11474                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu6         11516                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu7         11585                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total        92456                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0                17919                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1                17840                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2                18080                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3                18091                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu4                18091                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu5                17754                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu6                17961                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu7                17927                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              143663                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0               17919                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu2               18080                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3               18091                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu4               18091                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu5               17754                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu6               17961                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu7               17927                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             143663                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0        0.872639                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.880314                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.876626                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.885961                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.884280                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.878520                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.885957                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.862521                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.878373                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.716472                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.726796                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.731374                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.718482                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.726814                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.720701                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.721645                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.722170                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.723046                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0     0.061143                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1     0.061309                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2     0.060591                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3     0.062830                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu4     0.058115                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu5     0.066062                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu6     0.059830                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu7     0.058265                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.061013                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0            0.295385                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.296020                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2            0.296626                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3            0.299707                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.300039                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.297623                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.297311                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.293133                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.296987                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.295385                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.296020                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.296626                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.299707                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.300039                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.297623                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.297311                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.293133                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.296987                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 16624.810770                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 17381.152836                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 16995.691719                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 16658.946855                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 16849.436679                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 17551.913876                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 16878.721902                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 17171.652281                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 17017.406192                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 34015.674657                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 34232.547562                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 34261.572104                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 34016.493612                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 34139.780114                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 34102.837605                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 34343.236938                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 34095.293013                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 34151.063714                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0 71151.839489                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1 71096.134181                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2 71038.353521                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3 71217.961433                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu4 71131.769001                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70809.618734                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70985.349782                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70078.128889                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 70941.886190                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 38955.002078                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 39174.683393                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 39130.398285                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 38997.730358                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 38712.665991                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 39368.496215                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 39071.030150                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 38717.255756                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 39015.288848                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 38955.002078                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 39174.683393                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 39130.398285                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 38997.730358                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 38712.665991                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 39368.496215                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 39071.030150                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 38717.255756                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 39015.288848                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             20827                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     2328                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     3189                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      6.776203                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      6.530887                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6347                       # number of writebacks
-system.l2c.writebacks::total                     6347                       # number of writebacks
-system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                7                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2                8                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5                8                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                2                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                9                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              45                       # number of ReadExReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0            7                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2            7                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3           10                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu4           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu5            8                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu6            9                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu7            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           71                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  20                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                  15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                  13                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  18                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                  16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                  13                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                116                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                 10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 20                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                 15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                 13                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 18                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::cpu6                 11                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::total               116                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         1217                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         1217                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          1934                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          2063                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          2062                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          2060                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          2025                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          2055                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          1973                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          2050                       # number of UpgradeReq MSHR misses
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 system.l2c.ReadSharedReq_mshr_misses::cpu0          694                       # number of ReadSharedReq MSHR misses
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+system.l2c.demand_mshr_misses::cpu2              5343                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3              5412                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4              5420                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5              5272                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5322                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5234                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            42554                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5281                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5270                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5343                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5412                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5420                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5             5272                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6             5322                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5234                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           42554                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0         9909                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1         9863                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2        10005                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3         9773                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu4         9801                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu5         9765                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu6         9782                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu7         9951                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        78849                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0         5376                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1         5525                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2         5482                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3         5537                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu4         5496                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu5         5409                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu6         5438                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu7         5416                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        43679                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0        15285                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1        15388                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2        15487                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3        15310                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu4        15297                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu5        15174                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu6        15220                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu7        15367                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       122528                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     41114731                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     44135575                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     43262560                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     42495420                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     44129731                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     43370592                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     43201403                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     42227606                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    343937618                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    110096109                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    110716645                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    112771891                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    112546795                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    114695609                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    108961847                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    112947605                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    110110769                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total    892847270                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     42686190                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     42892571                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     42733862                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     44195932                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     40778543                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     45766520                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     41640903                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     39953551                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    340648072                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    152782299                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    153609216                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    155505753                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    156742727                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    155474152                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    154728367                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    154588508                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    150064320                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1233495342                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    152782299                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    153609216                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    155505753                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    156742727                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    155474152                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    154728367                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    154588508                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    150064320                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1233495342                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    531934603                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    529144419                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    536612256                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    524755063                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    526637223                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    524048250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    524701912                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    534783521                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   4232617247                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    531934603                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    529144419                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    536612256                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    524755063                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    526637223                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    524048250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    524701912                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    534783521                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4232617247                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.879091                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.882378                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.889944                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.876223                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.877383                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.875213                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.869163                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.871599                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.877624                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.725119                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.720530                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.715941                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.726428                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.723000                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.713980                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.724926                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.723835                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.721698                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.060427                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.062878                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.060402                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.063992                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.058874                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.061413                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.059630                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.060577                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.061023                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.300678                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.295507                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.295355                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.298878                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.293178                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.298154                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.297961                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.299051                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.297344                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.300678                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.295507                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.295355                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.298878                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.293178                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.298154                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.297961                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.299051                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.297344                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20793.145295                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20771.712555                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.084384                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20737.336893                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20718.154568                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20760.129440                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20722.885454                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20708.580488                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20741.143139                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24285.835384                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 23942.015331                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 23976.722977                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23906.158397                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24418.595347                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 23905.807618                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24097.867653                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 23975.594157                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 24063.749388                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 60435.688761                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 60163.767857                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 60832.001429                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 60240.191892                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59677.107715                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60108.402266                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 60324.903930                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59915.208870                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 60212.795426                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 28924.888314                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 28923.019456                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 28812.467104                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 28927.107937                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 29001.001324                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 28657.440231                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 28750.695083                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 28638.138827                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 28828.827873                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 28924.888314                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 28923.019456                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 28812.467104                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 28927.107937                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 29001.001324                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 28657.440231                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 28750.695083                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 28638.138827                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 28828.827873                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53478.342438                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53528.071198                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53575.323140                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53520.679490                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53508.103980                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53534.804641                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53571.977818                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53563.064046                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53534.903328                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 55252.493333                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 55271.636595                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 55356.153069                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 55111.633630                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 55462.967617                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 55437.218047                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 55650.921251                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 55411.013699                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 55369.106167                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 54107.738936                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 54151.346895                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 54220.779326                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 54082.192716                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 54197.260682                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 54205.591315                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 54312.268558                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 54219.151482                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 54186.935729                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests        125196                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       119242                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.872639                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.879901                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.876206                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.885961                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.884280                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.877680                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.885957                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.862521                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.878161                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.716159                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.726478                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.730588                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.717564                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.726203                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.720382                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.720403                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.721224                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.722362                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.060274                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.060530                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.059310                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.062484                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.057769                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.065191                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.058961                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.056970                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.060180                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.294715                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.295404                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.295520                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.299154                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.299596                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.296947                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.296309                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.291962                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.296207                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.294715                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.295404                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.295520                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.299154                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.299596                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.296947                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.296309                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.291962                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.296207                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20691.862607                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20701.489212                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.616858                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20719.366163                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20698.748124                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20771.356322                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20749.953410                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20709.958803                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20720.381830                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24001.767822                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 24221.536863                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 24262.455034                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23997.184435                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24131.203240                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 24085.288904                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24326.427956                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 24073.189550                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 24137.530954                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61507.478386                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 61362.762518                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 61487.571223                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 61213.202216                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 61137.245877                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 61185.187166                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 61326.808542                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60535.683333                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 61223.593098                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 28930.562204                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 29147.858824                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 29104.576642                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 28962.070769                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 28685.267897                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 29349.083270                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 29047.070274                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 28671.058464                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 28986.589792                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 28930.562204                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 29147.858824                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 29104.576642                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 28962.070769                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 28685.267897                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 29349.083270                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 29047.070274                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 28671.058464                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 28986.589792                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53681.966192                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53649.439217                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53634.408396                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53694.368464                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53733.009183                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53665.975422                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53639.533020                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53741.686363                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53680.037122                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 34801.086228                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 34386.822134                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 34649.206173                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 34275.314370                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 34427.484016                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 34535.933175                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 34474.501445                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 34800.775753                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 34544.081736                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        125015                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       119335                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq               79046                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84668                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43599                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43596                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty         6347                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             1243                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            60999                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             49250                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3150                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          5631                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       377529                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 377529                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1090828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1090828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            56847                       # Total snoops (count)
-system.membus.snoop_fanout::samples            245688                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               78845                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84388                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43678                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43672                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty         6244                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             1238                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            61417                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             49074                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3109                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          5552                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       377217                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 377217                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1076434                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1076434                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            56879                       # Total snoops (count)
+system.membus.snoop_fanout::samples            245548                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  245688    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  245548    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              245688                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           290283631                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              54.2                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          245575000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             45.9                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests       665524                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       283935                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       335837                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          12315                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         5744                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         6571                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              79051                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            371557                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43601                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43596                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty        84007                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          105887                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29231                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29230                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           162413                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          162411                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       292528                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133547                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133251                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       133734                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133419                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       133559                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133487                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133484                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       133586                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1068067                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1785416                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1780080                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1798067                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1787232                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1784031                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1801672                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1781660                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1785403                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14303561                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          335445                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           626448                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.148675                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.987271                       # Request fanout histogram
+system.membus.snoop_fanout::total              245548                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           288762573                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              57.6                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          244649000                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             48.8                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests       663848                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       283900                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       334405                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          12239                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         5805                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         6434                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              78849                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            372013                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43679                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43671                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty        83947                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          105636                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29816                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29815                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           162678                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          162674                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       293185                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133340                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133547                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       134024                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133820                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       133857                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133294                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133675                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       133694                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1069251                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1781172                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1779932                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1786043                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1802764                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1783744                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1780612                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1792304                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1782917                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14289488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          336712                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           624467                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.150434                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.985907                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 174709     27.89%     27.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 258191     41.22%     69.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 133874     21.37%     90.47% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                  46929      7.49%     97.97% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  11007      1.76%     99.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                   1601      0.26%     99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                    133      0.02%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      4      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 172892     27.69%     27.69% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 258676     41.42%     69.11% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 133601     21.39%     90.50% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                  46619      7.47%     97.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  10890      1.74%     99.71% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                   1624      0.26%     99.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                    162      0.03%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                      3      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             626448                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          498178453                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization             93.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         102533331                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         102040683                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization            19.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         102532818                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         102294677                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            19.1                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         102527849                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         102329742                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            19.1                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         102510939                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         102349372                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization            19.1                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total             624467                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          494463871                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             98.6                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         102665881                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy         102599371                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         102945420                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         102767709                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         102912196                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy         102768177                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         102966672                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy         102752542                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization            20.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index 36475e393..35b91ee55 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,1811 +1,1733 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000530                       # Number of seconds simulated
-sim_ticks                                   530176500                       # Number of ticks simulated
-final_tick                                  530176500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000500                       # Number of seconds simulated
+sim_ticks                                   500337000                       # Number of ticks simulated
+final_tick                                  500337000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              118834220                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236308                       # Number of bytes of host memory used
-host_seconds                                     4.46                       # Real time elapsed on the host
+host_tick_rate                               94931123                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234040                       # Number of bytes of host memory used
+host_seconds                                     5.27                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 78184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 80178                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 79911                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 80308                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 82157                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 80611                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 79164                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 81441                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               641954                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       404160                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5485                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5400                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5418                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5526                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5422                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5458                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5386                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5538                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            447793                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  10774                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  10815                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10863                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  11071                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  10904                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  10870                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10935                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  10881                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 87113                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6315                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5485                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5400                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5418                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5526                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5422                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5458                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5386                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5538                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                49948                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                147467872                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                151228883                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                150725277                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                151474085                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                154961602                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                152045592                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                149316313                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                153611109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1210830733                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         762312173                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                10345611                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                10185287                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                10219238                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                10422944                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                10226783                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                10294685                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                10158881                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                10445578                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              844611181                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         762312173                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               157813483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               161414171                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               160944516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               161897029                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               165188385                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               162340277                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               159475194                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               164056687                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2055441914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 75919                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 81043                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 80577                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 79993                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 82197                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 76405                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 83460                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 78091                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               637685                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       400320                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5398                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5467                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5426                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5579                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5520                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5451                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5589                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5357                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            444107                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  10777                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10924                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  11088                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  10945                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  11007                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10948                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  11010                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10807                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87506                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6255                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5398                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5467                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5426                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5579                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5520                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5451                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5589                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5357                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                50042                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                151735730                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                161976828                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                161045455                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                159878242                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                164283273                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                152707075                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                166807572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                156076804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1274510980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         800100732                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                10788728                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                10926635                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                10844691                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                11150485                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                11032564                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                10894657                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                11170471                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                10706784                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              887615747                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         800100732                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               162524459                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               172903463                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               171890146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               171028727                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               175315837                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               163601732                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               177978043                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               166783588                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2162126727                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                           99175                       # number of read accesses completed
-system.cpu0.num_writes                          54789                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22440                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             392.189512                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13440                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22832                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.588648                       # Average number of references to valid blocks.
+system.cpu0.num_reads                           99905                       # number of read accesses completed
+system.cpu0.num_writes                          55400                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22463                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             391.153981                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13877                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22862                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.606990                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      392.189512                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.765995                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.765995                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          392                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          373                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.765625                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              338141                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             338141                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8693                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8693                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1204                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1204                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9897                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9897                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9897                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9897                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36509                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36509                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23927                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23927                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60436                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60436                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60436                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60436                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    645236912                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    645236912                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    543361201                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    543361201                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1188598113                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1188598113                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1188598113                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1188598113                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          45202                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         45202                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         25131                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        25131                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           70333                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          70333                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          70333                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         70333                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807686                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.807686                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.952091                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.952091                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.859284                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.859284                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.859284                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.859284                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17673.365800                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 17673.365800                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 22709.123626                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 22709.123626                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 19667.054620                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 19667.054620                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 19667.054620                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 19667.054620                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs       716464                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      391.153981                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.763973                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.763973                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          389                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              340651                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             340651                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8894                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8894                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1261                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1261                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0               10155                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total              10155                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0              10155                       # number of overall hits
+system.cpu0.l1c.overall_hits::total             10155                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36720                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36720                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           24041                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          24041                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60761                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60761                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60761                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60761                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    677337671                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    677337671                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    564207136                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    564207136                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1241544807                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1241544807                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1241544807                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1241544807                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          45614                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         45614                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         25302                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        25302                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           70916                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          70916                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          70916                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         70916                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.805016                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.805016                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.950162                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.950162                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.856802                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.856802                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.856802                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.856802                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18446.015005                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 18446.015005                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23468.538580                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 23468.538580                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 20433.251708                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 20433.251708                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 20433.251708                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 20433.251708                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs       800862                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               58624                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               65942                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.221343                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.144946                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9950                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9950                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36509                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36509                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23927                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23927                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60436                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60436                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60436                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60436                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9705                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9705                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5489                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5489                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15194                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15194                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    608727912                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    608727912                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    519435201                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    519435201                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1128163113                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1128163113                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1128163113                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1128163113                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    718425919                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    718425919                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    939004763                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    939004763                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1657430682                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1657430682                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807686                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807686                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.952091                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.952091                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.859284                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.859284                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.859284                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.859284                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16673.365800                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16673.365800                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 21709.165420                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 21709.165420                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18667.071166                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18667.071166                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18667.071166                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18667.071166                       # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 74026.369809                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74026.369809                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 171070.279286                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171070.279286                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109084.551928                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109084.551928                       # average overall mshr uncacheable latency
-system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           99705                       # number of read accesses completed
-system.cpu1.num_writes                          54823                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               22335                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             390.697643                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13624                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22725                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.599516                       # Average number of references to valid blocks.
+system.cpu0.l1c.writebacks::writebacks          10055                       # number of writebacks
+system.cpu0.l1c.writebacks::total               10055                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36720                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36720                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        24041                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        24041                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60761                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60761                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60761                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60761                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9743                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9743                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5400                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5400                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15143                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15143                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    640619671                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    640619671                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    540167136                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    540167136                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1180786807                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1180786807                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1180786807                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1180786807                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    730760811                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    730760811                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0    730760811                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total    730760811                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.805016                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.805016                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.950162                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.950162                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.856802                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.856802                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.856802                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.856802                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17446.069472                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17446.069472                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22468.580176                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22468.580176                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19433.301081                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19433.301081                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19433.301081                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19433.301081                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75003.675562                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.675562                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 48257.334148                       # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 48257.334148                       # average overall mshr uncacheable latency
+system.cpu1.num_reads                           99552                       # number of read accesses completed
+system.cpu1.num_writes                          55243                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22440                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             392.475962                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13641                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22851                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.596954                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      390.697643                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.763081                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.763081                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              339221                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             339221                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8840                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8840                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1148                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1148                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9988                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9988                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9988                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9988                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36605                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36605                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           23987                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          23987                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60592                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60592                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60592                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60592                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    646842299                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    646842299                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    543658224                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    543658224                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1190500523                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1190500523                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1190500523                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1190500523                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          45445                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         45445                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         25135                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        25135                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           70580                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          70580                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          70580                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         70580                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805479                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.805479                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954327                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.954327                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.858487                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.858487                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.858487                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.858487                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17670.872804                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 17670.872804                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 22664.702714                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 22664.702714                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 19647.816923                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 19647.816923                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 19647.816923                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 19647.816923                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs       718948                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      392.475962                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.766555                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.766555                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          411                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          399                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.802734                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              339640                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             339640                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8906                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8906                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1136                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1136                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1               10042                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total              10042                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1              10042                       # number of overall hits
+system.cpu1.l1c.overall_hits::total             10042                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36595                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36595                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           24033                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          24033                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60628                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60628                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60628                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60628                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    675076804                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    675076804                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    561344066                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    561344066                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1236420870                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1236420870                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1236420870                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1236420870                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45501                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45501                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         25169                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        25169                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70670                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70670                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70670                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70670                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.804268                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.804268                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954865                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.954865                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.857903                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.857903                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.857903                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.857903                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18447.241536                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 18447.241536                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23357.219906                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 23357.219906                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 20393.561886                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 20393.561886                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 20393.561886                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 20393.561886                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs       800224                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               59028                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               65844                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.179779                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.153332                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9932                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9932                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36605                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36605                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23987                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        23987                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60592                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60592                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60592                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60592                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9715                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9715                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5400                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5400                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15115                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15115                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    610238299                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    610238299                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    519672224                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    519672224                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1129910523                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1129910523                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1129910523                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1129910523                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    721621903                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    721621903                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    954237303                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    954237303                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1675859206                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1675859206                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805479                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805479                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954327                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954327                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.858487                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.858487                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.858487                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.858487                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16670.900123                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16670.900123                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 21664.744403                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 21664.744403                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18647.849931                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18647.849931                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18647.849931                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18647.849931                       # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74279.145960                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74279.145960                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 176710.611667                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176710.611667                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 110873.913728                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 110873.913728                       # average overall mshr uncacheable latency
-system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99117                       # number of read accesses completed
-system.cpu2.num_writes                          54908                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22381                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             392.253516                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13534                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22797                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.593675                       # Average number of references to valid blocks.
+system.cpu1.l1c.writebacks::writebacks           9864                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9864                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36595                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36595                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        24033                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        24033                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60628                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60628                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60628                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60628                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9811                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9811                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5468                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5468                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15279                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15279                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    638481804                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    638481804                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    537312066                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    537312066                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1175793870                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1175793870                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1175793870                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1175793870                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    734637731                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    734637731                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1    734637731                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total    734637731                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.804268                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.804268                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954865                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954865                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.857903                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.857903                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.857903                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.857903                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17447.241536                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17447.241536                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22357.261515                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22357.261515                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19393.578380                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19393.578380                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19393.578380                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19393.578380                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74878.985934                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74878.985934                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48081.532234                       # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48081.532234                       # average overall mshr uncacheable latency
+system.cpu2.num_reads                          100001                       # number of read accesses completed
+system.cpu2.num_writes                          55556                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22129                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             390.469202                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13617                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22527                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.604475                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      392.253516                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.766120                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.766120                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          416                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          405                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              338010                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             338010                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8679                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8679                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1137                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1137                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9816                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9816                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9816                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9816                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36478                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36478                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           24024                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          24024                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             60502                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            60502                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            60502                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           60502                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    647459345                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    647459345                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    543523925                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    543523925                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1190983270                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1190983270                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1190983270                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1190983270                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45157                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45157                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         25161                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        25161                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70318                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70318                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70318                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70318                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.807804                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.807804                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954811                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.954811                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.860406                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.860406                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.860406                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.860406                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17749.310406                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 17749.310406                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 22624.206002                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 22624.206002                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 19685.023140                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 19685.023140                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 19685.023140                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 19685.023140                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs       722959                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2      390.469202                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.762635                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.762635                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          390                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              339163                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             339163                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8741                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8741                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1177                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1177                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9918                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9918                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9918                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9918                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36520                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36520                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           24129                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          24129                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60649                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60649                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60649                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60649                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    666978729                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    666978729                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    561823462                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    561823462                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1228802191                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1228802191                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1228802191                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1228802191                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45261                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45261                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         25306                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        25306                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70567                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70567                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70567                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70567                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.806876                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.806876                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953489                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.953489                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.859453                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.859453                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.859453                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.859453                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18263.382503                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 18263.382503                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23284.158564                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 23284.158564                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 20260.881317                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 20260.881317                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 20260.881317                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 20260.881317                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs       804972                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               59032                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               66283                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.246900                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.144471                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9774                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9774                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36478                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36478                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24024                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        24024                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        60502                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        60502                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        60502                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        60502                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9767                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9767                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5419                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5419                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15186                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15186                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    610981345                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    610981345                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    519499925                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    519499925                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1130481270                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1130481270                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1130481270                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1130481270                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    722748371                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    722748371                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    934057840                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    934057840                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1656806211                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1656806211                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.807804                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.807804                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954811                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954811                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.860406                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.860406                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.860406                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.860406                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16749.310406                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16749.310406                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 21624.206002                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 21624.206002                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18685.023140                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18685.023140                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18685.023140                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18685.023140                       # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73999.014129                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73999.014129                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 172367.196900                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172367.196900                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 109100.896286                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 109100.896286                       # average overall mshr uncacheable latency
-system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                          100000                       # number of read accesses completed
-system.cpu3.num_writes                          55255                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22194                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             391.395366                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13678                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22603                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.605141                       # Average number of references to valid blocks.
+system.cpu2.l1c.writebacks::writebacks           9821                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9821                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36520                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36520                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24129                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        24129                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60649                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60649                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60649                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60649                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9985                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9985                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5427                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5427                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15412                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15412                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    630459729                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    630459729                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    537696462                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    537696462                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1168156191                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1168156191                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1168156191                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1168156191                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    746431095                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    746431095                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2    746431095                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total    746431095                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.806876                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.806876                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953489                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953489                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.859453                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.859453                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.859453                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.859453                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17263.409885                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17263.409885                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22284.241452                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22284.241452                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19260.930782                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19260.930782                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19260.930782                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19260.930782                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 74755.242364                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74755.242364                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 48431.812549                       # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 48431.812549                       # average overall mshr uncacheable latency
+system.cpu3.num_reads                           99831                       # number of read accesses completed
+system.cpu3.num_writes                          55461                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22291                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             391.006782                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13350                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22681                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.588598                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      391.395366                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.764444                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.764444                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          409                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          403                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.798828                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              337339                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             337339                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8923                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8923                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1132                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1132                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3               10055                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total              10055                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3              10055                       # number of overall hits
-system.cpu3.l1c.overall_hits::total             10055                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36521                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36521                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23639                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23639                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60160                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60160                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60160                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60160                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    641069966                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    641069966                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    531956623                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    531956623                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1173026589                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1173026589                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1173026589                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1173026589                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45444                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45444                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         24771                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        24771                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70215                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70215                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70215                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70215                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.803648                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.803648                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954301                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.954301                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.856797                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.856797                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.856797                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.856797                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17553.461461                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 17553.461461                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 22503.347138                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 22503.347138                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 19498.447291                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 19498.447291                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 19498.447291                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 19498.447291                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs       718925                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      391.006782                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.763685                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.763685                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          379                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              338050                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             338050                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8529                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8529                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1176                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1176                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9705                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9705                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9705                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9705                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36689                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36689                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23899                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23899                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60588                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60588                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60588                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60588                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    675943664                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    675943664                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    557387689                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    557387689                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1233331353                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1233331353                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1233331353                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1233331353                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45218                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45218                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         25075                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        25075                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70293                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70293                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70293                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70293                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.811380                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.811380                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.953101                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.953101                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.861935                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.861935                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.861935                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.861935                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18423.605549                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 18423.605549                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23322.636470                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 23322.636470                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 20356.033422                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 20356.033422                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 20356.033422                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 20356.033422                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs       801051                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               58812                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               65873                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.224121                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.160536                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9851                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9851                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36521                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36521                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23639                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23639                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60160                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60160                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60160                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60160                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9973                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9973                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5527                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5527                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15500                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15500                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    604549966                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    604549966                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    508318623                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    508318623                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1112868589                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1112868589                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1112868589                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1112868589                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    738348758                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    738348758                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    962176807                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    962176807                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1700525565                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1700525565                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.803648                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.803648                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954301                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954301                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.856797                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.856797                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.856797                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.856797                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16553.488842                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16553.488842                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 21503.389441                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 21503.389441                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18498.480535                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18498.480535                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18498.480535                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18498.480535                       # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 74034.769678                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74034.769678                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 174086.630541                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174086.630541                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109711.326774                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109711.326774                       # average overall mshr uncacheable latency
-system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           98958                       # number of read accesses completed
-system.cpu4.num_writes                          54718                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               22445                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             392.205168                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13326                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22839                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.583476                       # Average number of references to valid blocks.
+system.cpu3.l1c.writebacks::writebacks           9857                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9857                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36689                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36689                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23899                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23899                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60588                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60588                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60588                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60588                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9849                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9849                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5582                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5582                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15431                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15431                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    639257664                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    639257664                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    533488689                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    533488689                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1172746353                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1172746353                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1172746353                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1172746353                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    738856089                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    738856089                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3    738856089                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total    738856089                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.811380                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.811380                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.953101                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.953101                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.861935                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.861935                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.861935                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.861935                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17423.687318                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17423.687318                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22322.636470                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22322.636470                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19356.082937                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19356.082937                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19356.082937                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19356.082937                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75018.386537                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75018.386537                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 47881.283715                       # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 47881.283715                       # average overall mshr uncacheable latency
+system.cpu4.num_reads                           99911                       # number of read accesses completed
+system.cpu4.num_writes                          55300                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22364                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             391.705900                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13535                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22773                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.594344                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      392.205168                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.766026                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.766026                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          394                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.769531                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              336585                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             336585                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8551                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8551                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1195                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1195                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9746                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9746                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9746                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9746                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36430                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36430                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23820                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23820                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             60250                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            60250                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            60250                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           60250                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    646410865                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    646410865                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    541537295                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    541537295                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1187948160                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1187948160                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1187948160                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1187948160                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          44981                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         44981                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         25015                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        25015                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           69996                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          69996                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          69996                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         69996                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.809898                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.809898                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952229                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.952229                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.860763                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.860763                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.860763                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.860763                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17743.916141                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 17743.916141                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 22734.563182                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 22734.563182                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 19716.981909                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 19716.981909                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 19716.981909                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 19716.981909                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs       719943                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      391.705900                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.765051                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.765051                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          409                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          401                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.798828                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              339861                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             339861                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8886                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8886                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1168                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1168                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4               10054                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total              10054                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4              10054                       # number of overall hits
+system.cpu4.l1c.overall_hits::total             10054                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36446                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36446                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           24191                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          24191                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60637                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60637                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60637                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60637                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    672672441                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    672672441                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    560233927                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    560233927                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1232906368                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1232906368                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1232906368                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1232906368                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45332                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45332                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25359                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25359                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70691                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70691                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70691                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70691                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.803980                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.803980                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.953941                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.953941                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.857775                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.857775                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.857775                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.857775                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18456.687730                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 18456.687730                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23158.775040                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 23158.775040                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 20332.575292                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 20332.575292                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 20332.575292                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 20332.575292                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs       801696                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               58800                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               65950                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.243929                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.156118                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9851                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9851                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36430                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36430                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23820                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23820                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        60250                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        60250                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        60250                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        60250                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9773                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9773                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5424                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5424                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15197                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15197                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    609980865                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    609980865                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    517717295                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    517717295                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1127698160                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1127698160                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1127698160                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1127698160                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    724329762                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    724329762                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    945564873                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    945564873                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1669894635                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1669894635                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.809898                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.809898                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952229                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952229                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.860763                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.860763                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.860763                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.860763                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16743.916141                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16743.916141                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 21734.563182                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 21734.563182                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18716.981909                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18716.981909                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18716.981909                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18716.981909                       # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74115.395682                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74115.395682                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174329.806969                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174329.806969                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 109883.176614                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 109883.176614                       # average overall mshr uncacheable latency
-system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99011                       # number of read accesses completed
-system.cpu5.num_writes                          55007                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22453                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             391.576438                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13255                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22854                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.579986                       # Average number of references to valid blocks.
+system.cpu4.l1c.writebacks::writebacks           9921                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9921                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36446                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36446                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        24191                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        24191                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60637                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60637                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60637                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60637                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9877                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9877                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5522                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5522                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15399                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15399                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    636227441                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    636227441                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    536043927                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    536043927                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1172271368                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1172271368                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1172271368                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1172271368                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    739458183                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    739458183                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4    739458183                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total    739458183                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.803980                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.803980                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.953941                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.953941                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.857775                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.857775                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.857775                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.857775                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17456.715168                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17456.715168                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22158.816378                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22158.816378                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19332.608275                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19332.608275                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19332.608275                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19332.608275                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74866.678445                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74866.678445                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48019.883304                       # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48019.883304                       # average overall mshr uncacheable latency
+system.cpu5.num_reads                           99665                       # number of read accesses completed
+system.cpu5.num_writes                          55439                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22286                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             391.859990                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13458                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22703                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.592785                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      391.576438                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.764798                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.764798                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          384                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              336606                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             336606                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8524                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8524                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1134                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1134                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9658                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9658                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9658                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9658                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36435                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36435                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           23892                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          23892                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             60327                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            60327                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            60327                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           60327                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    644721410                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    644721410                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    540612961                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    540612961                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1185334371                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1185334371                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1185334371                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1185334371                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          44959                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         44959                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         25026                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        25026                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           69985                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          69985                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          69985                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         69985                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.810405                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.810405                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954687                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.954687                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.861999                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.861999                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.861999                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.861999                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17695.112117                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 17695.112117                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 22627.363176                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 22627.363176                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 19648.488587                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 19648.488587                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 19648.488587                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 19648.488587                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs       717184                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      391.859990                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.765352                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.765352                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          417                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          407                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.814453                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              338594                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             338594                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8649                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8649                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1196                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1196                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9845                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9845                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9845                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9845                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36574                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36574                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           24003                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          24003                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60577                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60577                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60577                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60577                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    671451246                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    671451246                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    559158053                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    559158053                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1230609299                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1230609299                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1230609299                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1230609299                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          45223                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         45223                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25199                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25199                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           70422                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          70422                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          70422                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         70422                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808748                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.808748                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952538                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.952538                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.860200                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.860200                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.860200                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.860200                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18358.704161                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 18358.704161                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23295.340291                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 23295.340291                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 20314.794377                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 20314.794377                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 20314.794377                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 20314.794377                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs       802483                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               58708                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               66128                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.216120                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.135298                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9910                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9910                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36435                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36435                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23892                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        23892                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        60327                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        60327                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        60327                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        60327                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9763                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9763                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5458                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5458                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15221                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15221                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    608288410                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    608288410                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    516720961                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    516720961                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1125009371                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1125009371                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1125009371                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1125009371                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    723860386                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    723860386                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    946272316                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    946272316                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1670132702                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1670132702                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.810405                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.810405                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954687                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954687                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.861999                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.861999                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.861999                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.861999                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16695.167010                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16695.167010                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 21627.363176                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 21627.363176                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18648.521740                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18648.521740                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18648.521740                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18648.521740                       # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74143.233227                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74143.233227                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 173373.454745                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173373.454745                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 109725.556928                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 109725.556928                       # average overall mshr uncacheable latency
-system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                           99860                       # number of read accesses completed
-system.cpu6.num_writes                          55212                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22379                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             392.641405                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13476                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22769                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.591857                       # Average number of references to valid blocks.
+system.cpu5.l1c.writebacks::writebacks           9886                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9886                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36574                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36574                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        24003                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        24003                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60577                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60577                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60577                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60577                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9910                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9910                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5451                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5451                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15361                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15361                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    634877246                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    634877246                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    535156053                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    535156053                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1170033299                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1170033299                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1170033299                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1170033299                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    742019082                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    742019082                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5    742019082                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total    742019082                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808748                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808748                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952538                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952538                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.860200                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.860200                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.860200                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.860200                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17358.704161                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17358.704161                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22295.381952                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22295.381952                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19314.810885                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19314.810885                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19314.810885                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19314.810885                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74875.790313                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74875.790313                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 48305.389102                       # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 48305.389102                       # average overall mshr uncacheable latency
+system.cpu6.num_reads                           99712                       # number of read accesses completed
+system.cpu6.num_writes                          55282                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22239                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             392.046110                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13503                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22637                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.596501                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      392.641405                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.766878                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.766878                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              338111                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             338111                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8761                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8761                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1100                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1100                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9861                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9861                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9861                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9861                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36533                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36533                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23935                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23935                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60468                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60468                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60468                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60468                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    641137331                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    641137331                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    545446790                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    545446790                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1186584121                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1186584121                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1186584121                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1186584121                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45294                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45294                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         25035                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        25035                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70329                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70329                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70329                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70329                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806575                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.806575                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956062                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.956062                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.859788                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.859788                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.859788                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.859788                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17549.539622                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 17549.539622                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 22788.668895                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 22788.668895                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 19623.339965                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 19623.339965                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 19623.339965                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 19623.339965                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs       722832                       # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6      392.046110                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.765715                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.765715                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              338073                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             338073                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8758                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8758                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1067                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1067                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9825                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9825                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9825                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9825                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36548                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36548                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           23952                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          23952                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60500                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60500                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60500                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60500                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    674135322                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    674135322                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    560982121                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    560982121                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1235117443                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1235117443                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1235117443                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1235117443                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45306                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45306                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         25019                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        25019                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70325                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70325                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70325                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70325                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806692                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.806692                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.957352                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.957352                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.860292                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.860292                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.860292                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.860292                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18445.204170                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 18445.204170                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23421.097236                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 23421.097236                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 20415.164347                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 20415.164347                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 20415.164347                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 20415.164347                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs       802988                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               59177                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               65839                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.214746                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.196236                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9900                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9900                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36533                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36533                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23935                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23935                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60468                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60468                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60468                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60468                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9853                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9853                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5386                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5386                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15239                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15239                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    604606331                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    604606331                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    521511790                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    521511790                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1126118121                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1126118121                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1126118121                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1126118121                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    730958843                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    730958843                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    936459347                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    936459347                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1667418190                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1667418190                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806575                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806575                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956062                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956062                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859788                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.859788                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859788                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.859788                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16549.594367                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16549.594367                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 21788.668895                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 21788.668895                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18623.373040                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18623.373040                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18623.373040                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18623.373040                       # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74186.424744                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74186.424744                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 173869.169514                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173869.169514                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 109417.822036                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 109417.822036                       # average overall mshr uncacheable latency
-system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99316                       # number of read accesses completed
-system.cpu7.num_writes                          55530                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22262                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             392.242621                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13656                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22650                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.602914                       # Average number of references to valid blocks.
+system.cpu6.l1c.writebacks::writebacks           9826                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9826                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36548                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36548                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23952                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        23952                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60500                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60500                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60500                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60500                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9861                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9861                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5592                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5592                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15453                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15453                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    637587322                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    637587322                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    537030121                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    537030121                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1174617443                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1174617443                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1174617443                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1174617443                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    737828201                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    737828201                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6    737828201                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total    737828201                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806692                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806692                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.957352                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.957352                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.860292                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.860292                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.860292                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.860292                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17445.204170                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17445.204170                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22421.097236                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22421.097236                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19415.164347                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19415.164347                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19415.164347                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19415.164347                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74822.857824                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74822.857824                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 47746.599431                       # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 47746.599431                       # average overall mshr uncacheable latency
+system.cpu7.num_reads                           99031                       # number of read accesses completed
+system.cpu7.num_writes                          54931                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22638                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             391.993848                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13556                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               23038                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.588419                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      392.242621                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.766099                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.766099                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          388                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          370                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              338652                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             338652                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8912                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8912                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1186                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1186                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7               10098                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total              10098                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7              10098                       # number of overall hits
-system.cpu7.l1c.overall_hits::total             10098                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36380                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36380                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23998                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23998                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60378                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60378                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60378                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60378                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    644409565                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    644409565                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    538142857                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    538142857                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1182552422                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1182552422                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1182552422                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1182552422                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45292                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45292                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         25184                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        25184                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70476                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70476                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70476                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70476                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.803232                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.803232                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.952907                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.952907                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.856717                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.856717                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.856717                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.856717                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17713.292056                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 17713.292056                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 22424.487749                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 22424.487749                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 19585.816390                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 19585.816390                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 19585.816390                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 19585.816390                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs       716334                       # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7      391.993848                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.765613                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.765613                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          386                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              339734                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             339734                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8818                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8818                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1148                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1148                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9966                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9966                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9966                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9966                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36554                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36554                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           24149                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          24149                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60703                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60703                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60703                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60703                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    675691654                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    675691654                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    565139421                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    565139421                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1240831075                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1240831075                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1240831075                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1240831075                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45372                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45372                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         25297                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        25297                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70669                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70669                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70669                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70669                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.805651                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.805651                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954619                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.954619                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.858976                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.858976                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.858976                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.858976                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18484.752804                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 18484.752804                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23402.187296                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 23402.187296                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 20441.017330                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 20441.017330                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 20441.017330                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 20441.017330                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs       799894                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               58812                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               65859                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.180065                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.145553                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
-system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9846                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9846                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36380                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36380                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23998                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23998                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60378                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60378                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60378                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60378                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9762                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9762                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5539                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5539                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15301                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15301                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    608029565                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    608029565                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    514144857                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    514144857                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1122174422                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1122174422                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1122174422                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1122174422                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    722808914                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    722808914                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    961004780                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    961004780                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1683813694                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1683813694                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.803232                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.803232                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.952907                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.952907                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.856717                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.856717                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.856717                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.856717                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16713.292056                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16713.292056                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 21424.487749                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 21424.487749                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18585.816390                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18585.816390                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18585.816390                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18585.816390                       # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 74043.117599                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74043.117599                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 173497.884095                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173497.884095                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 110045.990066                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 110045.990066                       # average overall mshr uncacheable latency
-system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    13767                       # number of replacements
-system.l2c.tags.tagsinuse                  787.442113                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     164717                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    14568                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    11.306768                       # Average number of references to valid blocks.
+system.cpu7.l1c.writebacks::writebacks           9912                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9912                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36554                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36554                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        24149                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        24149                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60703                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60703                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60703                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60703                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9740                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9740                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5359                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5359                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15099                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15099                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    639138654                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    639138654                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    540990421                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    540990421                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1180129075                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1180129075                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1180129075                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1180129075                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    730529776                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    730529776                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7    730529776                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total    730529776                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.805651                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.805651                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954619                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954619                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.858976                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.858976                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.858976                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.858976                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17484.780161                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17484.780161                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22402.187296                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22402.187296                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19441.033804                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19441.033804                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19441.033804                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19441.033804                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75003.057084                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.057084                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 48382.659514                       # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 48382.659514                       # average overall mshr uncacheable latency
+system.l2c.tags.replacements                    13688                       # number of replacements
+system.l2c.tags.tagsinuse                  782.559938                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     164623                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14478                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    11.370562                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     730.095360                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             6.568517                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             7.047502                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             7.052359                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             7.453742                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             6.826765                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             7.175771                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             7.149899                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             8.072198                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.712984                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.006415                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.006882                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.006887                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.007279                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.006667                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.007008                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.006982                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.007883                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.768986                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          801                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          661                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          140                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.782227                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  2101238                       # Number of tag accesses
-system.l2c.tags.data_accesses                 2101238                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks        77585                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total           77585                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0                  280                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  286                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  296                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  265                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  264                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  299                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  295                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  273                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2258                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1755                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1883                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1739                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  1749                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1791                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1796                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1820                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1726                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                14259                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0             10845                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1             10830                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2             10896                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3             10859                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4             10783                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5             11038                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6             10953                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7             10583                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total            86787                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0                    12600                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12713                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12635                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12608                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12574                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12834                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12773                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12309                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  101046                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12600                       # number of overall hits
-system.l2c.overall_hits::cpu1                   12713                       # number of overall hits
-system.l2c.overall_hits::cpu2                   12635                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12608                       # number of overall hits
-system.l2c.overall_hits::cpu4                   12574                       # number of overall hits
-system.l2c.overall_hits::cpu5                   12834                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12773                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12309                       # number of overall hits
-system.l2c.overall_hits::total                 101046                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0               2028                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               2036                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               2114                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2014                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               2072                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               1987                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               2026                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               2019                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             16296                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4674                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4592                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4655                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4541                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4557                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4639                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4724                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4602                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              36984                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0             715                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1             735                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2             738                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3             731                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu4             726                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu5             715                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu6             671                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu7             749                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total           5780                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0                   5389                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5327                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5393                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5272                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5283                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5354                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   5395                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5351                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 42764                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5389                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5327                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5393                       # number of overall misses
-system.l2c.overall_misses::cpu3                  5272                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5283                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5354                       # number of overall misses
-system.l2c.overall_misses::cpu6                  5395                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5351                       # number of overall misses
-system.l2c.overall_misses::total                42764                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0     32787478                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     32272475                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     34405982                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     32097495                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     34646656                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     31653981                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     32901471                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     32271475                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    263037013                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     151347885                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     149012881                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     150333871                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     147794053                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     149925888                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     151442380                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     154217889                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     149568871                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1203643718                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0     49081904                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1     50341908                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2     51226892                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3     50079413                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu4     49691401                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu5     48946419                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu6     46272414                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu7     51820900                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total    397461251                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0        200429789                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        199354789                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2        201560763                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3        197873466                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4        199617289                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5        200388799                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        200490303                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        201389771                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      1601104969                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       200429789                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1       199354789                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2       201560763                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       197873466                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       199617289                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       200388799                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       200490303                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       201389771                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     1601104969                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks        77585                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total        77585                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2308                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2322                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2410                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2279                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2336                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2286                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2321                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2292                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18554                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6429                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1              6475                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2              6394                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3              6290                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4              6348                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5              6435                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6              6544                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7              6328                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            51243                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0         11560                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1         11565                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2         11634                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3         11590                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu4         11509                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu5         11753                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu6         11624                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu7         11332                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total        92567                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0                17989                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1                18040                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2                18028                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3                17880                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4                17857                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5                18188                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6                18168                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7                17660                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              143810                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0               17989                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1               18040                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2               18028                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3               17880                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4               17857                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5               18188                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6               18168                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               17660                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             143810                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.878683                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.876830                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.877178                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.883721                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.886986                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.869204                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.872900                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.880890                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.878301                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.727018                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.709189                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.728026                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.721940                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.717864                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.720901                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.721883                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.727244                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.721738                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0     0.061851                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1     0.063554                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2     0.063435                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3     0.063072                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu4     0.063081                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu5     0.060836                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu6     0.057725                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu7     0.066096                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.062441                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0            0.299572                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.295288                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.299146                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.294855                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.295850                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.294370                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.296951                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.303001                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.297365                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.299572                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.295288                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.299146                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.294855                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.295850                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.294370                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.296951                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.303001                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.297365                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 16167.395464                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 15850.920923                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 16275.298959                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 15937.187190                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 16721.359073                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 15930.539004                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 16239.620434                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 15983.890540                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 16141.201092                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 32380.805520                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 32450.540287                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 32295.138776                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 32546.587316                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 32900.129032                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 32645.479629                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 32645.615792                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 32500.841156                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 32544.984804                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68646.019580                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68492.391837                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69413.132791                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68508.088919                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68445.455923                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68456.530070                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68960.378539                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69186.782377                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 68764.922318                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 37192.389868                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 37423.463300                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 37374.515668                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 37532.903263                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 37784.836078                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 37427.866829                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 37162.243373                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 37635.913100                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 37440.486601                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 37192.389868                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 37423.463300                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 37374.515668                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 37532.903263                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 37784.836078                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 37427.866829                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 37162.243373                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 37635.913100                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 37440.486601                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             15217                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks     726.348525                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             6.677170                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             6.765222                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             6.924842                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             7.010620                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             7.585654                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             6.814501                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             7.441816                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             6.991588                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.709325                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006521                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.006607                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2            0.006763                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3            0.006846                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4            0.007408                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5            0.006655                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6            0.007267                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7            0.006828                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.764219                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          790                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          664                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  2107372                       # Number of tag accesses
+system.l2c.tags.data_accesses                 2107372                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks        77671                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total           77671                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0                  272                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  284                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  276                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  280                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  255                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  283                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  239                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  262                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                2151                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0                  1876                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1                  1780                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2                  1805                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3                  1782                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu4                  1816                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu5                  1727                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu6                  1803                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu7                  1809                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                14398                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0             10873                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1             10958                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2             10812                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3             11007                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu4             10755                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu5             10989                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu6             11012                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu7             10808                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total            87214                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0                    12749                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1                    12738                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2                    12617                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3                    12789                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu4                    12571                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu5                    12716                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu6                    12815                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu7                    12617                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  101612                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0                   12749                       # number of overall hits
+system.l2c.overall_hits::cpu1                   12738                       # number of overall hits
+system.l2c.overall_hits::cpu2                   12617                       # number of overall hits
+system.l2c.overall_hits::cpu3                   12789                       # number of overall hits
+system.l2c.overall_hits::cpu4                   12571                       # number of overall hits
+system.l2c.overall_hits::cpu5                   12716                       # number of overall hits
+system.l2c.overall_hits::cpu6                   12815                       # number of overall hits
+system.l2c.overall_hits::cpu7                   12617                       # number of overall hits
+system.l2c.overall_hits::total                 101612                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0               2119                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1               2003                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2               2061                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3               2101                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4               1934                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu5               2026                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu6               2139                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu7               2027                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             16410                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0                4596                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1                4672                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2                4641                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3                4561                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu4                4696                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu5                4677                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu6                4637                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu7                4651                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              37131                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0             698                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1             712                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2             734                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3             737                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu4             740                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu5             681                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu6             738                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu7             697                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           5737                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0                   5294                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1                   5384                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2                   5375                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3                   5298                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu4                   5436                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu5                   5358                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu6                   5375                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu7                   5348                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                 42868                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0                  5294                       # number of overall misses
+system.l2c.overall_misses::cpu1                  5384                       # number of overall misses
+system.l2c.overall_misses::cpu2                  5375                       # number of overall misses
+system.l2c.overall_misses::cpu3                  5298                       # number of overall misses
+system.l2c.overall_misses::cpu4                  5436                       # number of overall misses
+system.l2c.overall_misses::cpu5                  5358                       # number of overall misses
+system.l2c.overall_misses::cpu6                  5375                       # number of overall misses
+system.l2c.overall_misses::cpu7                  5348                       # number of overall misses
+system.l2c.overall_misses::total                42868                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0     34306000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1     32515999                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2     33970000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3     33665000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu4     30524499                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu5     33417998                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu6     35180998                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu7     31945000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    265525494                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0     148628443                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1     153234943                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2     151708946                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3     148204781                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu4     153854439                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu5     151693945                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu6     152734439                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu7     151392920                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1211452856                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0     49327224                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1     49579908                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2     50488876                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3     50929398                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu4     51564743                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu5     47695729                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu6     51087902                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu7     48881401                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total    399555181                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0        197955667                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1        202814851                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2        202197822                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3        199134179                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu4        205419182                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu5        199389674                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu6        203822341                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu7        200274321                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      1611008037                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0       197955667                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1       202814851                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2       202197822                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3       199134179                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu4       205419182                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu5       199389674                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu6       203822341                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu7       200274321                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     1611008037                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks        77671                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total        77671                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0             2391                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1             2287                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2             2337                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3             2381                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu4             2189                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu5             2309                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu6             2378                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu7             2289                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           18561                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0              6472                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1              6452                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2              6446                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3              6343                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu4              6512                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu5              6404                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu6              6440                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu7              6460                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            51529                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0         11571                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1         11670                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2         11546                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3         11744                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu4         11495                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu5         11670                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu6         11750                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu7         11505                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total        92951                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0                18043                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1                18122                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2                17992                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3                18087                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu4                18007                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu5                18074                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu6                18190                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu7                17965                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              144480                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0               18043                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu3               18087                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu4               18007                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu6               18190                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu7               17965                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             144480                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0        0.886240                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.875820                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.881900                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.882402                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.883508                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.877436                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.899495                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.885540                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.884112                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.710136                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.724117                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.719981                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.719060                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.721130                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.730325                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.720031                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.719969                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.720585                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0     0.060323                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1     0.061011                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2     0.063572                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3     0.062755                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu4     0.064376                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu5     0.058355                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu6     0.062809                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu7     0.060582                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.061721                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0            0.293410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.297097                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2            0.298744                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3            0.292918                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.301883                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.296448                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.295492                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.297690                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.296705                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.293410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.297097                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.298744                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.292918                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.301883                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.296448                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.295492                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.297690                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.296705                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 16189.712128                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 16233.649026                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 16482.290150                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 16023.322228                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 15783.091520                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 16494.569595                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 16447.404395                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 15759.743463                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 16180.712614                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 32338.651654                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 32798.575128                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 32688.848524                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 32493.922605                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 32762.870315                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 32434.027154                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 32938.201208                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 32550.617072                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 32626.453799                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70669.375358                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69634.702247                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68785.934605                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69103.660787                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69682.085135                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70037.781204                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69224.799458                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70131.134864                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 69645.316542                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 37392.456932                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 37669.920319                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 37618.199442                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 37586.670253                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 37788.664827                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 37213.451661                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 37920.435535                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 37448.451945                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 37580.667094                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 37392.456932                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 37669.920319                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 37618.199442                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 37586.670253                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 37788.664827                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 37213.451661                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 37920.435535                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 37448.451945                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 37580.667094                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             19223                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     2217                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     2973                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      6.863780                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      6.465859                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6315                       # number of writebacks
-system.l2c.writebacks::total                     6315                       # number of writebacks
-system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                6                       # number of ReadExReq MSHR hits
+system.l2c.writebacks::writebacks                6255                       # number of writebacks
+system.l2c.writebacks::total                     6255                       # number of writebacks
+system.l2c.UpgradeReq_mshr_hits::cpu2               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu6               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total              2                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                2                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu1                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                2                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                8                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              38                       # number of ReadExReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1            7                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2            5                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3            6                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu4           11                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu5           10                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu6            3                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu7            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           59                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                  19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                  10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                  11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  13                       # number of demand (read+write) MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu2                9                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
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+system.l2c.ReadExReq_mshr_hits::cpu5                5                       # number of ReadExReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu5                  14                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu5                 14                       # number of overall MSHR hits
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+system.l2c.demand_mshr_misses::cpu5              5344                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5362                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5333                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            42745                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5281                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5370                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5352                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5282                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5421                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5             5344                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6             5362                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5333                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           42745                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0         9743                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1         9811                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2         9985                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3         9849                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu4         9877                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu5         9910                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu6         9861                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu7         9739                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        78775                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0         5399                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1         5467                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2         5427                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3         5579                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu4         5520                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu5         5451                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu6         5590                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu7         5357                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        43790                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0        15142                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1        15278                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2        15412                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3        15428                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu4        15397                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu5        15361                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu6        15451                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu7        15096                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       122565                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     40841935                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     38564215                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     39647592                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     40417370                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     37145795                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     38899918                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     41229107                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     39009527                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    315755459                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    102604763                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    106353151                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    105053935                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    102451130                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    106647279                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    104810242                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    106228599                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    104763871                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total    838912970                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     41984323                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     42028851                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     42690563                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     43142020                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     43825891                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     40479162                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     43405339                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     41523836                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    339079985                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    144589086                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    148382002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    147744498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    145593150                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    150473170                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    145289404                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    149633938                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    146287707                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1177992955                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    144589086                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    148382002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    147744498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    145593150                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    150473170                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    145289404                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    149633938                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    146287707                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1177992955                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    506398152                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    509332752                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    518417832                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    511679337                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    512962712                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    514656758                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    512189388                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    505729590                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   4091366521                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    506398152                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    509332752                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    518417832                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    511679337                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    512962712                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    514656758                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    512189388                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    505729590                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4091366521                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.878683                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.876830                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.877178                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.883282                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.886558                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.869204                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.872900                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.880454                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.878139                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.726085                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.708571                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.727244                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.721145                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.717549                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.720280                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.721271                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.725980                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.720996                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.060727                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.062949                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.063005                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.062554                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.062125                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.059985                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.057467                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.065743                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.061804                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.298516                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.294678                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.298591                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.294239                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.295122                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.293600                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.296565                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.302322                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.296690                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.298516                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.294678                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.298591                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.294239                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.295122                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.293600                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.296565                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.302322                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.296690                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19237.777613                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19269.184185                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19290.727058                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19303.659712                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19276.070014                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19248.586311                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19230.378578                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19251.534192                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19263.681397                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22354.528063                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22422.961857                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22275.815054                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22547.604718                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22884.830516                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22625.916073                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22633.139407                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22492.943404                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 22529.055513                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59120.613960                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58754.313187                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59471.547067                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58655.411034                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58813.765035                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 58747.060993                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58985.702096                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59138.512752                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58962.207481                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 27160.820857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 27398.361362                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 27340.736392                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 27523.495153                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 27759.439279                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 27394.718914                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 27140.101522                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 27606.438284                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 27414.190686                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 27160.820857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 27398.361362                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 27340.736392                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 27523.495153                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 27759.439279                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 27394.718914                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 27140.101522                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 27606.438284                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 27414.190686                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51836.922617                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51834.520021                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51837.208150                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51831.934617                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51793.861967                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51846.302571                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51891.205644                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51793.501639                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51833.236869                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53272.199599                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53730.930556                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54048.480716                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53785.831524                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53636.094044                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53581.986259                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53652.224285                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53756.660347                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53682.780686                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 52355.251201                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52512.033543                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52626.282695                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 52528.620274                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 52451.299750                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 52468.690165                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52513.652579                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 52504.088105                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 52495.065513                       # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               78306                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84006                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43633                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43633                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty         6315                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             1254                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            60980                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             48711                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3097                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          5709                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       375644                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 375644                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1089674                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1089674                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            56426                       # Total snoops (count)
-system.membus.snoop_fanout::samples            252331                       # Request fanout histogram
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.886240                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.875820                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.881472                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.882402                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.883508                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.877436                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.899075                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.885540                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.884004                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.709827                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.723497                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.718585                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.718587                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.720055                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.729544                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.719255                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.719195                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.719808                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.059373                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.060154                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.062359                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.061649                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.063680                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.057584                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.062128                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.059713                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.060828                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.292690                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.296325                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.297466                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.292033                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.301050                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.295673                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.294777                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.296855                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.295854                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.292690                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.296325                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.297466                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.292033                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.301050                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.295673                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.294777                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.296855                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.295854                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19274.155262                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19253.227659                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19246.403883                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19237.206092                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19206.719235                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19200.354393                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19283.960243                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19244.956586                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19243.994332                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22334.515237                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22783.451371                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22680.037781                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22477.211496                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22744.141395                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22433.699058                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22933.635363                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22549.261946                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 22617.696207                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61112.551674                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59870.158120                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59292.448611                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59588.425414                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59871.435792                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60236.848214                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59459.368493                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60442.264920                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59971.698797                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 27379.111153                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 27631.657728                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 27605.474215                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 27564.019311                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 27757.456189                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 27187.388473                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 27906.366654                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 27430.659479                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 27558.613990                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 27379.111153                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 27631.657728                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 27605.474215                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 27564.019311                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 27757.456189                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 27187.388473                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 27906.366654                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 27430.659479                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 27558.613990                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51975.587807                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51914.458465                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51919.662694                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51952.415169                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51935.072593                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51933.073461                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51940.917554                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51928.287298                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51937.372529                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 33443.280412                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 33337.658856                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 33637.284713                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 33165.629829                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 33315.757096                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 33504.118091                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 33149.271115                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 33500.900238                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 33381.197903                       # average overall mshr uncacheable latency
+system.membus.trans_dist::ReadReq               78773                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84410                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43787                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43783                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty         6255                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             1278                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            61348                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             49073                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3087                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          5646                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       377440                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 377440                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1081783                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1081783                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            56900                       # Total snoops (count)
+system.membus.snoop_fanout::samples            253448                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  252331    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  253448    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              252331                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           290210873                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              54.7                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          244257000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             46.1                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests       663692                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       283641                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       333885                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          12353                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         5692                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         6661                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              78309                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            370176                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43636                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43632                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty        83900                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          105566                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29367                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29367                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           161854                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          161852                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       291888                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133128                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133137                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       133276                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133136                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       132901                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133285                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133385                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       132788                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1065036                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1790740                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1793737                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1783183                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1779785                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1777562                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1801715                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1799686                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1764480                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14290888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          334512                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           624442                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.148246                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.987708                       # Request fanout histogram
+system.membus.snoop_fanout::total              253448                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           289313112                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              57.8                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          244976000                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             49.0                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests       662658                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       284136                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       332740                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          12293                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         5765                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         6528                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              78775                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            371396                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43790                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43780                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty        83926                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          105295                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29475                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29475                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           162920                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          162916                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       292639                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133502                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133647                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       133520                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133779                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       133547                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133528                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133790                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       133396                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1068709                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1800550                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1795691                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1783667                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1792707                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1790564                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1791999                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1796631                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1788086                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14339895                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          335681                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           623777                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.148975                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.984758                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 174331     27.92%     27.92% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 257461     41.23%     69.15% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 132941     21.29%     90.44% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                  47060      7.54%     97.97% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  10899      1.75%     99.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                   1610      0.26%     99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                    136      0.02%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      4      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 172972     27.73%     27.73% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 258444     41.43%     69.16% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 133198     21.35%     90.52% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                  46670      7.48%     98.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  10752      1.72%     99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                   1603      0.26%     99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                    135      0.02%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                      3      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             624442                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          496537925                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization             93.7                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         101982318                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         102105458                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization            19.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         101942894                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         101777352                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         101724075                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         101820787                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            19.2                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         102063169                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization            19.3                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         101980781                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total             623777                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          493769156                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             98.7                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         102470874                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy         102502346                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         102645272                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         102492443                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         102725884                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy         102549521                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         102424000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization            20.5                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy         102560017                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization            20.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 8e6ab353a..e76d0cce6 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.134742                       # Nu
 sim_ticks                                134741611500                       # Number of ticks simulated
 final_tick                               134741611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 536259                       # Simulator instruction rate (inst/s)
-host_op_rate                                   536259                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              817928903                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239376                       # Number of bytes of host memory used
-host_seconds                                   164.74                       # Real time elapsed on the host
+host_inst_rate                                1303886                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1303885                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1988750581                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260188                       # Number of bytes of host memory used
+host_seconds                                    67.75                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -198,8 +198,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168278                       # number of writebacks
 system.cpu.dcache.writebacks::total            168278                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60766                       # number of ReadReq MSHR misses
@@ -234,7 +232,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             74391                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1870.507754                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            88361638                       # Total number of references to valid blocks.
@@ -294,8 +291,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        74391                       # number of writebacks
 system.cpu.icache.writebacks::total             74391                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        76436                       # number of ReadReq MSHR misses
@@ -322,7 +317,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149
 system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           131998                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30708.485304                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             247404                       # Total number of references to valid blocks.
@@ -431,8 +425,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114382                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114382                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          105                       # number of CleanEvict MSHR misses
@@ -487,7 +479,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       555419                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       274639                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index c10ef56cb..2518d4d22 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.128077                       # Nu
 sim_ticks                                128076834500                       # Number of ticks simulated
 final_tick                               128076834500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 508798                       # Simulator instruction rate (inst/s)
-host_op_rate                                   649592                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              925989388                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253236                       # Number of bytes of host memory used
-host_seconds                                   138.31                       # Real time elapsed on the host
+host_inst_rate                                 775777                       # Simulator instruction rate (inst/s)
+host_op_rate                                   990450                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1411878896                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277764                       # Number of bytes of host memory used
+host_seconds                                    90.71                       # Real time elapsed on the host
 sim_insts                                    70373651                       # Number of instructions simulated
 sim_ops                                      89847385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -300,8 +300,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       128175                       # number of writebacks
 system.cpu.dcache.writebacks::total            128175                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data         7598                       # number of ReadReq MSHR hits
@@ -350,7 +348,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             16890                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1732.356634                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78126184                       # Total number of references to valid blocks.
@@ -410,8 +407,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        16890                       # number of writebacks
 system.cpu.icache.writebacks::total             16890                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18908                       # number of ReadReq MSHR misses
@@ -438,7 +433,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947
 system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            95333                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30336.891531                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             114380                       # Total number of references to valid blocks.
@@ -547,8 +541,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        86150                       # number of writebacks
 system.cpu.l2cache.writebacks::total            86150                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          104                       # number of CleanEvict MSHR misses
@@ -603,7 +595,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       351698                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       172817                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3696                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 75f9fb3c6..97bc2f274 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.203116                       # Nu
 sim_ticks                                203115946500                       # Number of ticks simulated
 final_tick                               203115946500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 864116                       # Simulator instruction rate (inst/s)
-host_op_rate                                   875304                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1305930078                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235576                       # Number of bytes of host memory used
-host_seconds                                   155.53                       # Real time elapsed on the host
+host_inst_rate                                1277402                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1293942                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1930526358                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259920                       # Number of bytes of host memory used
+host_seconds                                   105.21                       # Real time elapsed on the host
 sim_insts                                   134398959                       # Number of instructions simulated
 sim_ops                                     136139187                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -178,8 +178,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       123865                       # number of writebacks
 system.cpu.dcache.writebacks::total            123865                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        45500                       # number of ReadReq MSHR misses
@@ -222,7 +220,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            184976                       # number of replacements
 system.cpu.icache.tags.tagsinuse          2004.181265                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           134366557                       # Total number of references to valid blocks.
@@ -283,8 +280,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       184976                       # number of writebacks
 system.cpu.icache.writebacks::total            184976                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       187024                       # number of ReadReq MSHR misses
@@ -311,7 +306,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245
 system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            99022                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30843.699683                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             433832                       # Total number of references to valid blocks.
@@ -420,8 +414,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        85270                       # number of writebacks
 system.cpu.l2cache.writebacks::total            85270                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           96                       # number of CleanEvict MSHR misses
@@ -476,7 +468,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       669262                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       331559                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests           66                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index da47b432f..c2aa1fab9 100644
--- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.118763                       # Nu
 sim_ticks                                118762761500                       # Number of ticks simulated
 final_tick                               118762761500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 546473                       # Simulator instruction rate (inst/s)
-host_op_rate                                   546472                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              706184987                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235092                       # Number of bytes of host memory used
-host_seconds                                   168.18                       # Real time elapsed on the host
+host_inst_rate                                1409040                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1409039                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1820846467                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255756                       # Number of bytes of host memory used
+host_seconds                                    65.22                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -193,8 +193,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
@@ -229,7 +227,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              6681                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1417.953327                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            91894580                       # Total number of references to valid blocks.
@@ -290,8 +287,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         6681                       # number of writebacks
 system.cpu.icache.writebacks::total              6681                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8510                       # number of ReadReq MSHR misses
@@ -318,7 +313,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123
 system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2073.923151                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              12687                       # Total number of references to valid blocks.
@@ -427,8 +421,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1722                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1722                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2621                       # number of ReadCleanReq MSHR misses
@@ -477,7 +469,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        17571                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         6838                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 9f34f3699..d21481ee3 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.230198                       # Nu
 sim_ticks                                230197694500                       # Number of ticks simulated
 final_tick                               230197694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1151849                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1214340                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1543000471                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 272972                       # Number of bytes of host memory used
-host_seconds                                   149.19                       # Real time elapsed on the host
+host_inst_rate                                 927075                       # Simulator instruction rate (inst/s)
+host_op_rate                                   977372                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1241896591                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272260                       # Number of bytes of host memory used
+host_seconds                                   185.36                       # Real time elapsed on the host
 sim_insts                                   171842484                       # Number of instructions simulated
 sim_ops                                     181165371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -295,8 +295,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          688                       # number of ReadReq MSHR misses
@@ -339,7 +337,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1506                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1147.958164                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           189857002                       # Total number of references to valid blocks.
@@ -400,8 +397,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         1506                       # number of writebacks
 system.cpu.icache.writebacks::total              1506                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3051                       # number of ReadReq MSHR misses
@@ -428,7 +423,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067
 system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         1675.610098                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               2846                       # Total number of references to valid blocks.
@@ -537,8 +531,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1092                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1092                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1729                       # number of ReadCleanReq MSHR misses
@@ -587,7 +579,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests         6386                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         1644                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests           64                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 9e9ac48d5..c87fb96c4 100644
--- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.270600                       # Nu
 sim_ticks                                270599529500                       # Number of ticks simulated
 final_tick                               270599529500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 568132                       # Simulator instruction rate (inst/s)
-host_op_rate                                   568133                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              794730164                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235264                       # Number of bytes of host memory used
-host_seconds                                   340.49                       # Real time elapsed on the host
+host_inst_rate                                1248385                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1248386                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1746300725                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255364                       # Number of bytes of host memory used
+host_seconds                                   154.96                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -173,8 +173,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks            2                       # number of writebacks
 system.cpu.dcache.writebacks::total                 2                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          498                       # number of ReadReq MSHR misses
@@ -217,7 +215,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             10362                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1591.528232                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           193433248                       # Total number of references to valid blocks.
@@ -278,8 +275,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        10362                       # number of writebacks
 system.cpu.icache.writebacks::total             10362                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12288                       # number of ReadReq MSHR misses
@@ -306,7 +301,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828
 system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2678.246108                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              19053                       # Total number of references to valid blocks.
@@ -409,8 +403,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1078                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1078                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3597                       # number of ReadCleanReq MSHR misses
@@ -459,7 +451,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        24228                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        10365                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 01cb3bdc8..25c6ff3ba 100644
--- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.250987                       # Nu
 sim_ticks                                250987138500                       # Number of ticks simulated
 final_tick                               250987138500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 290260                       # Simulator instruction rate (inst/s)
-host_op_rate                                   486501                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              551606975                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279340                       # Number of bytes of host memory used
-host_seconds                                   455.01                       # Real time elapsed on the host
+host_inst_rate                                 637690                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1068827                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1211861746                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298388                       # Number of bytes of host memory used
+host_seconds                                   207.11                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,8 +164,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks            7                       # number of writebacks
 system.cpu.dcache.writebacks::total                 7                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          327                       # number of ReadReq MSHR misses
@@ -200,7 +198,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2836                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1455.245085                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           173489673                       # Total number of references to valid blocks.
@@ -261,8 +258,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         2836                       # number of writebacks
 system.cpu.icache.writebacks::total              2836                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4694                       # number of ReadReq MSHR misses
@@ -289,7 +284,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467
 system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse         2058.105553                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               4732                       # Total number of references to valid blocks.
@@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1575                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1575                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2840                       # number of ReadCleanReq MSHR misses
@@ -448,7 +440,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests         9476                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         2878                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.