diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-02-19 07:59:46 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-02-19 07:59:46 -0500 |
| commit | fd9343eb857493ba7bade90d99a945f5577ab7ab (patch) | |
| tree | 8807d425acf7a49ca457fb814b4ab1b1d647784c /tests | |
| parent | 6b765ba8b79814eddaa4c10a5cc140b636bb9df8 (diff) | |
| download | gem5-fd9343eb857493ba7bade90d99a945f5577ab7ab.tar.xz | |
arm: Bump stats after FS config script update
This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).
Diffstat (limited to 'tests')
11 files changed, 12534 insertions, 12557 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 1902f9930..a0de7ff7f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526147 # Number of seconds simulated -sim_ticks 2526146947500 # Number of ticks simulated -final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526127 # Number of seconds simulated +sim_ticks 2526126762000 # Number of ticks simulated +final_tick 2526126762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57077 # Simulator instruction rate (inst/s) -host_op_rate 73443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2390895648 # Simulator tick rate (ticks/s) -host_mem_usage 424332 # Number of bytes of host memory used -host_seconds 1056.57 # Real time elapsed on the host -sim_insts 60306154 # Number of instructions simulated -sim_ops 77597242 # Number of ops (including micro ops) simulated +host_inst_rate 50904 # Simulator instruction rate (inst/s) +host_op_rate 65499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2132173780 # Simulator tick rate (ticks/s) +host_mem_usage 425424 # Number of bytes of host memory used +host_seconds 1184.77 # Real time elapsed on the host +sim_insts 60309150 # Number of instructions simulated +sim_ops 77600646 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093912 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096848 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47320533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1089 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3599943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51237470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1497768 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691719 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1497768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47320533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1089 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096836 # Number of read requests accepted -system.physmem.writeReqs 813120 # Number of write requests accepted -system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943071 # Per bank write bursts -system.physmem.perBankRdBursts::2 939289 # Per bank write bursts -system.physmem.perBankRdBursts::3 939279 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4793894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53929189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096848 # Number of read requests accepted +system.physmem.writeReqs 813136 # Number of write requests accepted +system.physmem.readBursts 15096848 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813136 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963809856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2388416 # Total number of bytes read from write queue +system.physmem.bytesWritten 6900096 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6799624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 37319 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705316 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4693 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943581 # Per bank write bursts +system.physmem.perBankRdBursts::1 943177 # Per bank write bursts +system.physmem.perBankRdBursts::2 939217 # Per bank write bursts +system.physmem.perBankRdBursts::3 939246 # Per bank write bursts system.physmem.perBankRdBursts::4 943119 # Per bank write bursts -system.physmem.perBankRdBursts::5 943242 # Per bank write bursts -system.physmem.perBankRdBursts::6 939090 # Per bank write bursts -system.physmem.perBankRdBursts::7 938633 # Per bank write bursts -system.physmem.perBankRdBursts::8 943981 # Per bank write bursts -system.physmem.perBankRdBursts::9 943506 # Per bank write bursts -system.physmem.perBankRdBursts::10 938534 # Per bank write bursts -system.physmem.perBankRdBursts::11 937721 # Per bank write bursts -system.physmem.perBankRdBursts::12 943933 # Per bank write bursts -system.physmem.perBankRdBursts::13 943406 # Per bank write bursts -system.physmem.perBankRdBursts::14 939034 # Per bank write bursts -system.physmem.perBankRdBursts::15 938886 # Per bank write bursts -system.physmem.perBankWrBursts::0 6687 # Per bank write bursts -system.physmem.perBankWrBursts::1 6452 # Per bank write bursts -system.physmem.perBankWrBursts::2 6617 # Per bank write bursts -system.physmem.perBankWrBursts::3 6618 # Per bank write bursts -system.physmem.perBankWrBursts::4 6551 # Per bank write bursts -system.physmem.perBankWrBursts::5 6799 # Per bank write bursts -system.physmem.perBankWrBursts::6 6798 # Per bank write bursts -system.physmem.perBankWrBursts::7 6724 # Per bank write bursts -system.physmem.perBankWrBursts::8 7121 # Per bank write bursts -system.physmem.perBankWrBursts::9 6870 # Per bank write bursts -system.physmem.perBankWrBursts::10 6536 # Per bank write bursts -system.physmem.perBankWrBursts::11 6184 # Per bank write bursts -system.physmem.perBankWrBursts::12 7152 # Per bank write bursts -system.physmem.perBankWrBursts::13 6752 # Per bank write bursts -system.physmem.perBankWrBursts::14 7039 # Per bank write bursts -system.physmem.perBankWrBursts::15 6901 # Per bank write bursts +system.physmem.perBankRdBursts::5 943143 # Per bank write bursts +system.physmem.perBankRdBursts::6 939192 # Per bank write bursts +system.physmem.perBankRdBursts::7 938854 # Per bank write bursts +system.physmem.perBankRdBursts::8 943994 # Per bank write bursts +system.physmem.perBankRdBursts::9 943547 # Per bank write bursts +system.physmem.perBankRdBursts::10 939009 # Per bank write bursts +system.physmem.perBankRdBursts::11 937977 # Per bank write bursts +system.physmem.perBankRdBursts::12 943925 # Per bank write bursts +system.physmem.perBankRdBursts::13 943586 # Per bank write bursts +system.physmem.perBankRdBursts::14 939160 # Per bank write bursts +system.physmem.perBankRdBursts::15 938802 # Per bank write bursts +system.physmem.perBankWrBursts::0 6706 # Per bank write bursts +system.physmem.perBankWrBursts::1 6463 # Per bank write bursts +system.physmem.perBankWrBursts::2 6599 # Per bank write bursts +system.physmem.perBankWrBursts::3 6631 # Per bank write bursts +system.physmem.perBankWrBursts::4 6542 # Per bank write bursts +system.physmem.perBankWrBursts::5 6795 # Per bank write bursts +system.physmem.perBankWrBursts::6 6787 # Per bank write bursts +system.physmem.perBankWrBursts::7 6728 # Per bank write bursts +system.physmem.perBankWrBursts::8 7129 # Per bank write bursts +system.physmem.perBankWrBursts::9 6879 # Per bank write bursts +system.physmem.perBankWrBursts::10 6534 # Per bank write bursts +system.physmem.perBankWrBursts::11 6185 # Per bank write bursts +system.physmem.perBankWrBursts::12 7139 # Per bank write bursts +system.physmem.perBankWrBursts::13 6761 # Per bank write bursts +system.physmem.perBankWrBursts::14 7032 # Per bank write bursts +system.physmem.perBankWrBursts::15 6904 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526145872500 # Total gap between requests +system.physmem.totGap 2526125654500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154590 # Read request sizes (log2) +system.physmem.readPktSize::6 154602 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59102 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1175583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1121241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1077080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3628602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2607512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2594359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2599949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -144,31 +144,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4767 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4787 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -176,574 +176,571 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 535 0.62% 56.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 547 0.64% 57.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 279 0.32% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 297 0.34% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 152 0.18% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 456 0.53% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 120 0.14% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 137 0.16% 58.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 61 0.07% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 169 0.20% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 508 0.59% 59.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 23 0.03% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 260 0.30% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 13 0.02% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 93 0.11% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 141 0.16% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 16 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 46 0.05% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 376 0.44% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 11 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 34 0.04% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 70 0.08% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 29 0.03% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 165 0.19% 61.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 6 0.01% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 16 0.02% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 175 0.20% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.02% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 306 0.36% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 11 0.01% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 15 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 94 0.11% 61.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 22 0.03% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 5 0.01% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 99 0.11% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 8 0.01% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 93 0.11% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 21 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 5 0.01% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 365 0.42% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.01% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 85983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11289.547748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1006.032615 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16787.302098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23431 27.25% 27.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14045 16.33% 43.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2670 3.11% 46.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2200 2.56% 49.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1296 1.51% 50.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1149 1.34% 52.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 926 1.08% 53.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 910 1.06% 54.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 583 0.68% 54.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 573 0.67% 55.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 527 0.61% 56.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 540 0.63% 56.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 283 0.33% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 315 0.37% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 148 0.17% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 512 0.60% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 103 0.12% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 250 0.29% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 57 0.07% 59.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 507 0.59% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 36 0.04% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 193 0.22% 59.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 17 0.02% 59.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 103 0.12% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 71 0.08% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 17 0.02% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 58 0.07% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 468 0.54% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 249 0.29% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 8 0.01% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 28 0.03% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 30 0.03% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 18 0.02% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 6 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 116 0.13% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 10 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 18 0.02% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 420 0.49% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 24 0.03% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 6 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 25 0.03% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 21 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 157 0.18% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 5 0.01% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 20 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 11 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 13 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 363 0.42% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 9 0.01% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 91 0.11% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 13 0.02% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 7 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 5 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 21 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 11 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 161 0.19% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 11 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 9 0.01% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 13 0.02% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 56 0.07% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 5 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 15 0.02% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 79 0.09% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 18 0.02% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 9 0.01% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 348 0.40% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 7 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 23 0.03% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 1 0.00% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 95 0.11% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 17 0.02% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 100 0.12% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 11 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 484 0.56% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 7 0.01% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 86 0.10% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 3 0.00% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 2 0.00% 65.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 27 0.03% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 10 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 1 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 155 0.18% 65.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 378 0.44% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 152 0.18% 66.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 21 0.02% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 2 0.00% 66.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 72 0.08% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 2 0.00% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 466 0.54% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 96 0.11% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 85 0.10% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 17 0.02% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 345 0.40% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10311 1 0.00% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 83 0.10% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 68 0.08% 67.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 1 0.00% 67.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 39 0.05% 67.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 396 0.46% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 2 0.00% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11463 1 0.00% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 156 0.18% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 8 0.01% 68.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 83 0.10% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 2 0.00% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 336 0.39% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 83 0.10% 69.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 2 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 81 0.09% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 70 0.08% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 277 0.32% 69.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 3 0.00% 69.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 151 0.18% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 132 0.15% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 32 0.04% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 2 0.00% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 338 0.39% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 77 0.09% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 2 0.00% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14791 1 0.00% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 81 0.09% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 1 0.00% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 72 0.08% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 269 0.31% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 2 0.00% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 3 0.00% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15815 1 0.00% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 157 0.18% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 3 0.00% 71.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 129 0.15% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 7 0.01% 71.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 2 0.00% 71.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 524 0.61% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 3 0.00% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 130 0.15% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 3 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 155 0.18% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16967 3 0.00% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 86 0.10% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 268 0.31% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 3 0.00% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 70 0.08% 72.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 80 0.09% 73.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 2 0.00% 73.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 82 0.10% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 35 0.04% 73.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 133 0.15% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 2 0.00% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 154 0.18% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 281 0.33% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 67 0.08% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 1 0.00% 74.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 87 0.10% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 327 0.38% 74.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 77 0.09% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 10 0.01% 74.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 2 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 151 0.18% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 39 0.05% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 2 0.00% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 65 0.08% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 2 0.00% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 85 0.10% 75.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 2 0.00% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 4 0.00% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 336 0.39% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 18 0.02% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 3 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 81 0.09% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 2 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23232-23239 2 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 92 0.11% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 463 0.54% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 70 0.08% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 19 0.02% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24199 1 0.00% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 148 0.17% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 5 0.01% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 262 0.30% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 2 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 150 0.17% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 1 0.00% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 2 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 20 0.02% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 73 0.08% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 464 0.54% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 93 0.11% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 84 0.10% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 18 0.02% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 5 0.01% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 339 0.39% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 80 0.09% 79.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 3 0.00% 79.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 63 0.07% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 2 0.00% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 47 0.05% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 2 0.00% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 394 0.46% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 2 0.00% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 150 0.17% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 8 0.01% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 82 0.10% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 329 0.38% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 2 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 3 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 83 0.10% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 2 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 82 0.10% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 72 0.08% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 2 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 276 0.32% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 3 0.00% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 155 0.18% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30023 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 130 0.15% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 35 0.04% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 7 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 2 0.00% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 330 0.38% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 2 0.00% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 79 0.09% 81.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 75 0.09% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 72 0.08% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 264 0.31% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 85 0.10% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 2 0.00% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 158 0.18% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 132 0.15% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32576-32583 2 0.00% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 130 0.15% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 160 0.19% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 2 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 90 0.10% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 4 0.00% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 276 0.32% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 69 0.08% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 76 0.09% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 78 0.09% 84.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34759 1 0.00% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 329 0.38% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 37 0.04% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 132 0.15% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 157 0.18% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 3 0.00% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 272 0.32% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 68 0.08% 85.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 82 0.10% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 85 0.10% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36800-36807 2 0.00% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 328 0.38% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 78 0.09% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 2 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 7 0.01% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 154 0.18% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 389 0.45% 87.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 41 0.05% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 2 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 63 0.07% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 83 0.10% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 332 0.39% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 17 0.02% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 81 0.09% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 95 0.11% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 463 0.54% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 69 0.08% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 4 0.00% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 15 0.02% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 149 0.17% 88.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 257 0.30% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 145 0.17% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 16 0.02% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41536-41543 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 458 0.53% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 90 0.10% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42304-42311 2 0.00% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.10% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 4 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 17 0.02% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 331 0.38% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 81 0.09% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 64 0.07% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 37 0.04% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 395 0.46% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 150 0.17% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 2 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 10 0.01% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 81 0.09% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 82 0.10% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 2 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 2 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 83 0.10% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 69 0.08% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 277 0.32% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 3 0.00% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 151 0.18% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 129 0.15% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46656-46663 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46784-46791 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 36 0.04% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 330 0.38% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 81 0.09% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 82 0.10% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 74 0.09% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 266 0.31% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 154 0.18% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48704-48711 2 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 62 0.07% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 129 0.15% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 4 0.00% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4946 5.74% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 108 0.13% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 18 0.02% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 14 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 161 0.19% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 23 0.03% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 14 0.02% 63.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 4 0.00% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 356 0.41% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 11 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 163 0.19% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 2 0.00% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 16 0.02% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 2 0.00% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 50 0.06% 63.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 13 0.02% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 4 0.00% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 197 0.23% 64.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 9 0.01% 64.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 7 0.01% 64.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 223 0.26% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 13 0.02% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 5 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 140 0.16% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 88 0.10% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 2 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 158 0.18% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 14 0.02% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 1 0.00% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 345 0.40% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 5 0.01% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 8 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 13 0.02% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 18 0.02% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 6 0.01% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 141 0.16% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 6 0.01% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 41 0.05% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 2 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 10 0.01% 65.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 399 0.46% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 36 0.04% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8583 2 0.00% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 130 0.15% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 2 0.00% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 5 0.01% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 341 0.40% 66.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 3 0.00% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 145 0.17% 66.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 78 0.09% 67.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 3 0.00% 67.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 2 0.00% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 212 0.25% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 2 0.00% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 150 0.17% 67.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 41 0.05% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10887 1 0.00% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 2 0.00% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 153 0.18% 67.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 349 0.41% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 8 0.01% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 3 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 141 0.16% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 3 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 94 0.11% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 2 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 334 0.39% 68.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 13 0.02% 68.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 3 0.00% 68.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 141 0.16% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 6 0.01% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 399 0.46% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 1 0.00% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 94 0.11% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13767 2 0.00% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 2 0.00% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 3 0.00% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14023 1 0.00% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 214 0.25% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 2 0.00% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 4 0.00% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 420 0.49% 70.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 5 0.01% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 1 0.00% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 22 0.03% 70.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 141 0.16% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 335 0.39% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 80 0.09% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 2 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15943 2 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 2 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 143 0.17% 71.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 6 0.01% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 673 0.78% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 144 0.17% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 7 0.01% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16967 2 0.00% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 81 0.09% 72.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 2 0.00% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 336 0.39% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 135 0.16% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 4 0.00% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 25 0.03% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 1 0.00% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 1 0.00% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 6 0.01% 72.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 2 0.00% 72.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 419 0.49% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 2 0.00% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 214 0.25% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18759 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 4 0.00% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 97 0.11% 73.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 391 0.45% 74.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 10 0.01% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 3 0.00% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 139 0.16% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 13 0.02% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 331 0.38% 74.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 94 0.11% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20800-20807 1 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 1 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20935 2 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 142 0.17% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 2 0.00% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 13 0.02% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 343 0.40% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 3 0.00% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 150 0.17% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 38 0.04% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22080-22087 1 0.00% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 3 0.00% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 148 0.17% 76.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 2 0.00% 76.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 76.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 208 0.24% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 129 0.15% 76.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 76 0.09% 76.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 2 0.00% 76.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 148 0.17% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 1 0.00% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 338 0.39% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 10 0.01% 77.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 2 0.00% 77.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 128 0.15% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 2 0.00% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 34 0.04% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 281 0.33% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24647 2 0.00% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 36 0.04% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 132 0.15% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 9 0.01% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25536-25543 1 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 331 0.38% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 146 0.17% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 78 0.09% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 2 0.00% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 128 0.15% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 6 0.01% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 207 0.24% 78.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 78.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 3 0.00% 78.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 78.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 146 0.17% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 3 0.00% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 1 0.00% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 38 0.04% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 151 0.18% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 337 0.39% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 1 0.00% 79.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 2 0.00% 79.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 13 0.02% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 1 0.00% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 141 0.16% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 1 0.00% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 97 0.11% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 5 0.01% 79.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 4 0.00% 79.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 328 0.38% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 12 0.01% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 2 0.00% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 141 0.16% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 7 0.01% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 3 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 399 0.46% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 90 0.10% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 2 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 5 0.01% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30407 1 0.00% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 214 0.25% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 1 0.00% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 3 0.00% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 415 0.48% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 5 0.01% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 3 0.00% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 21 0.02% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 2 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 1 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 138 0.16% 82.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 338 0.39% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 2 0.00% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 78 0.09% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 9 0.01% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 145 0.17% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 671 0.78% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32960-32967 1 0.00% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 141 0.16% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 7 0.01% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 85 0.10% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 348 0.40% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 136 0.16% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 21 0.02% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34496-34503 2 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 8 0.01% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 2 0.00% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 412 0.48% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 212 0.25% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 5 0.01% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 91 0.11% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 392 0.46% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35904-35911 1 0.00% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 2 0.00% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 8 0.01% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 140 0.16% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 4 0.00% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36544-36551 1 0.00% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 12 0.01% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 327 0.38% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36928-36935 1 0.00% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 90 0.10% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 141 0.16% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 10 0.01% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 1 0.00% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37760-37767 1 0.00% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 334 0.39% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 149 0.17% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 37 0.04% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 150 0.17% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 205 0.24% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 127 0.15% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 76 0.09% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 146 0.17% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 330 0.38% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 132 0.15% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 37 0.04% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40896-40903 1 0.00% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 277 0.32% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41088-41095 1 0.00% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 34 0.04% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 128 0.15% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 10 0.01% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 332 0.39% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 142 0.17% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 76 0.09% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 131 0.15% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 208 0.24% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 145 0.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 1 0.00% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 36 0.04% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 152 0.18% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 340 0.40% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 8 0.01% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 144 0.17% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 94 0.11% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 3 0.00% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 12 0.01% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 1 0.00% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 141 0.16% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 11 0.01% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 393 0.46% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 91 0.11% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 4 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 211 0.25% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 2 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 416 0.48% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 4 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 2 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 32 0.04% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 141 0.16% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 335 0.39% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 74 0.09% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 4 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 140 0.16% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 4 0.00% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5017 5.83% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 4 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 3 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52288-52295 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86110 # Bytes accessed per row activation -system.physmem.totQLat 365142496500 # Total ticks spent queuing -system.physmem.totMemAccLat 457904364000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75291530000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17470337500 # Total ticks spent accessing banks -system.physmem.avgQLat 24248.58 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1160.18 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 85983 # Bytes accessed per row activation +system.physmem.totQLat 365185132750 # Total ticks spent queuing +system.physmem.totMemAccLat 457949856500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75297645000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17467078750 # Total ticks spent accessing banks +system.physmem.avgQLat 24249.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1159.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30408.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30409.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -752,14 +749,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.37 # Average write queue length when enqueuing -system.physmem.readRowHits 14986658 # Number of row buffer hits during reads -system.physmem.writeRowHits 93339 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.57 # Row buffer hit rate for writes -system.physmem.avgGap 158777.68 # Average gap between requests +system.physmem.avgWrQLen 14.56 # Average write queue length when enqueuing +system.physmem.readRowHits 14988012 # Number of row buffer hits during reads +system.physmem.writeRowHits 93348 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.58 # Row buffer hit rate for writes +system.physmem.avgGap 158776.13 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.54 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.53 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -772,50 +769,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54877277 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149448 # Transaction distribution -system.membus.trans_dist::ReadResp 16149448 # Transaction distribution -system.membus.trans_dist::WriteReq 763332 # Transaction distribution -system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution -system.membus.trans_dist::ReadExReq 131427 # Transaction distribution -system.membus.trans_dist::ReadExResp 131427 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) +system.membus.throughput 54878485 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149469 # Transaction distribution +system.membus.trans_dist::ReadResp 16149469 # Transaction distribution +system.membus.trans_dist::WriteReq 763349 # Transaction distribution +system.membus.trans_dist::WriteResp 763349 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4690 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4693 # Transaction distribution +system.membus.trans_dist::ReadExReq 131452 # Transaction distribution +system.membus.trans_dist::ReadExResp 131452 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272628 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34157044 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694304 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092346 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138628065 # Total data (bytes) +system.membus.tot_pkt_size::total 138630010 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630010 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486866000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17361359500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4731205438 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737720957 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -823,12 +820,12 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266379 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution -system.iobus.trans_dist::WriteReq 8157 # Transaction distribution -system.iobus.trans_dist::WriteResp 8157 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48266825 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution +system.iobus.trans_dist::WriteReq 8174 # Transaction distribution +system.iobus.trans_dist::WriteResp 8174 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) @@ -851,11 +848,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) @@ -878,12 +875,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927965 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121928118 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -931,20 +928,20 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40922322043 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14756776 # Number of BP lookups -system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits +system.cpu.branchPred.lookups 14743416 # Number of BP lookups +system.cpu.branchPred.condPredicted 11827380 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704687 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9504018 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7655579 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.550973 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397368 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72480 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -968,9 +965,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986903 # DTB read hits +system.cpu.checker.dtb.read_hits 14987484 # DTB read hits system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227441 # DTB write hits +system.cpu.checker.dtb.write_hits 11227618 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -981,12 +978,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994210 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229632 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994791 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229809 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214344 # DTB hits +system.cpu.checker.dtb.hits 26215102 # DTB hits system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26223842 # DTB accesses +system.cpu.checker.dtb.accesses 26224600 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1008,7 +1005,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61480126 # ITB inst hits +system.cpu.checker.itb.inst_hits 61483125 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -1025,11 +1022,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484599 # ITB inst accesses -system.cpu.checker.itb.hits 61480126 # DTB hits +system.cpu.checker.itb.inst_accesses 61487598 # ITB inst accesses +system.cpu.checker.itb.hits 61483125 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61484599 # DTB accesses -system.cpu.checker.numCycles 77883033 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61487598 # DTB accesses +system.cpu.checker.numCycles 77886440 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -1055,25 +1052,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51181584 # DTB read hits -system.cpu.dtb.read_misses 65031 # DTB read misses -system.cpu.dtb.write_hits 11699885 # DTB write hits -system.cpu.dtb.write_misses 15694 # DTB write misses +system.cpu.dtb.read_hits 51180405 # DTB read hits +system.cpu.dtb.read_misses 65067 # DTB read misses +system.cpu.dtb.write_hits 11700451 # DTB write hits +system.cpu.dtb.write_misses 15748 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2401 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51246615 # DTB read accesses -system.cpu.dtb.write_accesses 11715579 # DTB write accesses +system.cpu.dtb.perms_faults 1377 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51245472 # DTB read accesses +system.cpu.dtb.write_accesses 11716199 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62881469 # DTB hits -system.cpu.dtb.misses 80725 # DTB misses -system.cpu.dtb.accesses 62962194 # DTB accesses +system.cpu.dtb.hits 62880856 # DTB hits +system.cpu.dtb.misses 80815 # DTB misses +system.cpu.dtb.accesses 62961671 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1095,8 +1092,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11524718 # ITB inst hits -system.cpu.itb.inst_misses 11477 # ITB inst misses +system.cpu.itb.inst_hits 11521970 # ITB inst hits +system.cpu.itb.inst_misses 11115 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1105,114 +1102,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2502 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2960 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11536195 # ITB inst accesses -system.cpu.itb.hits 11524718 # DTB hits -system.cpu.itb.misses 11477 # DTB misses -system.cpu.itb.accesses 11536195 # DTB accesses -system.cpu.numCycles 477111575 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533085 # ITB inst accesses +system.cpu.itb.hits 11521970 # DTB hits +system.cpu.itb.misses 11115 # DTB misses +system.cpu.itb.accesses 11533085 # DTB accesses +system.cpu.numCycles 477047952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29756603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90277136 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14743416 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9052947 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20141800 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4650225 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121200 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98195863 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2631 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87675 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2688966 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11518528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5147 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154198551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081572 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134072201 86.95% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1305405 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710070 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2294026 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2104673 1.36% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1102818 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555300 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746086 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307972 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154198551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030906 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189241 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31769851 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100064901 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18067338 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1262749 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3033712 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957542 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172175 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107250920 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3033712 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33504513 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38619180 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55176666 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17578446 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6286034 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102244327 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 450 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 980082 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063460 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 782 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106315700 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473686161 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432563323 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10440 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727135 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27588564 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170552 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1076872 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12591466 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19711121 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13300191 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1936389 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2436828 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95079446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983827 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122895781 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165904 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18895197 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47144933 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501515 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154198551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515893 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109876529 71.26% 71.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14361592 9.31% 80.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6875815 4.46% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5666847 3.68% 88.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12323021 7.99% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2802995 1.82% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1694666 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 469725 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127361 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154198551 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61834 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1240,436 +1237,437 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8368136 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413820 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57946622 47.15% 47.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52506141 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318913 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued -system.cpu.iq.rate 0.257621 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122895781 # Type of FU issued +system.cpu.iq.rate 0.257617 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8843793 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071962 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409057037 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 115975062 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85458771 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23247 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12478 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10297 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131698673 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12383 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624051 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4056444 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6518 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30236 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1568197 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34108054 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680529 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3033712 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30168583 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433803 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97285878 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203457 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19711121 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13300191 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411588 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3352 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30236 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349021 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270487 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619508 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120819447 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51867420 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2076334 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221300 # number of nop insts executed -system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed -system.cpu.iew.exec_branches 11821026 # Number of branches executed -system.cpu.iew.exec_stores 12211427 # Number of stores executed -system.cpu.iew.exec_rate 0.253266 # Inst execution rate -system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47016858 # num instructions producing a value -system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value +system.cpu.iew.exec_nop 222605 # number of nop insts executed +system.cpu.iew.exec_refs 64079545 # number of memory reference insts executed +system.cpu.iew.exec_branches 11817660 # Number of branches executed +system.cpu.iew.exec_stores 12212125 # Number of stores executed +system.cpu.iew.exec_rate 0.253265 # Inst execution rate +system.cpu.iew.wb_sent 119878750 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85469068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47006672 # num instructions producing a value +system.cpu.iew.wb_consumers 87538881 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179162 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536980 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18642428 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482312 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534972 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151164839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.491788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122735782 81.19% 81.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14630083 9.68% 90.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3890528 2.57% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132680 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1607271 1.06% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 973341 0.64% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1599818 1.06% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 715537 0.47% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2879799 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456535 # Number of instructions committed -system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151164839 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459531 # Number of instructions committed +system.cpu.commit.committedOps 77751027 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385855 # Number of memory references committed -system.cpu.commit.loads 15654083 # Number of loads committed -system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 10305769 # Number of branches committed +system.cpu.commit.refs 27386671 # Number of memory references committed +system.cpu.commit.loads 15654677 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 10306328 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69188185 # Number of committed integer instructions. -system.cpu.commit.function_calls 991209 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69191102 # Number of committed integer instructions. +system.cpu.commit.function_calls 991248 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2879799 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242914035 # The number of ROB reads -system.cpu.rob.rob_writes 195975439 # The number of ROB writes -system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60306154 # Number of Instructions Simulated -system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated -system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548607877 # number of integer regfile reads -system.cpu.int_regfile_writes 87541392 # number of integer regfile writes -system.cpu.fp_regfile_reads 8324 # number of floating regfile reads -system.cpu.fp_regfile_writes 2920 # number of floating regfile writes -system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.rob.rob_reads 242830080 # The number of ROB reads +system.cpu.rob.rob_writes 195907164 # The number of ROB writes +system.cpu.timesIdled 1776346 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322849401 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575122538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309150 # Number of Instructions Simulated +system.cpu.committedOps 77600646 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309150 # Number of Instructions Simulated +system.cpu.cpi 7.910043 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.910043 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548535748 # number of integer regfile reads +system.cpu.int_regfile_writes 87515633 # number of integer regfile writes +system.cpu.fp_regfile_reads 8349 # number of floating regfile reads +system.cpu.fp_regfile_writes 2926 # number of floating regfile writes +system.cpu.misc_regfile_reads 268179441 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173225 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58877700 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2957 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795840 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30059 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62784704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85494778 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 211580 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148531598 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148531598 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 200936 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128807668 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1475592252 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550083892 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19930988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74876053 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980909 # number of replacements -system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 981505 # number of replacements +system.cpu.icache.tags.tagsinuse 511.575357 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10456797 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 982017 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.648285 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6907075250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.575357 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999171 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999171 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits -system.cpu.icache.overall_hits::total 10459956 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses -system.cpu.icache.overall_misses::total 1061258 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11521214 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11521214 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11521214 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092113 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092113 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092113 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13453.040297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13453.040297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13453.040297 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 745356250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8857279773 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9606047773 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6336999 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935139250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941476249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17447345437 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17447345437 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942244250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948581249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17449661616 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17449661616 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6336999 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184382484687 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184388821686 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60372.286571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61567.461912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61477.131933 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1790,168 +1788,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101513406 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101513406 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13755166 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13755166 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258873 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258873 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242710 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242710 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21014039 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21014039 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21014039 # number of overall hits -system.cpu.dcache.overall_hits::total 21014039 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # 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number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16294938912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16294938912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16294938912 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16294938912 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335926750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335926750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26847444003 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26847444003 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209183370753 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209183370753 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024356 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047558 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047558 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025675 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025675 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025675 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025675 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12894.305424 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12894.305424 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45482.364765 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45482.364765 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11918.136692 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11918.136692 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25681.785662 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25681.785662 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1975,16 +1973,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499139103043 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499139103043 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 2d523b33d..d9a1ddbd2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605645 # Number of seconds simulated -sim_ticks 2605645191500 # Number of ticks simulated -final_tick 2605645191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605623 # Number of seconds simulated +sim_ticks 2605623216500 # Number of ticks simulated +final_tick 2605623216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69894 # Simulator instruction rate (inst/s) -host_op_rate 90000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2899968268 # Simulator tick rate (ticks/s) -host_mem_usage 430484 # Number of bytes of host memory used -host_seconds 898.51 # Real time elapsed on the host -sim_insts 62800764 # Number of instructions simulated -sim_ops 80866121 # Number of ops (including micro ops) simulated +host_inst_rate 60428 # Simulator instruction rate (inst/s) +host_op_rate 77810 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2507107577 # Simulator tick rate (ticks/s) +host_mem_usage 430512 # Number of bytes of host memory used +host_seconds 1039.29 # Real time elapsed on the host +sim_insts 62801984 # Number of instructions simulated +sim_ops 80867321 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 392704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4367548 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 428032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5265336 # Number of bytes read from this memory -system.physmem.bytes_read::total 131566132 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 392704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 428032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 820736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282176 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4350396 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 426880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5253880 # Number of bytes read from this memory +system.physmem.bytes_read::total 131538740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4261184 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7311312 # Number of bytes written to this memory +system.physmem.bytes_written::total 7290320 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6136 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6688 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82299 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302287 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66909 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301859 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66581 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824193 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46480054 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823865 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46480446 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 150713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2020742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50492727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 150713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314984 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1643423 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1669618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2016362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50482640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163830 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1635380 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2805951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1643423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46480054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156014 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2797918 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1635380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46480446 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 150713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1682711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3176746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53298678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302287 # Number of read requests accepted -system.physmem.writeReqs 824193 # Number of write requests accepted -system.physmem.readBursts 15302287 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 824193 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976879168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2467200 # Total number of bytes read from write queue -system.physmem.bytesWritten 7418176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131566132 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7311312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38550 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 708272 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956326 # Per bank write bursts -system.physmem.perBankRdBursts::1 956081 # Per bank write bursts -system.physmem.perBankRdBursts::2 952133 # Per bank write bursts -system.physmem.perBankRdBursts::3 952389 # Per bank write bursts -system.physmem.perBankRdBursts::4 956868 # Per bank write bursts -system.physmem.perBankRdBursts::5 956262 # Per bank write bursts -system.physmem.perBankRdBursts::6 951633 # Per bank write bursts -system.physmem.perBankRdBursts::7 951532 # Per bank write bursts -system.physmem.perBankRdBursts::8 956738 # Per bank write bursts -system.physmem.perBankRdBursts::9 956585 # Per bank write bursts -system.physmem.perBankRdBursts::10 951315 # Per bank write bursts -system.physmem.perBankRdBursts::11 950633 # Per bank write bursts -system.physmem.perBankRdBursts::12 956323 # Per bank write bursts -system.physmem.perBankRdBursts::13 956319 # Per bank write bursts -system.physmem.perBankRdBursts::14 951484 # Per bank write bursts -system.physmem.perBankRdBursts::15 951116 # Per bank write bursts -system.physmem.perBankWrBursts::0 7149 # Per bank write bursts -system.physmem.perBankWrBursts::1 7007 # Per bank write bursts -system.physmem.perBankWrBursts::2 7292 # Per bank write bursts -system.physmem.perBankWrBursts::3 7274 # Per bank write bursts -system.physmem.perBankWrBursts::4 7928 # Per bank write bursts -system.physmem.perBankWrBursts::5 7489 # Per bank write bursts -system.physmem.perBankWrBursts::6 7090 # Per bank write bursts -system.physmem.perBankWrBursts::7 7095 # Per bank write bursts -system.physmem.perBankWrBursts::8 7536 # Per bank write bursts -system.physmem.perBankWrBursts::9 7648 # Per bank write bursts -system.physmem.perBankWrBursts::10 6979 # Per bank write bursts -system.physmem.perBankWrBursts::11 6633 # Per bank write bursts -system.physmem.perBankWrBursts::12 7251 # Per bank write bursts -system.physmem.perBankWrBursts::13 7189 # Per bank write bursts -system.physmem.perBankWrBursts::14 7290 # Per bank write bursts -system.physmem.perBankWrBursts::15 7059 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 151598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1676143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3172376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53280558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15301859 # Number of read requests accepted +system.physmem.writeReqs 823865 # Number of write requests accepted +system.physmem.readBursts 15301859 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823865 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976840512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2478464 # Total number of bytes read from write queue +system.physmem.bytesWritten 7393984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131538740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7290320 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38726 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 708315 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14211 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956322 # Per bank write bursts +system.physmem.perBankRdBursts::1 955904 # Per bank write bursts +system.physmem.perBankRdBursts::2 952374 # Per bank write bursts +system.physmem.perBankRdBursts::3 952254 # Per bank write bursts +system.physmem.perBankRdBursts::4 956762 # Per bank write bursts +system.physmem.perBankRdBursts::5 955994 # Per bank write bursts +system.physmem.perBankRdBursts::6 951679 # Per bank write bursts +system.physmem.perBankRdBursts::7 951390 # Per bank write bursts +system.physmem.perBankRdBursts::8 956653 # Per bank write bursts +system.physmem.perBankRdBursts::9 956558 # Per bank write bursts +system.physmem.perBankRdBursts::10 951325 # Per bank write bursts +system.physmem.perBankRdBursts::11 950816 # Per bank write bursts +system.physmem.perBankRdBursts::12 956256 # Per bank write bursts +system.physmem.perBankRdBursts::13 956091 # Per bank write bursts +system.physmem.perBankRdBursts::14 951432 # Per bank write bursts +system.physmem.perBankRdBursts::15 951323 # Per bank write bursts +system.physmem.perBankWrBursts::0 7131 # Per bank write bursts +system.physmem.perBankWrBursts::1 6969 # Per bank write bursts +system.physmem.perBankWrBursts::2 7487 # Per bank write bursts +system.physmem.perBankWrBursts::3 7380 # Per bank write bursts +system.physmem.perBankWrBursts::4 7843 # Per bank write bursts +system.physmem.perBankWrBursts::5 7402 # Per bank write bursts +system.physmem.perBankWrBursts::6 7084 # Per bank write bursts +system.physmem.perBankWrBursts::7 7084 # Per bank write bursts +system.physmem.perBankWrBursts::8 7461 # Per bank write bursts +system.physmem.perBankWrBursts::9 7519 # Per bank write bursts +system.physmem.perBankWrBursts::10 6987 # Per bank write bursts +system.physmem.perBankWrBursts::11 6657 # Per bank write bursts +system.physmem.perBankWrBursts::12 7185 # Per bank write bursts +system.physmem.perBankWrBursts::13 7089 # Per bank write bursts +system.physmem.perBankWrBursts::14 7212 # Per bank write bursts +system.physmem.perBankWrBursts::15 7041 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605643958000 # Total gap between requests +system.physmem.totGap 2605622062000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 109 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 163362 # Read request sizes (log2) +system.physmem.readPktSize::6 162934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66909 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1182621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1128295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1080999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3674790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2650191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2638240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2645126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 56320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 21310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 21179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66581 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1184108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1129171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1082709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3674312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2649053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2636381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2643445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 56452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 21240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 21122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -161,620 +161,609 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 10742.195593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 915.011801 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16529.689653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25868 28.23% 28.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14885 16.24% 44.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3175 3.47% 47.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2307 2.52% 50.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1552 1.69% 52.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1265 1.38% 53.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 967 1.06% 54.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1319 1.44% 56.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 664 0.72% 56.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 632 0.69% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 552 0.60% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 612 0.67% 58.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 295 0.32% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 299 0.33% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 170 0.19% 59.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 591 0.64% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 145 0.16% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 120 0.13% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 94 0.10% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 139 0.15% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 69 0.08% 60.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 555 0.61% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 36 0.04% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 297 0.32% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 26 0.03% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 93 0.10% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 171 0.19% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 18 0.02% 62.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 53 0.06% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 22 0.02% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 386 0.42% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 91489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 10757.948868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 916.821036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16539.903542 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25786 28.18% 28.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14910 16.30% 44.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3164 3.46% 47.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2339 2.56% 50.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1506 1.65% 52.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1246 1.36% 53.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1021 1.12% 54.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1185 1.30% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 667 0.73% 56.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 658 0.72% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 602 0.66% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 572 0.63% 58.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 315 0.34% 58.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 283 0.31% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 170 0.19% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 580 0.63% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 115 0.13% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 145 0.16% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 84 0.09% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 210 0.23% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 59 0.06% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 551 0.60% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 52 0.06% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 273 0.30% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 29 0.03% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 104 0.11% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 17 0.02% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 169 0.18% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 21 0.02% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 56 0.06% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 21 0.02% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 399 0.44% 62.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2119 9 0.01% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 41 0.04% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 10 0.01% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 62 0.07% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 6 0.01% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 32 0.03% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 10 0.01% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 171 0.19% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 4 0.00% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 16 0.02% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 7 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 87 0.09% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 9 0.01% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 8 0.01% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 355 0.39% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 3 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 6 0.01% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 101 0.11% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 10 0.01% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 14 0.02% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 93 0.10% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 11 0.01% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 22 0.02% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 63.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 109 0.12% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 11 0.01% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 64.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 384 0.42% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 10 0.01% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 16 0.02% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 6 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 99 0.11% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 15 0.02% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 11 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 45 0.05% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 4 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 10 0.01% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 11 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 152 0.17% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 9 0.01% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 16 0.02% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 3 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 484 0.53% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 12 0.01% 65.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 12 0.01% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 6 0.01% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 6 0.01% 65.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 65.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 100 0.11% 65.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 6 0.01% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 10 0.01% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 6 0.01% 65.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 142 0.15% 65.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 4 0.00% 65.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 15 0.02% 65.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 4 0.00% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 300 0.33% 66.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 4 0.00% 66.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 14 0.02% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 89 0.10% 66.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 2 0.00% 66.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 160 0.17% 66.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 7 0.01% 66.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 20 0.02% 66.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 31 0.03% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 3 0.00% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 11 0.01% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 463 0.51% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 5 0.01% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 6 0.01% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 163 0.18% 67.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 4 0.00% 67.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 11 0.01% 67.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 5 0.01% 67.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 15 0.02% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 1 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 91 0.10% 67.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 6 0.01% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 9 0.01% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 397 0.43% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 85 0.09% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8519 1 0.00% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8583 2 0.00% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 6 0.01% 67.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8775 1 0.00% 67.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 2 0.00% 67.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 154 0.17% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 3 0.00% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 460 0.50% 68.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 24 0.03% 68.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 68.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 5 0.01% 68.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 143 0.16% 68.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 68.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 68.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 68.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 82 0.09% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 1 0.00% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 282 0.31% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10311 1 0.00% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 93 0.10% 69.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 2 0.00% 69.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 69.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 2 0.00% 69.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 93 0.10% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 1 0.00% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 7 0.01% 69.41% # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 1 0.00% 70.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 70.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 353 0.39% 70.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 70.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 70.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 89 0.10% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 73 0.08% 70.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 2 0.00% 70.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 85 0.09% 70.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 70.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 4 0.00% 70.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 70.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 331 0.36% 71.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 70 0.08% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 2 0.00% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 145 0.16% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 2 0.00% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 17 0.02% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 2 0.00% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 336 0.37% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 4 0.00% 71.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 80 0.09% 71.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 71.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 83 0.09% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 18 0.02% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 2 0.00% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 1 0.00% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 400 0.44% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 72.51% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 30 0.03% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 317 0.35% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 3 0.00% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 20 0.02% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 11 0.01% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 167 0.18% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 13 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 17 0.02% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 159 0.17% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 8 0.01% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 11 0.01% 63.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 119 0.13% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 21 0.02% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 498 0.54% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 8 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.01% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 9 0.01% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 21 0.02% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 17 0.02% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 15 0.02% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 10 0.01% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 32 0.03% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 10 0.01% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 144 0.16% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 10 0.01% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 10 0.01% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 298 0.33% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 8 0.01% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 12 0.01% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 6 0.01% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 14 0.02% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 7 0.01% 65.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 8 0.01% 65.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 5 0.01% 65.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 74 0.08% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 15 0.02% 65.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 4 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 253 0.28% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 4 0.00% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 13 0.01% 65.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 13 0.01% 65.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 396 0.43% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 4 0.00% 66.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 10 0.01% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 4 0.00% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 85 0.09% 66.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 5 0.01% 66.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 103 0.11% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 8 0.01% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 22 0.02% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 2 0.00% 66.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 29 0.03% 66.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 4 0.00% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 7 0.01% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 3 0.00% 66.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 296 0.32% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 7 0.01% 66.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 10 0.01% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 167 0.18% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 11 0.01% 67.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 5 0.01% 67.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 20 0.02% 67.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 67.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 5 0.01% 67.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 73 0.08% 67.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 3 0.00% 67.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 9 0.01% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 634 0.69% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 75 0.08% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8583 2 0.00% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 13 0.01% 68.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 68.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 157 0.17% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 1 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 2 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9159 1 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 285 0.31% 68.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 15 0.02% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 1 0.00% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 93 0.10% 68.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 68.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 68.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 77 0.08% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 4 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 396 0.43% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 2 0.00% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 200 0.22% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 1 0.00% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 71 0.08% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 1 0.00% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10887 1 0.00% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 1 0.00% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 10 0.01% 69.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 69.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 289 0.32% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 1 0.00% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 139 0.15% 69.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 69.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 14 0.02% 69.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 10 0.01% 69.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 5 0.01% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 2 0.00% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 463 0.51% 70.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 93 0.10% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12615 1 0.00% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 146 0.16% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 1 0.00% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 146 0.16% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 294 0.32% 71.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 17 0.02% 71.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13639 1 0.00% 71.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 71.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 141 0.15% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 14 0.02% 71.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 71.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 345 0.38% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 2 0.00% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 78 0.09% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 2 0.00% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 78 0.09% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 3 0.00% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 81 0.09% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 2 0.00% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 392 0.43% 72.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 92 0.10% 72.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::15808-15815 1 0.00% 72.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 147 0.16% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15943 1 0.00% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 3 0.00% 72.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 74 0.08% 72.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 4 0.00% 72.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 514 0.56% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 1 0.00% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 75 0.08% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 1 0.00% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 140 0.15% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 75 0.08% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 3 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 397 0.43% 74.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 74.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 74.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 22 0.02% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 2 0.00% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 82 0.09% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 3 0.00% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 2 0.00% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 77 0.08% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 4 0.00% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 337 0.37% 74.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 74.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 20 0.02% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18823 2 0.00% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 146 0.16% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19143 1 0.00% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 69 0.08% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 4 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 2 0.00% 75.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 330 0.36% 75.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 75.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 82 0.09% 75.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 77 0.08% 75.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 1 0.00% 75.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 92 0.10% 75.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 2 0.00% 75.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 75.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 348 0.38% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20551 1 0.00% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 3 0.00% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 78 0.09% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 26 0.03% 76.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 76.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 1 0.00% 76.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 140 0.15% 76.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 3 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 2 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 469 0.51% 76.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 6 0.01% 76.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 94 0.10% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22215 4 0.00% 76.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 92 0.10% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 3 0.00% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 276 0.30% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 77 0.08% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 2 0.00% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 1 0.00% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 140 0.15% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23232-23239 1 0.00% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 28 0.03% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 2 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 459 0.50% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 3 0.00% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 146 0.16% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23872-23879 1 0.00% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 7 0.01% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24135 1 0.00% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24199 1 0.00% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 88 0.10% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 78.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 5 0.01% 78.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 2 0.00% 78.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 281 0.31% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24647 1 0.00% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 86 0.09% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 6 0.01% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 153 0.17% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 4 0.00% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 454 0.50% 79.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 79.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 26 0.03% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 1 0.00% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 144 0.16% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 3 0.00% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 79 0.09% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 2 0.00% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 5 0.01% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 276 0.30% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 2 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 94 0.10% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 2 0.00% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 1 0.00% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 92 0.10% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 9 0.01% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 4 0.00% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 472 0.52% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 2 0.00% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 2 0.00% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 140 0.15% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 21 0.02% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 2 0.00% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 2 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 78 0.09% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 2 0.00% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 4 0.00% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 344 0.38% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 2 0.00% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 87 0.09% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 75 0.08% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 2 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 81 0.09% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 2 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 2 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 325 0.35% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29760-29767 3 0.00% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 2 0.00% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 72 0.08% 82.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30023 2 0.00% 82.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 3 0.00% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 142 0.15% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 20 0.02% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 1 0.00% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 3 0.00% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 331 0.36% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 1 0.00% 82.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 75 0.08% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 2 0.00% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 4 0.00% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 2 0.00% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 80 0.09% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 2 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 17 0.02% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 2 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 3 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 402 0.44% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 74 0.08% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 2 0.00% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 141 0.15% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 73 0.08% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 516 0.56% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 3 0.00% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 69 0.08% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33095 1 0.00% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 142 0.15% 84.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 2 0.00% 84.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 81 0.09% 84.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 2 0.00% 84.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 419 0.46% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 2 0.00% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 17 0.02% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34183 1 0.00% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 80 0.09% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34496-34503 1 0.00% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 75 0.08% 85.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 329 0.36% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 20 0.02% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 143 0.16% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 69 0.08% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35776-35783 1 0.00% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 324 0.35% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 79 0.09% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36160-36167 2 0.00% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 2 0.00% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 71 0.08% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 2 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 87 0.09% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 344 0.38% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 77 0.08% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 23 0.03% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 141 0.15% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37760-37767 1 0.00% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 468 0.51% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 6 0.01% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 91 0.10% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 6 0.01% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 98 0.11% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38784-38791 2 0.00% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 273 0.30% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 79 0.09% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 143 0.16% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 3 0.00% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 23 0.03% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39744-39751 1 0.00% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 454 0.50% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 151 0.16% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 4 0.00% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 4 0.00% 89.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 86 0.09% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 275 0.30% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41024-41031 2 0.00% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41088-41095 1 0.00% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 85 0.09% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 4 0.00% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 148 0.16% 89.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 453 0.49% 90.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 3 0.00% 90.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42176-42183 1 0.00% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 24 0.03% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42304-42311 1 0.00% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 142 0.15% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42560-42567 1 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 2 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 76 0.08% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 275 0.30% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 88 0.10% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 89 0.10% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 3 0.00% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 6 0.01% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 1 0.00% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43968-43975 2 0.00% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 468 0.51% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 137 0.15% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 25 0.03% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 78 0.09% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44992-44999 2 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 347 0.38% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 91 0.10% 92.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45504-45511 1 0.00% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 81 0.09% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 3 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 13 0.01% 72.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15943 1 0.00% 72.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 1 0.00% 72.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.08% 72.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 1 0.00% 72.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 10 0.01% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 676 0.74% 73.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 76 0.08% 73.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 13 0.01% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16967 2 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 98 0.11% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17223 1 0.00% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 2 0.00% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 394 0.43% 74.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 4 0.00% 74.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 1 0.00% 74.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17600-17607 2 0.00% 74.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 80 0.09% 74.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 74.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 1 0.00% 74.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 74.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 77 0.08% 74.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 1 0.00% 74.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 83 0.09% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 3 0.00% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 341 0.37% 74.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 14 0.02% 74.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 2 0.00% 74.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 141 0.15% 74.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 23 0.03% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 287 0.31% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 3 0.00% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 3 0.00% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 144 0.16% 75.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19776-19783 2 0.00% 75.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 144 0.16% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 1 0.00% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 97 0.11% 75.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 75.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 75.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 470 0.51% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20551 1 0.00% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 10 0.01% 76.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 16 0.02% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21056-21063 1 0.00% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 142 0.16% 76.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 76.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 3 0.00% 76.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 283 0.31% 76.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 9 0.01% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 72 0.08% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 2 0.00% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 194 0.21% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 387 0.42% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 2 0.00% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 79 0.09% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 89 0.10% 77.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 77.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 2 0.00% 77.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.02% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 1 0.00% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 286 0.31% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 2 0.00% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 151 0.17% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 13 0.01% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 2 0.00% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 73 0.08% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 6 0.01% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 527 0.58% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 73 0.08% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 14 0.02% 78.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 78.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 1 0.00% 78.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 156 0.17% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25408-25415 2 0.00% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 3 0.00% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 278 0.30% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25671 2 0.00% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 13 0.01% 79.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 79.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 79.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 89 0.10% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 4 0.00% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 78 0.09% 79.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 4 0.00% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 385 0.42% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 1 0.00% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 2 0.00% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 196 0.21% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 1 0.00% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27072-27079 2 0.00% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 71 0.08% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 10 0.01% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 2 0.00% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 2 0.00% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 285 0.31% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 2 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 137 0.15% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 20 0.02% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 15 0.02% 80.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 454 0.50% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 95 0.10% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 2 0.00% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 2 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 143 0.16% 81.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 3 0.00% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 2 0.00% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 147 0.16% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 5 0.01% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 291 0.32% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29760-29767 1 0.00% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 18 0.02% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 1 0.00% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 139 0.15% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 2 0.00% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 17 0.02% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 2 0.00% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 5 0.01% 82.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 334 0.37% 82.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 2 0.00% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 75 0.08% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 2 0.00% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 1 0.00% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 77 0.08% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 2 0.00% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 84 0.09% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 6 0.01% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 392 0.43% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 91 0.10% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 2 0.00% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 14 0.02% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 81 0.09% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 2 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 668 0.73% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 70 0.08% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 13 0.01% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 3 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 95 0.10% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 3 0.00% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 402 0.44% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 82 0.09% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 76 0.08% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 4 0.00% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 80 0.09% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34759 1 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 334 0.37% 85.60% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 2 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39872-39879 1 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 277 0.30% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 154 0.17% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 11 0.01% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 77 0.08% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 525 0.57% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41088-41095 1 0.00% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 3 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 14 0.02% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 154 0.17% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 280 0.31% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 1 0.00% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 18 0.02% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 2 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 88 0.10% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 77 0.08% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 387 0.42% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 193 0.21% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 69 0.08% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 13 0.01% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 277 0.30% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 139 0.15% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 17 0.02% 91.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 11 0.01% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 459 0.50% 92.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 92.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 99 0.11% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 3 0.00% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 3 0.00% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 148 0.16% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 92.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::45760-45767 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 326 0.36% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 68 0.07% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46400-46407 1 0.00% 92.92% # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 85 0.09% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 2 0.00% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 2 0.00% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 398 0.43% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 77 0.08% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 140 0.15% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 56 0.06% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 70 0.08% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5010 5.47% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49607 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 151 0.17% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 285 0.31% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 17 0.02% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 140 0.15% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 15 0.02% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 339 0.37% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 2 0.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 80 0.09% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 79 0.09% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 82 0.09% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 389 0.43% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 92 0.10% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 12 0.01% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48704-48711 2 0.00% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 69 0.08% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5070 5.54% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::50112-50119 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51776-51783 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52032-52039 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91629 # Bytes accessed per row activation -system.physmem.totQLat 370859657500 # Total ticks spent queuing -system.physmem.totMemAccLat 464833837500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76318685000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17655495000 # Total ticks spent accessing banks -system.physmem.avgQLat 24296.78 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1156.70 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52231 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91489 # Bytes accessed per row activation +system.physmem.totQLat 370803624750 # Total ticks spent queuing +system.physmem.totMemAccLat 464795231000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76315665000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17675941250 # Total ticks spent accessing banks +system.physmem.avgQLat 24294.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1158.08 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30453.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30452.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.95 # Data bus utilization in percentage system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.21 # Average write queue length when enqueuing -system.physmem.readRowHits 15189856 # Number of row buffer hits during reads -system.physmem.writeRowHits 98161 # Number of row buffer hits during writes +system.physmem.avgWrQLen 14.44 # Average write queue length when enqueuing +system.physmem.readRowHits 15189237 # Number of row buffer hits during reads +system.physmem.writeRowHits 97938 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.68 # Row buffer hit rate for writes -system.physmem.avgGap 161575.49 # Average gap between requests +system.physmem.writeRowHitRate 84.76 # Row buffer hit rate for writes +system.physmem.avgGap 161581.71 # Average gap between requests system.physmem.pageHitRate 99.40 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.44 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.46 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -793,299 +782,299 @@ system.realview.nvmem.bw_inst_read::total 172 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54229250 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352579 # Transaction distribution -system.membus.trans_dist::ReadResp 16352579 # Transaction distribution -system.membus.trans_dist::WriteReq 769165 # Transaction distribution -system.membus.trans_dist::WriteResp 769165 # Transaction distribution -system.membus.trans_dist::Writeback 66909 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35978 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18300 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14191 # Transaction distribution -system.membus.trans_dist::ReadExReq 138286 # Transaction distribution -system.membus.trans_dist::ReadExResp 137908 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384274 # Packet count per connected master and slave (bytes) +system.membus.throughput 54211188 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352626 # Transaction distribution +system.membus.trans_dist::ReadResp 16352626 # Transaction distribution +system.membus.trans_dist::WriteReq 769179 # Transaction distribution +system.membus.trans_dist::WriteResp 769179 # Transaction distribution +system.membus.trans_dist::Writeback 66581 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35757 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18322 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14211 # Transaction distribution +system.membus.trans_dist::ReadExReq 137874 # Transaction distribution +system.membus.trans_dist::ReadExResp 137463 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384372 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13818 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1977266 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4377428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4376186 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34655060 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392545 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34653818 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392693 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27636 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17766916 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20191657 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17718532 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20143401 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141302185 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141302185 # Total data (bytes) +system.membus.tot_pkt_size::total 141253929 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141253929 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1488154000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1488197499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11766000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11766500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1797499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17661743000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17658492000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4847485258 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4844234238 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34183780195 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34183641699 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 73073 # number of replacements -system.l2c.tags.tagsinuse 53003.397460 # Cycle average of tags in use -system.l2c.tags.total_refs 1874154 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 138227 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.558523 # Average number of references to valid blocks. +system.l2c.tags.replacements 72645 # number of replacements +system.l2c.tags.tagsinuse 53020.689119 # Cycle average of tags in use +system.l2c.tags.total_refs 1874829 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137818 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.603658 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37718.016524 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.174616 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 37720.403327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.416210 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4163.072469 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2965.510583 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.620056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4041.319246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4099.683602 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575531 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4180.066464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2958.458343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.364086 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4038.603525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4106.376802 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063523 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061666 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062556 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808768 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3081 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9065 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52647 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18858156 # Number of tag accesses -system.l2c.tags.data_accesses 18858156 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22538 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4343 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 33531 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5781 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 608221 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201520 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435370 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583255 # number of Writeback hits -system.l2c.Writeback_hits::total 583255 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1158 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 763 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1921 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 161 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 371 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47894 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59257 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107151 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4343 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 393811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 213519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 33531 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5781 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 608221 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260777 # number of demand (read+write) hits -system.l2c.demand_hits::total 1542521 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22538 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4343 # number of overall hits -system.l2c.overall_hits::cpu0.inst 393811 # number of overall hits -system.l2c.overall_hits::cpu0.data 213519 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 33531 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5781 # number of overall hits -system.l2c.overall_hits::cpu1.inst 608221 # number of overall hits -system.l2c.overall_hits::cpu1.data 260777 # number of overall hits -system.l2c.overall_hits::total 1542521 # number of overall hits +system.l2c.tags.occ_percent::cpu0.inst 0.063783 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045142 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061624 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.062658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.809032 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3126 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8643 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53076 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994385 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66441.329129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62437.741144 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1276,67 +1265,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58740655 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2741580 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2741579 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769165 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769165 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583255 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35242 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18671 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259438 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259438 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800468 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073661 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13619 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56672 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1230417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15509 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 76068 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8087268 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25596864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34696353 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17380 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90204 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39355008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48247560 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 134188 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148160681 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148160681 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4896624 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4922304939 # Layer occupancy (ticks) +system.toL2Bus.throughput 58734643 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2740334 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2740333 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769179 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769179 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583828 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35005 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18696 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53701 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259560 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259560 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1075466 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57080 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1228838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820247 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15511 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75325 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8086020 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25566400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34789221 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 92772 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39303552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48210820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22868 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148136601 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148136601 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4903748 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4924229951 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1803966688 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1801808391 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1516604948 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1518829470 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9296947 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9386457 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34267946 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34051657 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2771620829 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2768216654 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 3258153300 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 3257831802 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 9753444 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 9819444 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 42798427 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 42547912 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47398269 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322887 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322887 # Transaction distribution -system.iobus.trans_dist::WriteReq 8066 # Transaction distribution -system.iobus.trans_dist::WriteResp 8066 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8846 # Packet count per connected master and slave (bytes) +system.iobus.throughput 47398726 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322919 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322919 # Transaction distribution +system.iobus.trans_dist::WriteReq 8083 # Transaction distribution +system.iobus.trans_dist::WriteResp 8083 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8844 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1353,17 +1342,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384372 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32661906 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17692 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32662004 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17688 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1380,14 +1369,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392545 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392693 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503073 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503073 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 123503221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503221 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4429000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4428000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1397,7 +1386,7 @@ system.iobus.reqLayer4.occupancy 27000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1433,19 +1422,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376208000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376289000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41458010805 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41457903301 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 6118154 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4670367 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295970 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3816631 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2949053 # Number of BTB hits +system.cpu0.branchPred.lookups 6116113 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4670014 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294465 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3791796 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2947023 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.268486 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 684315 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28445 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.721032 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 683382 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28116 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1469,25 +1458,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8969635 # DTB read hits -system.cpu0.dtb.read_misses 28952 # DTB read misses -system.cpu0.dtb.write_hits 5211846 # DTB write hits -system.cpu0.dtb.write_misses 5698 # DTB write misses +system.cpu0.dtb.read_hits 8971213 # DTB read hits +system.cpu0.dtb.read_misses 29038 # DTB read misses +system.cpu0.dtb.write_hits 5214205 # DTB write hits +system.cpu0.dtb.write_misses 5642 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1738 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 275 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1740 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 972 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 590 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8998587 # DTB read accesses -system.cpu0.dtb.write_accesses 5217544 # DTB write accesses +system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9000251 # DTB read accesses +system.cpu0.dtb.write_accesses 5219847 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14181481 # DTB hits -system.cpu0.dtb.misses 34650 # DTB misses -system.cpu0.dtb.accesses 14216131 # DTB accesses +system.cpu0.dtb.hits 14185418 # DTB hits +system.cpu0.dtb.misses 34680 # DTB misses +system.cpu0.dtb.accesses 14220098 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1509,8 +1498,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4279077 # ITB inst hits -system.cpu0.itb.inst_misses 5117 # ITB inst misses +system.cpu0.itb.inst_hits 4275051 # ITB inst hits +system.cpu0.itb.inst_misses 5189 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1519,148 +1508,148 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1212 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1217 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1385 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1383 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4284194 # ITB inst accesses -system.cpu0.itb.hits 4279077 # DTB hits -system.cpu0.itb.misses 5117 # DTB misses -system.cpu0.itb.accesses 4284194 # DTB accesses -system.cpu0.numCycles 70223968 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4280240 # ITB inst accesses +system.cpu0.itb.hits 4275051 # DTB hits +system.cpu0.itb.misses 5189 # DTB misses +system.cpu0.itb.accesses 4280240 # DTB accesses +system.cpu0.numCycles 70241745 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11927082 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32438478 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6118154 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3633368 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7610656 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1458202 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60559 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20342851 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5497 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47160 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1383184 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4277582 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 158526 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2073 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42423154 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.988026 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.369139 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11929498 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32445295 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6116113 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3630405 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7610256 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1455955 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 63581 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20356712 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5910 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46897 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1384514 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 336 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4273539 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157097 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2132 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42442805 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.987587 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.368800 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34819772 82.08% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 571665 1.35% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 825898 1.95% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 684492 1.61% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 779946 1.84% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 566234 1.33% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 677676 1.60% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 358556 0.85% 92.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3138915 7.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34839840 82.09% 82.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 572205 1.35% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 825004 1.94% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 684840 1.61% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 778500 1.83% 88.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 566486 1.33% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 678699 1.60% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 357241 0.84% 92.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3139990 7.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42423154 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.087123 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461929 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12476093 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21540045 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6871897 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 553157 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 981962 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 949644 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64975 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40551006 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213850 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 981962 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13051542 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5910563 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13528575 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6803012 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2147500 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39435352 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 334 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 441883 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1170709 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 119 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39847910 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 180543493 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 163844376 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4138 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31495709 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8352200 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460642 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417076 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5513022 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7756413 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5773431 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120554 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1217575 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37342460 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 905810 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37712626 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 83166 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6296628 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13228023 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256791 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42423154 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.888963 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.506683 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42442805 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.087072 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461909 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12488007 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21548451 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6870426 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 554367 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 981554 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 948390 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64682 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40553105 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 211793 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 981554 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13063645 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5927392 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13516172 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6803229 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2150813 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39442908 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 349 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 442190 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1172580 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 108 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39856158 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 180580051 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 163873696 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4140 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31502925 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8353232 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 459972 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 416665 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5510720 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7760142 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5773435 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1130797 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1218383 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37351008 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 906143 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37719109 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82376 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6300240 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13226792 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257129 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42442805 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888704 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.506616 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27070740 63.81% 63.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5892236 13.89% 77.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3160742 7.45% 85.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2473733 5.83% 90.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2116122 4.99% 95.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 945480 2.23% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 519157 1.22% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188675 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56269 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27084248 63.81% 63.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5900278 13.90% 77.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3162124 7.45% 85.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2465638 5.81% 90.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2124054 5.00% 95.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 938721 2.21% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 522569 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188950 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56223 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42423154 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42442805 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27921 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839960 77.98% 80.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208811 19.39% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27701 2.58% 2.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 461 0.04% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 838727 78.09% 80.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207210 19.29% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22686320 60.16% 60.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48095 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14552 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22689290 60.15% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48124 0.13% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued @@ -1677,7 +1666,7 @@ system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Ty system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued @@ -1688,380 +1677,380 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9430202 25.01% 85.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5532744 14.67% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9432418 25.01% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5534012 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37712626 # Type of FU issued -system.cpu0.iq.rate 0.537034 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1077156 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028562 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119034571 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44552771 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34849273 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8516 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4702 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38770775 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4456 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316259 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37719109 # Type of FU issued +system.cpu0.iq.rate 0.536990 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1074099 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028476 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119063513 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44565262 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34855631 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8367 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4694 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38774303 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4353 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316534 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1371122 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2677 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13108 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 538058 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1373139 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2492 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13119 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 536810 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149551 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5893 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149889 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5851 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 981962 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4290254 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 101346 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38366333 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 82356 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7756413 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5773431 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 579216 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40773 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5894 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13108 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150282 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117544 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267826 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37333576 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9286892 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 379050 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 981554 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4303712 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 102086 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38375609 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 82190 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7760142 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5773435 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 578535 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 41087 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6130 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13119 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149567 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117143 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266710 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37339391 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9288472 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379718 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118063 # number of nop insts executed -system.cpu0.iew.exec_refs 14771553 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4961106 # Number of branches executed -system.cpu0.iew.exec_stores 5484661 # Number of stores executed -system.cpu0.iew.exec_rate 0.531636 # Inst execution rate -system.cpu0.iew.wb_sent 37138785 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34853166 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18592793 # num instructions producing a value -system.cpu0.iew.wb_consumers 35689861 # num instructions consuming a value +system.cpu0.iew.exec_nop 118458 # number of nop insts executed +system.cpu0.iew.exec_refs 14775675 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4960531 # Number of branches executed +system.cpu0.iew.exec_stores 5487203 # Number of stores executed +system.cpu0.iew.exec_rate 0.531584 # Inst execution rate +system.cpu0.iew.wb_sent 37145263 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34859509 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18586335 # num instructions producing a value +system.cpu0.iew.wb_consumers 35686170 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496314 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520954 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496279 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520827 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6112781 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 649019 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232084 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41441192 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.767334 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.727698 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6112161 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 649014 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 230918 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41461251 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.767144 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.727678 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29493448 71.17% 71.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5926009 14.30% 85.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1935659 4.67% 90.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1007052 2.43% 92.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 761622 1.84% 94.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 520069 1.25% 95.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 411110 0.99% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 222523 0.54% 97.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1163700 2.81% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29511356 71.18% 71.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5920392 14.28% 85.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1945303 4.69% 90.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1006881 2.43% 92.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 766693 1.85% 94.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 514145 1.24% 95.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 405651 0.98% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 222934 0.54% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1167896 2.82% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41441192 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24076968 # Number of instructions committed -system.cpu0.commit.committedOps 31799237 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41461251 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24081359 # Number of instructions committed +system.cpu0.commit.committedOps 31806750 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11620664 # Number of memory references committed -system.cpu0.commit.loads 6385291 # Number of loads committed -system.cpu0.commit.membars 231891 # Number of memory barriers committed -system.cpu0.commit.branches 4352331 # Number of branches committed +system.cpu0.commit.refs 11623628 # Number of memory references committed +system.cpu0.commit.loads 6387003 # Number of loads committed +system.cpu0.commit.membars 231881 # Number of memory barriers committed +system.cpu0.commit.branches 4353159 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28144226 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499126 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1163700 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28151052 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499153 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1167896 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77320455 # The number of ROB reads -system.cpu0.rob.rob_writes 76807713 # The number of ROB writes -system.cpu0.timesIdled 366523 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27800814 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5141023759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23996226 # Number of Instructions Simulated -system.cpu0.committedOps 31718495 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23996226 # Number of Instructions Simulated -system.cpu0.cpi 2.926459 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.926459 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341710 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341710 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174280890 # number of integer regfile reads -system.cpu0.int_regfile_writes 34606104 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3371 # number of floating regfile reads -system.cpu0.fp_regfile_writes 930 # number of floating regfile writes -system.cpu0.misc_regfile_reads 79193882 # number of misc regfile reads -system.cpu0.misc_regfile_writes 501030 # number of misc regfile writes -system.cpu0.icache.tags.replacements 399855 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.561575 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3845551 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 400367 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.605065 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7054920250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.561575 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999144 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 77343282 # The number of ROB reads +system.cpu0.rob.rob_writes 76821100 # The number of ROB writes +system.cpu0.timesIdled 366365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27798940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5140962052 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24000617 # Number of Instructions Simulated +system.cpu0.committedOps 31726008 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24000617 # Number of Instructions Simulated +system.cpu0.cpi 2.926664 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.926664 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341686 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341686 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174312752 # number of integer regfile reads +system.cpu0.int_regfile_writes 34607985 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3310 # number of floating regfile reads +system.cpu0.fp_regfile_writes 918 # number of floating regfile writes +system.cpu0.misc_regfile_reads 79392098 # number of misc regfile reads +system.cpu0.misc_regfile_writes 500989 # number of misc regfile writes +system.cpu0.icache.tags.replacements 399371 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.568929 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3842185 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 399883 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.608273 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7067442000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568929 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999158 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999158 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4677842 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4677842 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3845551 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3845551 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3845551 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3845551 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3845551 # number of overall hits -system.cpu0.icache.overall_hits::total 3845551 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431900 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431900 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431900 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431900 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431900 # number of overall misses -system.cpu0.icache.overall_misses::total 431900 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5980648802 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5980648802 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5980648802 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5980648802 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5980648802 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5980648802 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4277451 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4277451 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4277451 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4277451 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4277451 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4277451 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100971 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100971 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100971 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100971 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100971 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100971 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13847.299843 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13847.299843 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13847.299843 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13847.299843 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13847.299843 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13847.299843 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3472 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 4673316 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 4673316 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 3842185 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3842185 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3842185 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3842185 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3842185 # number of overall hits +system.cpu0.icache.overall_hits::total 3842185 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431224 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431224 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 431224 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 431224 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 431224 # number of overall misses +system.cpu0.icache.overall_misses::total 431224 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969029520 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5969029520 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5969029520 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5969029520 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5969029520 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5969029520 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4273409 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4273409 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4273409 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4273409 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4273409 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4273409 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100909 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100909 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100909 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100909 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100909 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100909 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13842.062408 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13842.062408 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13842.062408 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13842.062408 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13842.062408 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13842.062408 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4009 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.993377 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.308140 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31508 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31508 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31508 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4871658304 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4871658304 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4871658304 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4871658304 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31316 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31316 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31316 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31316 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31316 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31316 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399908 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 399908 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 399908 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 399908 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 399908 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 399908 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4860978096 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4860978096 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4860978096 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4860978096 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4860978096 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4860978096 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9448000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9448000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9448000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 9448000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093605 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093605 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093605 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093605 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12167.221883 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12167.221883 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12167.221883 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12167.221883 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093581 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093581 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093581 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12155.240945 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12155.240945 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.240945 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12155.240945 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 275331 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.265935 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9430413 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 275843 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.187610 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 275793 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.388822 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9427243 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276305 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.118974 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43744250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.265935 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938019 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938019 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.388822 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938259 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938259 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 45818436 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 45818436 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5876487 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5876487 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3229447 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3229447 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139508 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139508 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137243 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137243 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9105934 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9105934 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9105934 # number of overall hits -system.cpu0.dcache.overall_hits::total 9105934 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392643 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392643 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1584583 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1584583 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8921 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8921 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7758 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7758 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1977226 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1977226 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1977226 # number of overall misses -system.cpu0.dcache.overall_misses::total 1977226 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519657990 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5519657990 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80059065889 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 80059065889 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91816480 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 91816480 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49938268 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 49938268 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 85578723879 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 85578723879 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 85578723879 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 85578723879 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269130 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6269130 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4814030 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4814030 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148429 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148429 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145001 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 145001 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11083160 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11083160 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11083160 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11083160 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062631 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062631 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329159 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.329159 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060103 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060103 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053503 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053503 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178399 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178399 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178399 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178399 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14057.701245 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14057.701245 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50523.744032 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50523.744032 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10292.173523 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10292.173523 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6437.002836 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6437.002836 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43282.216539 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43282.216539 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9306 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7994 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 611 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 137 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.230769 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 58.350365 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 45827663 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45827663 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5876905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5876905 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3228758 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3228758 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139532 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139532 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137231 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137231 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9105663 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9105663 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9105663 # number of overall hits +system.cpu0.dcache.overall_hits::total 9105663 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 393187 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 393187 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1586487 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1586487 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7768 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7768 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1979674 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1979674 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1979674 # number of overall misses +system.cpu0.dcache.overall_misses::total 1979674 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5526786247 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5526786247 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79724845605 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79724845605 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91251732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 91251732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50083768 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50083768 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85251631852 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85251631852 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85251631852 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85251631852 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6270092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6270092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4815245 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4815245 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148435 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148435 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144999 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144999 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11085337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11085337 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11085337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11085337 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062708 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062708 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329472 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.329472 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059979 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059979 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053573 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053573 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178585 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178585 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178585 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178585 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14056.380926 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14056.380926 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50252.441782 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50252.441782 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10249.548691 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10249.548691 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6447.446962 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6447.446962 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43063.469971 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43063.469971 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43063.469971 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43063.469971 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8922 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 589 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.147708 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 55.632353 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255436 # number of writebacks -system.cpu0.dcache.writebacks::total 255436 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203336 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203336 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453472 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1453472 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656808 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1656808 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656808 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1656808 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189307 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189307 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131111 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131111 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8437 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8437 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320418 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320418 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2405173678 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2405173678 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5317055578 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5317055578 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69940520 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69940520 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34423732 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34423732 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 256103 # number of writebacks +system.cpu0.dcache.writebacks::total 256103 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203673 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203673 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455296 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1455296 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1658969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658969 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1658969 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189514 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189514 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131191 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131191 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8434 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8434 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7768 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7768 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320705 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320705 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320705 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320705 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2409533443 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2409533443 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5292752283 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5292752283 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69541268 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69541268 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34547232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34547232 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7722229256 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7722229256 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7722229256 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7722229256 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13428836532 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13428836532 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1202345879 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1202345879 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631182411 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631182411 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030197 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030197 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027235 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027235 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056842 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056842 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053503 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053503 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.149192 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.149192 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40553.848098 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40553.848098 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8289.738059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8289.738059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4437.191544 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4437.191544 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7702285726 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7702285726 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7702285726 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7702285726 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13436185037 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13436185037 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206083884 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206083884 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14642268921 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14642268921 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030225 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030225 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027245 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027245 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056819 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056819 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053573 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053573 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028931 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028931 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028931 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028931 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12714.276745 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12714.276745 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40343.867209 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40343.867209 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8245.348352 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8245.348352 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4447.377961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4447.377961 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24016.731033 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24016.731033 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24016.731033 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24016.731033 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -2069,15 +2058,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9295999 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7633656 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 416141 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5924050 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5051274 # Number of BTB hits +system.cpu1.branchPred.lookups 9293568 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7630023 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 416409 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5939121 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5050753 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.267241 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 796895 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43453 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.042096 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 798930 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43976 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2101,25 +2090,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42971577 # DTB read hits -system.cpu1.dtb.read_misses 38230 # DTB read misses -system.cpu1.dtb.write_hits 6978417 # DTB write hits -system.cpu1.dtb.write_misses 10824 # DTB write misses +system.cpu1.dtb.read_hits 42973192 # DTB read hits +system.cpu1.dtb.read_misses 37885 # DTB read misses +system.cpu1.dtb.write_hits 6980403 # DTB write hits +system.cpu1.dtb.write_misses 10788 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2766 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1925 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2835 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43009807 # DTB read accesses -system.cpu1.dtb.write_accesses 6989241 # DTB write accesses +system.cpu1.dtb.read_accesses 43011077 # DTB read accesses +system.cpu1.dtb.write_accesses 6991191 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49949994 # DTB hits -system.cpu1.dtb.misses 49054 # DTB misses -system.cpu1.dtb.accesses 49999048 # DTB accesses +system.cpu1.dtb.hits 49953595 # DTB hits +system.cpu1.dtb.misses 48673 # DTB misses +system.cpu1.dtb.accesses 50002268 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2141,8 +2130,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7718441 # ITB inst hits -system.cpu1.itb.inst_misses 5545 # ITB inst misses +system.cpu1.itb.inst_hits 7723190 # ITB inst hits +system.cpu1.itb.inst_misses 5562 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2151,114 +2140,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1355 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1359 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1471 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7723986 # ITB inst accesses -system.cpu1.itb.hits 7718441 # DTB hits -system.cpu1.itb.misses 5545 # DTB misses -system.cpu1.itb.accesses 7723986 # DTB accesses -system.cpu1.numCycles 413843853 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7728752 # ITB inst accesses +system.cpu1.itb.hits 7723190 # DTB hits +system.cpu1.itb.misses 5562 # DTB misses +system.cpu1.itb.accesses 7728752 # DTB accesses +system.cpu1.numCycles 413796923 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19379988 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61315433 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9295999 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5848169 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13365504 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3344948 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 69502 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 81000911 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 40728 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1501346 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7716683 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 552961 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 117651923 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.637947 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.959423 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19367440 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61322975 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9293568 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5849683 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13369526 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3346649 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69265 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 80967245 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 6008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41697 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1506074 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 288 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7721399 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 552563 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2913 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117616541 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.638291 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.959867 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 104293797 88.65% 88.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 816533 0.69% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 959642 0.82% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1712278 1.46% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1420540 1.21% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 586826 0.50% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1954913 1.66% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 421869 0.36% 95.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5485525 4.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 104254528 88.64% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 816257 0.69% 89.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 960958 0.82% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1713992 1.46% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1419991 1.21% 92.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 586388 0.50% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1955965 1.66% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 421912 0.36% 95.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5486550 4.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 117651923 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022463 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.148161 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20970716 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 81766548 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11917801 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 808551 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2188307 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1138241 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 101191 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71099803 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 336135 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2188307 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22164827 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33899952 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 43340583 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11475244 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4583010 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67141114 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 681863 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3070840 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 445 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 70764915 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 313106059 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 286755701 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6517 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50418755 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20346160 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 765693 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 705478 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8425217 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12844634 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8117566 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1057819 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1511606 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 61861483 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1182497 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88912346 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94590 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13560397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36234299 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 282991 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 117651923 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.755724 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.498826 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117616541 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022459 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.148196 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20958094 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 81738883 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11922126 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 807725 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2189713 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1139186 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 101010 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71114524 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 335626 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2189713 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22150930 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33873368 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 43341870 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11481154 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4579506 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67156903 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 160 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 681335 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3069410 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 515 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70770910 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 313189992 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 286825978 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6578 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50413534 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20357376 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 766049 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 705865 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8415941 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12847707 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8121662 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1063533 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1519311 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 61868936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1182413 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88920941 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95302 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13575964 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36252507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 283075 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117616541 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.756024 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.499146 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86792358 73.77% 73.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9289300 7.90% 81.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4170595 3.54% 85.21% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3605495 3.06% 88.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10372617 8.82% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1993778 1.69% 98.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1066938 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282351 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78491 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86757290 73.76% 73.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9288969 7.90% 81.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4169197 3.54% 85.21% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3602778 3.06% 88.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10372979 8.82% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1998574 1.70% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1065464 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 282646 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 78644 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 117651923 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117616541 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32498 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 992 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32554 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 991 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -2286,13 +2275,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7572169 95.70% 96.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 306556 3.87% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7574498 95.71% 96.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 306293 3.87% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14270 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37625981 42.32% 42.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61252 0.07% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14269 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37628828 42.32% 42.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61233 0.07% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued @@ -2305,11 +2294,11 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued @@ -2318,373 +2307,377 @@ system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Ty system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43860086 49.33% 91.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7349035 8.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43862772 49.33% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7352107 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88912346 # Type of FU issued -system.cpu1.iq.rate 0.214845 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7912215 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088989 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 303516932 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 76613298 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54268341 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15366 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8022 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96802135 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8156 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 354682 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88920941 # Type of FU issued +system.cpu1.iq.rate 0.214890 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7914336 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089004 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 303501191 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 76636250 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54272980 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15357 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8072 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6822 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96812856 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8152 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 352971 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2862502 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4198 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17495 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1113245 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2867339 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4206 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1118674 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965664 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675731 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965666 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675765 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2188307 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26389520 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 363046 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63147070 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 115346 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12844634 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8117566 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 886491 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65999 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3974 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17495 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203953 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158404 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 362357 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87176512 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43353711 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1735834 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2189713 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26359334 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 362918 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63155083 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 115853 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12847707 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8121662 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 886435 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65883 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4133 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 204959 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158107 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 363066 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87182630 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43355393 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1738311 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103090 # number of nop insts executed -system.cpu1.iew.exec_refs 50638153 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7380246 # Number of branches executed -system.cpu1.iew.exec_stores 7284442 # Number of stores executed -system.cpu1.iew.exec_rate 0.210651 # Inst execution rate -system.cpu1.iew.wb_sent 86413088 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54275144 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30296614 # num instructions producing a value -system.cpu1.iew.wb_consumers 53882453 # num instructions consuming a value +system.cpu1.iew.exec_nop 103734 # number of nop insts executed +system.cpu1.iew.exec_refs 50641864 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7379983 # Number of branches executed +system.cpu1.iew.exec_stores 7286471 # Number of stores executed +system.cpu1.iew.exec_rate 0.210689 # Inst execution rate +system.cpu1.iew.wb_sent 86418752 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54279802 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30301489 # num instructions producing a value +system.cpu1.iew.wb_consumers 53896999 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131149 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.562272 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131175 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.562211 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13436842 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899506 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 316660 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 115463616 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.426258 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.378914 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13446942 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 317124 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 115426828 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.426339 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.379011 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97442898 84.39% 84.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9592965 8.31% 92.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2168696 1.88% 94.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1301481 1.13% 95.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 990246 0.86% 96.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 587576 0.51% 97.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1009945 0.87% 97.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 534541 0.46% 98.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1835268 1.59% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97406330 84.39% 84.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9593486 8.31% 92.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2169699 1.88% 94.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1301842 1.13% 95.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 990133 0.86% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 584983 0.51% 97.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1011097 0.88% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 533551 0.46% 98.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1835707 1.59% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 115463616 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38874177 # Number of instructions committed -system.cpu1.commit.committedOps 49217265 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 115426828 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38871006 # Number of instructions committed +system.cpu1.commit.committedOps 49210952 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16986453 # Number of memory references committed -system.cpu1.commit.loads 9982132 # Number of loads committed -system.cpu1.commit.membars 195521 # Number of memory barriers committed -system.cpu1.commit.branches 6425226 # Number of branches committed +system.cpu1.commit.refs 16983356 # Number of memory references committed +system.cpu1.commit.loads 9980368 # Number of loads committed +system.cpu1.commit.membars 195496 # Number of memory barriers committed +system.cpu1.commit.branches 6424614 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43929395 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553319 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1835268 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43923604 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553281 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1835707 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175215898 # The number of ROB reads -system.cpu1.rob.rob_writes 127579322 # The number of ROB writes -system.cpu1.timesIdled 1429072 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 296191930 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796799037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38804538 # Number of Instructions Simulated -system.cpu1.committedOps 49147626 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38804538 # Number of Instructions Simulated -system.cpu1.cpi 10.664831 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.664831 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093766 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093766 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391691607 # number of integer regfile reads -system.cpu1.int_regfile_writes 56383706 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5043 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes -system.cpu1.misc_regfile_reads 202850334 # number of misc regfile reads -system.cpu1.misc_regfile_writes 723182 # number of misc regfile writes -system.cpu1.icache.tags.replacements 614906 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.718219 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7054617 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 615418 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.463131 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74929846000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.718219 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974059 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974059 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 175182622 # The number of ROB reads +system.cpu1.rob.rob_writes 127588630 # The number of ROB writes +system.cpu1.timesIdled 1428402 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 296180382 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796803337 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38801367 # Number of Instructions Simulated +system.cpu1.committedOps 49141313 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38801367 # Number of Instructions Simulated +system.cpu1.cpi 10.664493 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.664493 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093769 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093769 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391717330 # number of integer regfile reads +system.cpu1.int_regfile_writes 56386728 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5093 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes +system.cpu1.misc_regfile_reads 202967536 # number of misc regfile reads +system.cpu1.misc_regfile_writes 722997 # number of misc regfile writes +system.cpu1.icache.tags.replacements 614130 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.669942 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7060189 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 614642 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.486669 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74938249500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.669942 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973965 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973965 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8332076 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8332076 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 7054617 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7054617 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7054617 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7054617 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7054617 # number of overall hits -system.cpu1.icache.overall_hits::total 7054617 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 662013 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 662013 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 662013 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 662013 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 662013 # number of overall misses -system.cpu1.icache.overall_misses::total 662013 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8999563943 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8999563943 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8999563943 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8999563943 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8999563943 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8999563943 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7716630 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7716630 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7716630 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7716630 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7716630 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7716630 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085790 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.085790 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085790 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.085790 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085790 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.085790 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13594.240510 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13594.240510 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13594.240510 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13594.240510 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13594.240510 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13594.240510 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3570 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 201 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 17.761194 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 8336018 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8336018 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7060189 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7060189 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7060189 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7060189 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7060189 # number of overall hits +system.cpu1.icache.overall_hits::total 7060189 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661158 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661158 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661158 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661158 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661158 # number of overall misses +system.cpu1.icache.overall_misses::total 661158 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8979670253 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8979670253 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8979670253 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8979670253 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8979670253 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8979670253 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7721347 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7721347 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7721347 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7721347 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7721347 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7721347 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085627 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.085627 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085627 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.085627 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085627 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.085627 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13581.731225 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13581.731225 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13581.731225 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13581.731225 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13581.731225 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13581.731225 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3157 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 541 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 208 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.177885 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 541 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46567 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46567 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46567 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46567 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46567 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46567 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615446 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 615446 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 615446 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 615446 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 615446 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 615446 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343690408 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343690408 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343690408 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7343690408 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343690408 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7343690408 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3568500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3568500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3568500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3568500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079756 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079756 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079756 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079756 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11932.306665 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11932.306665 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11932.306665 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11932.306665 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46487 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46487 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46487 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46487 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46487 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46487 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 614671 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 614671 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 614671 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 614671 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 614671 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 614671 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7323309836 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7323309836 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7323309836 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7323309836 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7323309836 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7323309836 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3568000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3568000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3568000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3568000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079607 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079607 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079607 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.079607 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.194481 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.194481 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.194481 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.194481 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 363287 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.536511 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 13021437 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 363669 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.805738 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70976822000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.536511 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 382 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 382 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 60298440 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 60298440 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8515057 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8515057 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4269820 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4269820 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99795 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 99795 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97086 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 97086 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12784877 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12784877 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12784877 # number of overall hits -system.cpu1.dcache.overall_hits::total 12784877 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 402462 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 402462 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1568055 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1568055 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14174 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14174 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10915 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10915 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1970517 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1970517 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1970517 # number of overall misses -system.cpu1.dcache.overall_misses::total 1970517 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6127843210 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6127843210 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 79461121233 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 79461121233 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 130724743 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 130724743 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58221587 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58221587 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 85588964443 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 85588964443 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 85588964443 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 85588964443 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8917519 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8917519 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837875 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5837875 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113969 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 113969 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108001 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 108001 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14755394 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14755394 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14755394 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14755394 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045132 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045132 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268600 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.268600 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124367 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124367 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101064 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101064 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133546 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.133546 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133546 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.133546 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15225.892656 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15225.892656 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50674.957979 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 50674.957979 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9222.854734 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9222.854734 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.089510 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.089510 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43434.775971 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 43434.775971 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43434.775971 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 43434.775971 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 28687 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 20050 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 363457 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.510277 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13025047 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 363822 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.800603 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70981354000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.510277 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948262 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.948262 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 365 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 60307713 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 60307713 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8518372 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8518372 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4270609 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4270609 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99866 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 99866 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97035 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 97035 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12788981 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12788981 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12788981 # number of overall hits +system.cpu1.dcache.overall_hits::total 12788981 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 402659 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 402659 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1566002 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1566002 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14224 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14224 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10931 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10931 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1968661 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1968661 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1968661 # number of overall misses +system.cpu1.dcache.overall_misses::total 1968661 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6122123976 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6122123976 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 79209493026 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 79209493026 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131211992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131211992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58251087 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58251087 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 85331617002 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 85331617002 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 85331617002 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 85331617002 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8921031 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8921031 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5836611 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5836611 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 114090 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 114090 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107966 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107966 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14757642 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14757642 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14757642 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14757642 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045136 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045136 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268307 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.268307 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124674 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124674 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101245 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101245 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133399 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133399 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133399 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133399 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15204.239756 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15204.239756 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50580.710003 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 50580.710003 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9224.690101 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9224.690101 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5328.980606 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5328.980606 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43345.003026 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 43345.003026 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43345.003026 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 43345.003026 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29359 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 20069 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3274 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.762065 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 115.229885 # average number of cycles each access was blocked +system.cpu1.dcache.blocked::no_targets 177 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.967318 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 113.384181 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327819 # number of writebacks -system.cpu1.dcache.writebacks::total 327819 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171130 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171130 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1404670 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1404670 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1454 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1454 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1575800 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1575800 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1575800 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1575800 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231332 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231332 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163385 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163385 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10915 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10915 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394717 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394717 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394717 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394717 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2884558137 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2884558137 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7099464771 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7099464771 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89380256 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89380256 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36390413 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36390413 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9984022908 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9984022908 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9984022908 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9984022908 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231255506 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231255506 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25855700445 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25855700445 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195086955951 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195086955951 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025941 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025941 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027987 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027987 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111609 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111609 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101064 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101064 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026751 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026751 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12469.343355 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12469.343355 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43452.365707 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43452.365707 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7026.749686 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7026.749686 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3333.981951 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3333.981951 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327725 # number of writebacks +system.cpu1.dcache.writebacks::total 327725 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171279 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171279 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402802 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1402802 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574081 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1574081 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574081 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1574081 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231380 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231380 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163200 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163200 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12769 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10931 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10931 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394580 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394580 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394580 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394580 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2885564133 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2885564133 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7076211500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7076211500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89844256 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89844256 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36388913 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36388913 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9961775633 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9961775633 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9961775633 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9961775633 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169230997009 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169230997009 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25854670209 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25854670209 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195085667218 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195085667218 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025936 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025936 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027961 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027961 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111920 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111920 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101245 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101245 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026737 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026737 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026737 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026737 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12471.104387 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12471.104387 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43359.139093 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43359.139093 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7036.123111 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7036.123111 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3328.964688 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3328.964688 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25246.529558 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25246.529558 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25246.529558 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25246.529558 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2708,18 +2701,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1519279146805 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1519279146805 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519280505301 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1519280505301 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519280505301 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1519280505301 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42657 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42637 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50405 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50394 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index bbb1c38b2..2c40bbbf1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526147 # Number of seconds simulated -sim_ticks 2526146947500 # Number of ticks simulated -final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526127 # Number of seconds simulated +sim_ticks 2526126762000 # Number of ticks simulated +final_tick 2526126762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69975 # Simulator instruction rate (inst/s) -host_op_rate 90038 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2931166527 # Simulator tick rate (ticks/s) -host_mem_usage 424336 # Number of bytes of host memory used -host_seconds 861.82 # Real time elapsed on the host -sim_insts 60306154 # Number of instructions simulated -sim_ops 77597242 # Number of ops (including micro ops) simulated +host_inst_rate 60304 # Simulator instruction rate (inst/s) +host_op_rate 77594 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2525902204 # Simulator tick rate (ticks/s) +host_mem_usage 424400 # Number of bytes of host memory used +host_seconds 1000.09 # Real time elapsed on the host +sim_insts 60309150 # Number of instructions simulated +sim_ops 77600646 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093912 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096848 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47320533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1089 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3599943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51237470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1497768 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691719 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1497768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47320533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1089 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096836 # Number of read requests accepted -system.physmem.writeReqs 813120 # Number of write requests accepted -system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943071 # Per bank write bursts -system.physmem.perBankRdBursts::2 939289 # Per bank write bursts -system.physmem.perBankRdBursts::3 939279 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4793894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53929189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096848 # Number of read requests accepted +system.physmem.writeReqs 813136 # Number of write requests accepted +system.physmem.readBursts 15096848 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813136 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963809856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2388416 # Total number of bytes read from write queue +system.physmem.bytesWritten 6900096 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6799624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 37319 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705316 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4693 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943581 # Per bank write bursts +system.physmem.perBankRdBursts::1 943177 # Per bank write bursts +system.physmem.perBankRdBursts::2 939217 # Per bank write bursts +system.physmem.perBankRdBursts::3 939246 # Per bank write bursts system.physmem.perBankRdBursts::4 943119 # Per bank write bursts -system.physmem.perBankRdBursts::5 943242 # Per bank write bursts -system.physmem.perBankRdBursts::6 939090 # Per bank write bursts -system.physmem.perBankRdBursts::7 938633 # Per bank write bursts -system.physmem.perBankRdBursts::8 943981 # Per bank write bursts -system.physmem.perBankRdBursts::9 943506 # Per bank write bursts -system.physmem.perBankRdBursts::10 938534 # Per bank write bursts -system.physmem.perBankRdBursts::11 937721 # Per bank write bursts -system.physmem.perBankRdBursts::12 943933 # Per bank write bursts -system.physmem.perBankRdBursts::13 943406 # Per bank write bursts -system.physmem.perBankRdBursts::14 939034 # Per bank write bursts -system.physmem.perBankRdBursts::15 938886 # Per bank write bursts -system.physmem.perBankWrBursts::0 6687 # Per bank write bursts -system.physmem.perBankWrBursts::1 6452 # Per bank write bursts -system.physmem.perBankWrBursts::2 6617 # Per bank write bursts -system.physmem.perBankWrBursts::3 6618 # Per bank write bursts -system.physmem.perBankWrBursts::4 6551 # Per bank write bursts -system.physmem.perBankWrBursts::5 6799 # Per bank write bursts -system.physmem.perBankWrBursts::6 6798 # Per bank write bursts -system.physmem.perBankWrBursts::7 6724 # Per bank write bursts -system.physmem.perBankWrBursts::8 7121 # Per bank write bursts -system.physmem.perBankWrBursts::9 6870 # Per bank write bursts -system.physmem.perBankWrBursts::10 6536 # Per bank write bursts -system.physmem.perBankWrBursts::11 6184 # Per bank write bursts -system.physmem.perBankWrBursts::12 7152 # Per bank write bursts -system.physmem.perBankWrBursts::13 6752 # Per bank write bursts -system.physmem.perBankWrBursts::14 7039 # Per bank write bursts -system.physmem.perBankWrBursts::15 6901 # Per bank write bursts +system.physmem.perBankRdBursts::5 943143 # Per bank write bursts +system.physmem.perBankRdBursts::6 939192 # Per bank write bursts +system.physmem.perBankRdBursts::7 938854 # Per bank write bursts +system.physmem.perBankRdBursts::8 943994 # Per bank write bursts +system.physmem.perBankRdBursts::9 943547 # Per bank write bursts +system.physmem.perBankRdBursts::10 939009 # Per bank write bursts +system.physmem.perBankRdBursts::11 937977 # Per bank write bursts +system.physmem.perBankRdBursts::12 943925 # Per bank write bursts +system.physmem.perBankRdBursts::13 943586 # Per bank write bursts +system.physmem.perBankRdBursts::14 939160 # Per bank write bursts +system.physmem.perBankRdBursts::15 938802 # Per bank write bursts +system.physmem.perBankWrBursts::0 6706 # Per bank write bursts +system.physmem.perBankWrBursts::1 6463 # Per bank write bursts +system.physmem.perBankWrBursts::2 6599 # Per bank write bursts +system.physmem.perBankWrBursts::3 6631 # Per bank write bursts +system.physmem.perBankWrBursts::4 6542 # Per bank write bursts +system.physmem.perBankWrBursts::5 6795 # Per bank write bursts +system.physmem.perBankWrBursts::6 6787 # Per bank write bursts +system.physmem.perBankWrBursts::7 6728 # Per bank write bursts +system.physmem.perBankWrBursts::8 7129 # Per bank write bursts +system.physmem.perBankWrBursts::9 6879 # Per bank write bursts +system.physmem.perBankWrBursts::10 6534 # Per bank write bursts +system.physmem.perBankWrBursts::11 6185 # Per bank write bursts +system.physmem.perBankWrBursts::12 7139 # Per bank write bursts +system.physmem.perBankWrBursts::13 6761 # Per bank write bursts +system.physmem.perBankWrBursts::14 7032 # Per bank write bursts +system.physmem.perBankWrBursts::15 6904 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526145872500 # Total gap between requests +system.physmem.totGap 2526125654500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154590 # Read request sizes (log2) +system.physmem.readPktSize::6 154602 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59102 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1175583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1121241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1077080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3628602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2607512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2594359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2599949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -144,31 +144,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4767 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4787 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -176,574 +176,571 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 535 0.62% 56.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 547 0.64% 57.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 279 0.32% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 297 0.34% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 152 0.18% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 456 0.53% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 120 0.14% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 137 0.16% 58.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 61 0.07% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 169 0.20% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 508 0.59% 59.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 23 0.03% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 260 0.30% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 13 0.02% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 93 0.11% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 141 0.16% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 16 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 46 0.05% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 376 0.44% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 11 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 34 0.04% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 70 0.08% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 29 0.03% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 165 0.19% 61.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 6 0.01% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 16 0.02% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 175 0.20% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.02% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 306 0.36% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 11 0.01% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 15 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 94 0.11% 61.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 22 0.03% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 5 0.01% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 99 0.11% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 8 0.01% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 93 0.11% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 21 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 5 0.01% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 365 0.42% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.01% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 85983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11289.547748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1006.032615 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16787.302098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23431 27.25% 27.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14045 16.33% 43.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2670 3.11% 46.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2200 2.56% 49.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1296 1.51% 50.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1149 1.34% 52.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 926 1.08% 53.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 910 1.06% 54.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 583 0.68% 54.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 573 0.67% 55.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 527 0.61% 56.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 540 0.63% 56.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 283 0.33% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 315 0.37% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 148 0.17% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 512 0.60% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 103 0.12% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 250 0.29% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 57 0.07% 59.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 507 0.59% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 36 0.04% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 193 0.22% 59.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 17 0.02% 59.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 103 0.12% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 71 0.08% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 17 0.02% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 58 0.07% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 468 0.54% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 249 0.29% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 8 0.01% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 28 0.03% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 30 0.03% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 18 0.02% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 6 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 116 0.13% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 10 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 18 0.02% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 420 0.49% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 24 0.03% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 6 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 25 0.03% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 21 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 157 0.18% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 5 0.01% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 20 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 11 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 13 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 363 0.42% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 9 0.01% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 91 0.11% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 13 0.02% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 7 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 5 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 21 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 11 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 161 0.19% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 11 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 9 0.01% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 13 0.02% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 56 0.07% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 5 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 15 0.02% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 79 0.09% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 18 0.02% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 9 0.01% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 348 0.40% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 7 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 23 0.03% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 1 0.00% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 95 0.11% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 17 0.02% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 100 0.12% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 11 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 484 0.56% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 7 0.01% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 86 0.10% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 3 0.00% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 2 0.00% 65.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 27 0.03% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 10 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 1 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 155 0.18% 65.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 378 0.44% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 152 0.18% 66.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 21 0.02% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 2 0.00% 66.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 72 0.08% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 2 0.00% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 466 0.54% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 96 0.11% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 85 0.10% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 17 0.02% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 345 0.40% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10311 1 0.00% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 83 0.10% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 68 0.08% 67.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 1 0.00% 67.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 39 0.05% 67.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 396 0.46% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 2 0.00% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11463 1 0.00% 68.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 156 0.18% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 8 0.01% 68.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 83 0.10% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 2 0.00% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 336 0.39% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 83 0.10% 69.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 2 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 69.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 81 0.09% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 70 0.08% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 277 0.32% 69.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 3 0.00% 69.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 151 0.18% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 132 0.15% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 32 0.04% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 2 0.00% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 338 0.39% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 77 0.09% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 2 0.00% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14791 1 0.00% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 81 0.09% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 1 0.00% 70.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 72 0.08% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 269 0.31% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 2 0.00% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 3 0.00% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15815 1 0.00% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 157 0.18% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 3 0.00% 71.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 129 0.15% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 7 0.01% 71.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 2 0.00% 71.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 524 0.61% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 3 0.00% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 130 0.15% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 3 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 155 0.18% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16967 3 0.00% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 86 0.10% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 268 0.31% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 3 0.00% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 70 0.08% 72.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 80 0.09% 73.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 2 0.00% 73.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 82 0.10% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 35 0.04% 73.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 133 0.15% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 2 0.00% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 154 0.18% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 281 0.33% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 67 0.08% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 1 0.00% 74.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 87 0.10% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 327 0.38% 74.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 77 0.09% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 10 0.01% 74.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 2 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 151 0.18% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 39 0.05% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 2 0.00% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 65 0.08% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 2 0.00% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 85 0.10% 75.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 2 0.00% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 4 0.00% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 336 0.39% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 18 0.02% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 3 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 81 0.09% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 2 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23232-23239 2 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 92 0.11% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 463 0.54% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 70 0.08% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 19 0.02% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24199 1 0.00% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 148 0.17% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 5 0.01% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 262 0.30% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 2 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 150 0.17% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 1 0.00% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 2 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 20 0.02% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 73 0.08% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 464 0.54% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 93 0.11% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 84 0.10% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 18 0.02% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 5 0.01% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 339 0.39% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 80 0.09% 79.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 3 0.00% 79.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 63 0.07% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 2 0.00% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 47 0.05% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 2 0.00% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 2 0.00% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 394 0.46% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 2 0.00% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 150 0.17% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 8 0.01% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 82 0.10% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 5 0.01% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 329 0.38% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 2 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 3 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 83 0.10% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 2 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 82 0.10% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 72 0.08% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 2 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 276 0.32% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 3 0.00% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 155 0.18% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30023 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 130 0.15% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 35 0.04% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 7 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 2 0.00% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 330 0.38% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 2 0.00% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 79 0.09% 81.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 75 0.09% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 72 0.08% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 264 0.31% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 85 0.10% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 2 0.00% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 158 0.18% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 132 0.15% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32576-32583 2 0.00% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 130 0.15% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 160 0.19% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 2 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 90 0.10% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 4 0.00% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 276 0.32% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 69 0.08% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 76 0.09% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 78 0.09% 84.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34759 1 0.00% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 329 0.38% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 37 0.04% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 132 0.15% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 157 0.18% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 3 0.00% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 272 0.32% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 68 0.08% 85.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 82 0.10% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 85 0.10% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36800-36807 2 0.00% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 328 0.38% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 78 0.09% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 2 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 7 0.01% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 154 0.18% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 389 0.45% 87.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 41 0.05% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 2 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 63 0.07% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 83 0.10% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 332 0.39% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 17 0.02% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 81 0.09% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 95 0.11% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 463 0.54% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 69 0.08% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 4 0.00% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 15 0.02% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 149 0.17% 88.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 257 0.30% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 145 0.17% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 16 0.02% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41536-41543 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 458 0.53% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 90 0.10% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42304-42311 2 0.00% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.10% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 4 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 17 0.02% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 331 0.38% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 81 0.09% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 64 0.07% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 37 0.04% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 395 0.46% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 150 0.17% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 2 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 10 0.01% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 81 0.09% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 82 0.10% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 2 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 2 0.00% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 83 0.10% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 69 0.08% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 277 0.32% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 3 0.00% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 151 0.18% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 129 0.15% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46656-46663 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46784-46791 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 36 0.04% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 330 0.38% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 81 0.09% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 82 0.10% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 74 0.09% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 266 0.31% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 154 0.18% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48704-48711 2 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 62 0.07% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 129 0.15% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 4 0.00% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4946 5.74% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 108 0.13% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 18 0.02% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 14 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 161 0.19% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 23 0.03% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 14 0.02% 63.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 4 0.00% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 356 0.41% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 11 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 163 0.19% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 2 0.00% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 16 0.02% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 2 0.00% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 50 0.06% 63.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 13 0.02% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 4 0.00% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 197 0.23% 64.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 9 0.01% 64.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 7 0.01% 64.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 223 0.26% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 13 0.02% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 5 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 140 0.16% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 88 0.10% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 2 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 158 0.18% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 14 0.02% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 1 0.00% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 345 0.40% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 5 0.01% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 8 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 13 0.02% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 18 0.02% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 6 0.01% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 141 0.16% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 6 0.01% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 41 0.05% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 2 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 10 0.01% 65.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 399 0.46% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 36 0.04% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8583 2 0.00% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 130 0.15% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 2 0.00% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 5 0.01% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 341 0.40% 66.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 3 0.00% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 145 0.17% 66.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 78 0.09% 67.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 3 0.00% 67.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 2 0.00% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 212 0.25% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 2 0.00% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 150 0.17% 67.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 41 0.05% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10887 1 0.00% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 2 0.00% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 153 0.18% 67.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 349 0.41% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 8 0.01% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 3 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 141 0.16% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 3 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 94 0.11% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 2 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 334 0.39% 68.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 13 0.02% 68.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 3 0.00% 68.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 141 0.16% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 6 0.01% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 399 0.46% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13383 1 0.00% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 1 0.00% 69.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 94 0.11% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13767 2 0.00% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 2 0.00% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 3 0.00% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14023 1 0.00% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 214 0.25% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 2 0.00% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 4 0.00% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 420 0.49% 70.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 5 0.01% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 1 0.00% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 22 0.03% 70.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 141 0.16% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 335 0.39% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 80 0.09% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 2 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15943 2 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 2 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 143 0.17% 71.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 6 0.01% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 673 0.78% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 144 0.17% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 7 0.01% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16967 2 0.00% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 81 0.09% 72.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 2 0.00% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 336 0.39% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 135 0.16% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 4 0.00% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 25 0.03% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 1 0.00% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 1 0.00% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 6 0.01% 72.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 2 0.00% 72.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 419 0.49% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 2 0.00% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 214 0.25% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18759 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 4 0.00% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 97 0.11% 73.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 391 0.45% 74.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 10 0.01% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 3 0.00% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 139 0.16% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 13 0.02% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 4 0.00% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 331 0.38% 74.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 94 0.11% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20800-20807 1 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 1 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20935 2 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 142 0.17% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 2 0.00% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 13 0.02% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 343 0.40% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 3 0.00% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 150 0.17% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 38 0.04% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22080-22087 1 0.00% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 3 0.00% 75.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 148 0.17% 76.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 2 0.00% 76.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 76.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 208 0.24% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 129 0.15% 76.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 76 0.09% 76.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 2 0.00% 76.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 148 0.17% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 1 0.00% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 338 0.39% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 10 0.01% 77.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 2 0.00% 77.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 128 0.15% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 2 0.00% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 34 0.04% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 281 0.33% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24647 2 0.00% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 3 0.00% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 36 0.04% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 132 0.15% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 9 0.01% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25536-25543 1 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 331 0.38% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 146 0.17% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 78 0.09% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 2 0.00% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 128 0.15% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 6 0.01% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 207 0.24% 78.87% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 138 0.16% 82.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 3 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 338 0.39% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 2 0.00% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 78 0.09% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 9 0.01% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 145 0.17% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 671 0.78% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32960-32967 1 0.00% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 141 0.16% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 7 0.01% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 85 0.10% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.82% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 12 0.01% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 327 0.38% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36928-36935 1 0.00% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 90 0.10% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 141 0.16% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 10 0.01% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 1 0.00% 86.59% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::40384-40391 1 0.00% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 132 0.15% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 37 0.04% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40896-40903 1 0.00% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 277 0.32% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41088-41095 1 0.00% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 34 0.04% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 128 0.15% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 10 0.01% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 332 0.39% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 142 0.17% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 76 0.09% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 131 0.15% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 208 0.24% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 145 0.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 1 0.00% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 36 0.04% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 152 0.18% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 340 0.40% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 90.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 8 0.01% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 144 0.17% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 94 0.11% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 3 0.00% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 12 0.01% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 1 0.00% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 141 0.16% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 11 0.01% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 393 0.46% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 91 0.11% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 4 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 211 0.25% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 2 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 416 0.48% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 4 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 2 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 32 0.04% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 141 0.16% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 335 0.39% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 74 0.09% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 4 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 140 0.16% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 4 0.00% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5017 5.83% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 4 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 3 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52288-52295 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86110 # Bytes accessed per row activation -system.physmem.totQLat 365142496500 # Total ticks spent queuing -system.physmem.totMemAccLat 457904364000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75291530000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17470337500 # Total ticks spent accessing banks -system.physmem.avgQLat 24248.58 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1160.18 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 85983 # Bytes accessed per row activation +system.physmem.totQLat 365185132750 # Total ticks spent queuing +system.physmem.totMemAccLat 457949856500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75297645000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17467078750 # Total ticks spent accessing banks +system.physmem.avgQLat 24249.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1159.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30408.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30409.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -752,14 +749,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.37 # Average write queue length when enqueuing -system.physmem.readRowHits 14986658 # Number of row buffer hits during reads -system.physmem.writeRowHits 93339 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.57 # Row buffer hit rate for writes -system.physmem.avgGap 158777.68 # Average gap between requests +system.physmem.avgWrQLen 14.56 # Average write queue length when enqueuing +system.physmem.readRowHits 14988012 # Number of row buffer hits during reads +system.physmem.writeRowHits 93348 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.58 # Row buffer hit rate for writes +system.physmem.avgGap 158776.13 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.54 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.53 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -772,50 +769,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54877277 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149448 # Transaction distribution -system.membus.trans_dist::ReadResp 16149448 # Transaction distribution -system.membus.trans_dist::WriteReq 763332 # Transaction distribution -system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution -system.membus.trans_dist::ReadExReq 131427 # Transaction distribution -system.membus.trans_dist::ReadExResp 131427 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) +system.membus.throughput 54878485 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149469 # Transaction distribution +system.membus.trans_dist::ReadResp 16149469 # Transaction distribution +system.membus.trans_dist::WriteReq 763349 # Transaction distribution +system.membus.trans_dist::WriteResp 763349 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4690 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4693 # Transaction distribution +system.membus.trans_dist::ReadExReq 131452 # Transaction distribution +system.membus.trans_dist::ReadExResp 131452 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272628 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34157044 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694304 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092346 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138628065 # Total data (bytes) +system.membus.tot_pkt_size::total 138630010 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630010 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486866000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17361359500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4731205438 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737720957 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -823,12 +820,12 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266379 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution -system.iobus.trans_dist::WriteReq 8157 # Transaction distribution -system.iobus.trans_dist::WriteResp 8157 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48266825 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution +system.iobus.trans_dist::WriteReq 8174 # Transaction distribution +system.iobus.trans_dist::WriteResp 8174 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) @@ -851,11 +848,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) @@ -878,12 +875,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927965 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121928118 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -931,20 +928,20 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40922322043 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14756776 # Number of BP lookups -system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits +system.cpu.branchPred.lookups 14743416 # Number of BP lookups +system.cpu.branchPred.condPredicted 11827380 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704687 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9504018 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7655579 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.550973 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397368 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72480 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -968,25 +965,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51181584 # DTB read hits -system.cpu.dtb.read_misses 65031 # DTB read misses -system.cpu.dtb.write_hits 11699885 # DTB write hits -system.cpu.dtb.write_misses 15694 # DTB write misses +system.cpu.dtb.read_hits 51180405 # DTB read hits +system.cpu.dtb.read_misses 65067 # DTB read misses +system.cpu.dtb.write_hits 11700451 # DTB write hits +system.cpu.dtb.write_misses 15748 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2401 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51246615 # DTB read accesses -system.cpu.dtb.write_accesses 11715579 # DTB write accesses +system.cpu.dtb.perms_faults 1377 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51245472 # DTB read accesses +system.cpu.dtb.write_accesses 11716199 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62881469 # DTB hits -system.cpu.dtb.misses 80725 # DTB misses -system.cpu.dtb.accesses 62962194 # DTB accesses +system.cpu.dtb.hits 62880856 # DTB hits +system.cpu.dtb.misses 80815 # DTB misses +system.cpu.dtb.accesses 62961671 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1008,8 +1005,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11524718 # ITB inst hits -system.cpu.itb.inst_misses 11477 # ITB inst misses +system.cpu.itb.inst_hits 11521970 # ITB inst hits +system.cpu.itb.inst_misses 11115 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1018,114 +1015,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2502 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2960 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11536195 # ITB inst accesses -system.cpu.itb.hits 11524718 # DTB hits -system.cpu.itb.misses 11477 # DTB misses -system.cpu.itb.accesses 11536195 # DTB accesses -system.cpu.numCycles 477111575 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533085 # ITB inst accesses +system.cpu.itb.hits 11521970 # DTB hits +system.cpu.itb.misses 11115 # DTB misses +system.cpu.itb.accesses 11533085 # DTB accesses +system.cpu.numCycles 477047952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29756603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90277136 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14743416 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9052947 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20141800 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4650225 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121200 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98195863 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2631 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87675 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2688966 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11518528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5147 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154198551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081572 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134072201 86.95% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1305405 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710070 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2294026 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2104673 1.36% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1102818 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555300 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746086 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307972 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154198551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030906 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189241 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31769851 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100064901 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18067338 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1262749 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3033712 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957542 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172175 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107250920 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3033712 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33504513 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38619180 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55176666 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17578446 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6286034 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102244327 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 450 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 980082 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063460 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 782 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106315700 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473686161 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432563323 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10440 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727135 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27588564 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170552 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1076872 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12591466 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19711121 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13300191 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1936389 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2436828 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95079446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983827 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122895781 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165904 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18895197 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47144933 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501515 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154198551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515893 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109876529 71.26% 71.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14361592 9.31% 80.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6875815 4.46% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5666847 3.68% 88.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12323021 7.99% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2802995 1.82% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1694666 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 469725 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127361 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154198551 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61834 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1153,436 +1150,437 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8368136 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413820 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57946622 47.15% 47.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52506141 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318913 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued -system.cpu.iq.rate 0.257621 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122895781 # Type of FU issued +system.cpu.iq.rate 0.257617 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8843793 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071962 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409057037 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 115975062 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85458771 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23247 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12478 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10297 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131698673 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12383 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624051 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4056444 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6518 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30236 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1568197 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34108054 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680529 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3033712 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30168583 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433803 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97285878 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203457 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19711121 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13300191 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411588 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3352 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30236 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349021 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270487 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619508 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120819447 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51867420 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2076334 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221300 # number of nop insts executed -system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed -system.cpu.iew.exec_branches 11821026 # Number of branches executed -system.cpu.iew.exec_stores 12211427 # Number of stores executed -system.cpu.iew.exec_rate 0.253266 # Inst execution rate -system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47016858 # num instructions producing a value -system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value +system.cpu.iew.exec_nop 222605 # number of nop insts executed +system.cpu.iew.exec_refs 64079545 # number of memory reference insts executed +system.cpu.iew.exec_branches 11817660 # Number of branches executed +system.cpu.iew.exec_stores 12212125 # Number of stores executed +system.cpu.iew.exec_rate 0.253265 # Inst execution rate +system.cpu.iew.wb_sent 119878750 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85469068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47006672 # num instructions producing a value +system.cpu.iew.wb_consumers 87538881 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179162 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536980 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18642428 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482312 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534972 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151164839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.491788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122735782 81.19% 81.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14630083 9.68% 90.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3890528 2.57% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132680 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1607271 1.06% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 973341 0.64% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1599818 1.06% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 715537 0.47% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2879799 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456535 # Number of instructions committed -system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151164839 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459531 # Number of instructions committed +system.cpu.commit.committedOps 77751027 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385855 # Number of memory references committed -system.cpu.commit.loads 15654083 # Number of loads committed -system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 10305769 # Number of branches committed +system.cpu.commit.refs 27386671 # Number of memory references committed +system.cpu.commit.loads 15654677 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 10306328 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69188185 # Number of committed integer instructions. -system.cpu.commit.function_calls 991209 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69191102 # Number of committed integer instructions. +system.cpu.commit.function_calls 991248 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2879799 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242914035 # The number of ROB reads -system.cpu.rob.rob_writes 195975439 # The number of ROB writes -system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60306154 # Number of Instructions Simulated -system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated -system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548607871 # number of integer regfile reads -system.cpu.int_regfile_writes 87541390 # number of integer regfile writes -system.cpu.fp_regfile_reads 8324 # number of floating regfile reads -system.cpu.fp_regfile_writes 2920 # number of floating regfile writes -system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.rob.rob_reads 242830080 # The number of ROB reads +system.cpu.rob.rob_writes 195907164 # The number of ROB writes +system.cpu.timesIdled 1776346 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322849401 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575122538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309150 # Number of Instructions Simulated +system.cpu.committedOps 77600646 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309150 # Number of Instructions Simulated +system.cpu.cpi 7.910043 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.910043 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548535745 # number of integer regfile reads +system.cpu.int_regfile_writes 87515632 # number of integer regfile writes +system.cpu.fp_regfile_reads 8349 # number of floating regfile reads +system.cpu.fp_regfile_writes 2926 # number of floating regfile writes +system.cpu.misc_regfile_reads 268179441 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173225 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58877700 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2957 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795840 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30059 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62784704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85494778 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 211580 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148531598 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148531598 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 200936 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128807668 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1475592252 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550083892 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19930988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74876053 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980909 # number of replacements -system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 981505 # number of replacements +system.cpu.icache.tags.tagsinuse 511.575357 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10456797 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 982017 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.648285 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6907075250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.575357 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999171 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999171 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits -system.cpu.icache.overall_hits::total 10459956 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses -system.cpu.icache.overall_misses::total 1061258 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11521214 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11521214 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11521214 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092113 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092113 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092113 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13453.040297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13453.040297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13453.040297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13453.040297 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6445 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12500448 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12500448 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10456797 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10456797 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10456797 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10456797 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10456797 # number of overall hits +system.cpu.icache.overall_hits::total 10456797 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061602 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061602 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061602 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061602 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061602 # number of overall misses +system.cpu.icache.overall_misses::total 1061602 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273209676 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14273209676 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14273209676 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14273209676 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14273209676 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14273209676 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518399 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518399 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518399 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518399 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092166 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092166 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092166 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092166 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092166 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092166 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13444.972481 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13444.972481 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13444.972481 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13444.972481 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13444.972481 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13444.972481 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6382 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 336 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 332 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.181548 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.222892 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79801 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79801 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79801 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79801 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79801 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79801 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981457 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981457 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981457 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981457 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981457 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981457 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11591245017 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11591245017 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11591245017 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11591245017 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11591245017 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11591245017 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79552 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79552 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79552 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79552 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79552 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79552 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982050 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 982050 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 982050 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 982050 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 982050 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 982050 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11590658741 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11590658741 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11590658741 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11590658741 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11590658741 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11590658741 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8870000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8870000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8870000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 8870000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085187 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085187 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085187 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085187 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.242341 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.242341 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.242341 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.242341 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085259 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085259 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085259 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085259 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085259 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085259 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11802.513865 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11802.513865 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11802.513865 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11802.513865 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11802.513865 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11802.513865 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64359 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51360.491961 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1887854 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129751 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.549822 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490800967500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36938.900442 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 39.947099 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 64371 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51367.805522 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1886658 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129763 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.539260 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490785434500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36937.207333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 28.555690 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8146.352593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.291454 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563643 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8169.178837 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6232.863288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563617 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60372.286571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61567.461912 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61477.131933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60372.286571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61567.461912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61477.131933 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1703,168 +1701,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643250 # number of replacements +system.cpu.dcache.tags.replacements 643213 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993295 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21507454 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643762 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.409015 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21506846 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643725 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.409990 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42602250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101513406 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101513406 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13755166 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13755166 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258873 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258873 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242710 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242710 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21014039 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21014039 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21014039 # number of overall hits -system.cpu.dcache.overall_hits::total 21014039 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963189 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963189 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13552 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13552 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 101509393 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101509393 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13753990 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753990 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259407 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259407 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242755 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242755 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # 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number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699504 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699504 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699504 # number of overall misses -system.cpu.dcache.overall_misses::total 3699504 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10015008577 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10015008577 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 140227660304 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 140227660304 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186052000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 186052000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 181002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 181002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 150242668881 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 150242668881 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 150242668881 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 150242668881 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14491481 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14491481 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222062 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222062 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24713543 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24713543 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24713543 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24713543 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050810 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050810 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289882 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289882 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052883 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3699136 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699136 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699136 # number of overall misses +system.cpu.dcache.overall_misses::total 3699136 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10001713308 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10001713308 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 140180267525 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 140180267525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184727500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184727500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150181980833 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150181980833 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150181980833 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150181980833 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14490311 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14490311 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222222 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222222 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256277 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256277 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24712533 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24712533 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24712533 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24712533 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050815 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289841 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289841 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052763 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149695 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149695 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149695 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149695 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13601.527304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13601.527304 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31857 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27549 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2688 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 281 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.851562 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.039146 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.149687 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149687 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149687 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149687 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13583.360121 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13583.360121 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47313.202993 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47313.202993 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13661.255731 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13661.255731 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40599.205012 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40599.205012 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40599.205012 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40599.205012 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30576 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27091 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2628 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 288 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.634703 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 94.065972 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607582 # number of writebacks -system.cpu.dcache.writebacks::total 607582 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350850 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350850 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714158 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714158 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1320 # 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number of writebacks +system.cpu.dcache.writebacks::total 607534 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350801 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350801 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713841 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713841 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064642 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064642 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064642 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064642 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385520 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385520 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248974 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248974 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634496 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634496 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634496 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634496 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4975619608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4975619608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323354786 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323354786 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146514250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146514250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 156998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 156998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16298974394 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16298974394 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16298974394 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16298974394 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328293250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328293250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26845365872 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26845365872 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209173659122 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209173659122 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024362 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024362 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047732 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 634494 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634494 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634494 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634494 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4971012627 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4971012627 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323926285 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323926285 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145258250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145258250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16294938912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16294938912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16294938912 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16294938912 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335926750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335926750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26847444003 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26847444003 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209183370753 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209183370753 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024356 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047558 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047558 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025675 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025675 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025675 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025675 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12894.305424 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12894.305424 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45482.364765 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45482.364765 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11918.136692 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11918.136692 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25681.785662 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25681.785662 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25681.785662 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1888,16 +1886,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499139103043 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499139103043 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499139103043 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 4ffbe6cb8..c90f786a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403670 # Number of seconds simulated -sim_ticks 2403669993000 # Number of ticks simulated -final_tick 2403669993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403672 # Number of seconds simulated +sim_ticks 2403671650000 # Number of ticks simulated +final_tick 2403671650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205695 # Simulator instruction rate (inst/s) -host_op_rate 264190 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8195476126 # Simulator tick rate (ticks/s) -host_mem_usage 425360 # Number of bytes of host memory used -host_seconds 293.29 # Real time elapsed on the host -sim_insts 60328724 # Number of instructions simulated -sim_ops 77484808 # Number of ops (including micro ops) simulated +host_inst_rate 179946 # Simulator instruction rate (inst/s) +host_op_rate 231118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7169234406 # Simulator tick rate (ticks/s) +host_mem_usage 425424 # Number of bytes of host memory used +host_seconds 335.28 # Real time elapsed on the host +sim_insts 60331512 # Number of instructions simulated +sim_ops 77488235 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7062488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7063576 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 676736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 184896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1338016 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 184896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 761928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3742720 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298604 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 64640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 678080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1335136 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 186240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743616 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298488 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1557912 # Number of bytes written to this memory -system.physmem.bytes_written::total 6758536 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558028 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759432 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14221 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110404 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1007 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10574 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20914 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512391 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58480 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324651 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20869 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512405 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324622 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812434 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768235 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 389507 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812448 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2938210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2938661 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 76922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 556655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51862028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 76922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557086 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 555457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51862365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540210 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768202 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3478469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3478871 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 76922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1204794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54673785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13478692 # Number of read requests accepted -system.physmem.writeReqs 446310 # Number of write requests accepted -system.physmem.readBursts 13478692 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446310 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 862636288 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 26892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1203644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54674493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13478771 # Number of read requests accepted +system.physmem.writeReqs 446331 # Number of write requests accepted +system.physmem.readBursts 13478771 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446331 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 862641344 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2859584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109811232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2805660 # Total written bytes from the system interface side +system.physmem.bytesWritten 2859200 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109811808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2805264 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401628 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2353 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 401653 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2355 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 837730 # Per bank write bursts -system.physmem.perBankRdBursts::1 837377 # Per bank write bursts -system.physmem.perBankRdBursts::2 837570 # Per bank write bursts -system.physmem.perBankRdBursts::3 838005 # Per bank write bursts -system.physmem.perBankRdBursts::4 839135 # Per bank write bursts -system.physmem.perBankRdBursts::5 839829 # Per bank write bursts -system.physmem.perBankRdBursts::6 839954 # Per bank write bursts -system.physmem.perBankRdBursts::7 841188 # Per bank write bursts -system.physmem.perBankRdBursts::8 842692 # Per bank write bursts -system.physmem.perBankRdBursts::9 845268 # Per bank write bursts -system.physmem.perBankRdBursts::10 845422 # Per bank write bursts -system.physmem.perBankRdBursts::11 845904 # Per bank write bursts -system.physmem.perBankRdBursts::12 847097 # Per bank write bursts -system.physmem.perBankRdBursts::13 848027 # Per bank write bursts -system.physmem.perBankRdBursts::14 846853 # Per bank write bursts -system.physmem.perBankRdBursts::15 846641 # Per bank write bursts -system.physmem.perBankWrBursts::0 2732 # Per bank write bursts -system.physmem.perBankWrBursts::1 2567 # Per bank write bursts -system.physmem.perBankWrBursts::2 2586 # Per bank write bursts -system.physmem.perBankWrBursts::3 3040 # Per bank write bursts -system.physmem.perBankWrBursts::4 3458 # Per bank write bursts -system.physmem.perBankWrBursts::5 3199 # Per bank write bursts -system.physmem.perBankWrBursts::6 2529 # Per bank write bursts -system.physmem.perBankWrBursts::7 2312 # Per bank write bursts -system.physmem.perBankWrBursts::8 2235 # Per bank write bursts -system.physmem.perBankWrBursts::9 2402 # Per bank write bursts -system.physmem.perBankWrBursts::10 2375 # Per bank write bursts -system.physmem.perBankWrBursts::11 2809 # Per bank write bursts -system.physmem.perBankWrBursts::12 3726 # Per bank write bursts -system.physmem.perBankWrBursts::13 3500 # Per bank write bursts -system.physmem.perBankWrBursts::14 2647 # Per bank write bursts -system.physmem.perBankWrBursts::15 2564 # Per bank write bursts +system.physmem.perBankRdBursts::1 837384 # Per bank write bursts +system.physmem.perBankRdBursts::2 837568 # Per bank write bursts +system.physmem.perBankRdBursts::3 837998 # Per bank write bursts +system.physmem.perBankRdBursts::4 839137 # Per bank write bursts +system.physmem.perBankRdBursts::5 839827 # Per bank write bursts +system.physmem.perBankRdBursts::6 839940 # Per bank write bursts +system.physmem.perBankRdBursts::7 841195 # Per bank write bursts +system.physmem.perBankRdBursts::8 842685 # Per bank write bursts +system.physmem.perBankRdBursts::9 845257 # Per bank write bursts +system.physmem.perBankRdBursts::10 845425 # Per bank write bursts +system.physmem.perBankRdBursts::11 845905 # Per bank write bursts +system.physmem.perBankRdBursts::12 847162 # Per bank write bursts +system.physmem.perBankRdBursts::13 848062 # Per bank write bursts +system.physmem.perBankRdBursts::14 846854 # Per bank write bursts +system.physmem.perBankRdBursts::15 846642 # Per bank write bursts +system.physmem.perBankWrBursts::0 2730 # Per bank write bursts +system.physmem.perBankWrBursts::1 2572 # Per bank write bursts +system.physmem.perBankWrBursts::2 2588 # Per bank write bursts +system.physmem.perBankWrBursts::3 3028 # Per bank write bursts +system.physmem.perBankWrBursts::4 3463 # Per bank write bursts +system.physmem.perBankWrBursts::5 3194 # Per bank write bursts +system.physmem.perBankWrBursts::6 2521 # Per bank write bursts +system.physmem.perBankWrBursts::7 2322 # Per bank write bursts +system.physmem.perBankWrBursts::8 2234 # Per bank write bursts +system.physmem.perBankWrBursts::9 2386 # Per bank write bursts +system.physmem.perBankWrBursts::10 2377 # Per bank write bursts +system.physmem.perBankWrBursts::11 2814 # Per bank write bursts +system.physmem.perBankWrBursts::12 3729 # Per bank write bursts +system.physmem.perBankWrBursts::13 3501 # Per bank write bursts +system.physmem.perBankWrBursts::14 2651 # Per bank write bursts +system.physmem.perBankWrBursts::15 2565 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402634752000 # Total gap between requests +system.physmem.totGap 2402635561500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13443296 # Read request sizes (log2) +system.physmem.readPktSize::3 13443376 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35388 # Read request sizes (log2) +system.physmem.readPktSize::6 35387 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429303 # Write request sizes (log2) +system.physmem.writePktSize::2 429332 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17007 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 975684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 953327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 947696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3279847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2361574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2361279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2377764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 51807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 17784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17747 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 16999 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 985231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 962596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 957159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3278666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2351782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2351346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2368287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 47071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 52789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,30 +178,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1989 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1969 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 1961 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -210,317 +210,337 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48746 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17755.207812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3162.737998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18340.275925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8642 17.73% 17.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4876 10.00% 27.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 980 2.01% 29.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 745 1.53% 31.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 418 0.86% 32.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 375 0.77% 32.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 281 0.58% 33.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 311 0.64% 34.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 181 0.37% 34.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 171 0.35% 34.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 151 0.31% 35.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 290 0.59% 35.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 88 0.18% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 76 0.16% 36.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 42 0.09% 36.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 366 0.75% 36.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 30 0.06% 36.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 31 0.06% 37.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 22 0.05% 37.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 117 0.24% 37.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 19 0.04% 37.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 158 0.32% 37.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 20 0.04% 37.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 128 0.26% 37.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 11 0.02% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 28 0.06% 38.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 10 0.02% 38.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 148 0.30% 38.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 9 0.02% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 16 0.03% 38.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 10 0.02% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 383 0.79% 39.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 7 0.01% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 5 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 66 0.14% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 1 0.00% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 3 0.01% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 4 0.01% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 69 0.14% 39.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 6 0.01% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 3 0.01% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 75 0.15% 39.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 2 0.00% 39.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 346 0.71% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 4 0.01% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 130 0.27% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 5 0.01% 40.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 2 0.00% 40.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 3 0.01% 40.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 69 0.14% 40.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 1 0.00% 40.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 8 0.02% 40.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 5 0.01% 40.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 77 0.16% 41.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 8 0.02% 41.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 4 0.01% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 6 0.01% 41.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 331 0.68% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 3 0.01% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 5 0.01% 41.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 190 0.39% 42.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 12 0.02% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 4 0.01% 42.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.01% 42.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 36 0.07% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 4 0.01% 42.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 4 0.01% 42.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 136 0.28% 42.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 1 0.00% 42.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 2 0.00% 42.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 260 0.53% 43.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 43.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 3 0.01% 43.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 4 0.01% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 67 0.14% 43.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 3 0.01% 43.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 2 0.00% 43.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 4 0.01% 43.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 1 0.00% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 324 0.66% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 6 0.01% 44.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 4 0.01% 44.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.01% 44.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 5 0.01% 44.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 69 0.14% 44.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 2 0.00% 44.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 7 0.01% 44.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 1 0.00% 44.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 3 0.01% 44.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 3 0.01% 44.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 44.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 295 0.61% 45.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 2 0.00% 45.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 10 0.02% 45.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 1 0.00% 45.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 539 1.11% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 1 0.00% 46.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 294 0.60% 47.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 1 0.00% 47.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 65 0.13% 47.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 64 0.13% 48.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 129 0.26% 49.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 31 0.06% 49.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 181 0.37% 49.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 323 0.66% 50.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 64 0.13% 50.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 50.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 126 0.26% 51.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 51.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 342 0.70% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 68 0.14% 51.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 65 0.13% 52.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 52.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 368 0.75% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 90 0.18% 53.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 84 0.17% 53.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 265 0.54% 54.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 64 0.13% 54.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 70 0.14% 54.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 644 1.32% 55.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 70 0.14% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 65 0.13% 56.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 266 0.55% 56.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 82 0.17% 56.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 88 0.18% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 127 0.26% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 370 0.76% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 65 0.13% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 69 0.14% 58.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 339 0.70% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 125 0.26% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 64 0.13% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 70 0.14% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 325 0.67% 60.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 182 0.37% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 30 0.06% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 127 0.26% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.53% 61.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 61.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 65 0.13% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 64 0.13% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 65 0.13% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 320 0.66% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 66 0.14% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 292 0.60% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 1 0.00% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 129 0.26% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 538 1.10% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 129 0.26% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 292 0.60% 65.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 65 0.13% 65.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 64 0.13% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 257 0.53% 67.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 128 0.26% 67.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 67.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 31 0.06% 67.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 182 0.37% 67.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 324 0.66% 68.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 69 0.14% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 64 0.13% 68.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 126 0.26% 69.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 341 0.70% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 69 0.14% 69.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 70.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 368 0.75% 70.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 128 0.26% 71.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 71.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 88 0.18% 71.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 82 0.17% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 1 0.00% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 266 0.55% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 69 0.14% 72.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 69 0.14% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 265 0.54% 74.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 74.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 82 0.17% 74.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34240-34247 1 0.00% 74.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 88 0.18% 74.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 1 0.00% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 367 0.75% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34880-34887 1 0.00% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 69 0.14% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 341 0.70% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 126 0.26% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 69 0.14% 77.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 323 0.66% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 182 0.37% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 31 0.06% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 1 0.00% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 129 0.26% 78.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 64 0.13% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 129 0.26% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 537 1.10% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 129 0.26% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 293 0.60% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 66 0.14% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 64 0.13% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 1 0.00% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 255 0.52% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 2 0.00% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 127 0.26% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 30 0.06% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 181 0.37% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 323 0.66% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 69 0.14% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 338 0.69% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 70 0.14% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 65 0.13% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 369 0.76% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 127 0.26% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 90 0.18% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 82 0.17% 89.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 266 0.55% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 69 0.14% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 2 0.00% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4685 9.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48746 # Bytes accessed per row activation -system.physmem.totQLat 326451020750 # Total ticks spent queuing -system.physmem.totMemAccLat 407972275750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67393460000 # Total ticks spent in databus transfers -system.physmem.totBankLat 14127795000 # Total ticks spent accessing banks -system.physmem.avgQLat 24219.78 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1048.16 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 48736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17758.945502 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3164.892038 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18326.287457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8690 17.83% 17.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4827 9.90% 27.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 1035 2.12% 29.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 694 1.42% 31.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 398 0.82% 32.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 429 0.88% 32.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 259 0.53% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 302 0.62% 34.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 176 0.36% 34.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 149 0.31% 34.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 171 0.35% 35.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 272 0.56% 35.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 78 0.16% 35.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 84 0.17% 36.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 41 0.08% 36.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 422 0.87% 36.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 26 0.05% 37.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 34 0.07% 37.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 22 0.05% 37.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 232 0.48% 37.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 28 0.06% 37.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 166 0.34% 38.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 13 0.03% 38.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 104 0.21% 38.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 12 0.02% 38.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 32 0.07% 38.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 7 0.01% 38.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 80 0.16% 38.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 11 0.02% 38.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 7 0.01% 38.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 239 0.49% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 4 0.01% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 11 0.02% 39.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 7 0.01% 39.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 71 0.15% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 4 0.01% 39.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 5 0.01% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 72 0.15% 39.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 1 0.00% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 3 0.01% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 2 0.00% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 6 0.01% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.01% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 360 0.74% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 3 0.01% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 3 0.01% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 2 0.00% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 69 0.14% 40.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 40.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 8 0.02% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 5 0.01% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 67 0.14% 40.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 5 0.01% 40.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 9 0.02% 40.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 4 0.01% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 338 0.69% 41.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 3 0.01% 41.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 5 0.01% 41.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 70 0.14% 41.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 13 0.03% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 5 0.01% 41.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 41.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 72 0.15% 41.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 1 0.00% 41.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 5 0.01% 41.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 3 0.01% 41.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 64 0.13% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 3 0.01% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 3 0.01% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 280 0.57% 42.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 2 0.00% 42.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 73 0.15% 42.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 4 0.01% 42.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 4 0.01% 42.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 1 0.00% 42.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 129 0.26% 43.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 2 0.00% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 4 0.01% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 176 0.36% 43.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 1 0.00% 43.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 327 0.67% 44.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 5 0.01% 44.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 7 0.01% 44.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 98 0.20% 44.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 1 0.00% 44.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 1 0.00% 44.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 73 0.15% 44.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 4 0.01% 44.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 8 0.02% 44.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 2 0.00% 44.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 60 0.12% 44.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 5 0.01% 44.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 268 0.55% 45.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 1 0.00% 45.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 7 0.01% 45.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 66 0.14% 45.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 45.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 64 0.13% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 42 0.09% 45.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 2 0.00% 45.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 515 1.06% 46.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 42 0.09% 46.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 66 0.14% 46.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 65 0.13% 46.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 267 0.55% 47.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 59 0.12% 47.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 69 0.14% 47.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 94 0.19% 47.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 322 0.66% 48.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 138 0.28% 48.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 128 0.26% 49.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 70 0.14% 49.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 279 0.57% 49.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 60 0.12% 50.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 1 0.00% 50.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 64 0.13% 50.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 65 0.13% 50.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 328 0.67% 50.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 63 0.13% 51.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12615 1 0.00% 51.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 64 0.13% 51.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 64 0.13% 51.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 357 0.73% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 65 0.13% 52.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 52.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 52.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 229 0.47% 52.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 64 0.13% 52.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 64 0.13% 53.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 190 0.39% 53.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 321 0.66% 54.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 65 0.13% 54.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 64 0.13% 54.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 672 1.38% 55.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 64 0.13% 55.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 64 0.13% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 321 0.66% 56.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 189 0.39% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 65 0.13% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 64 0.13% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 229 0.47% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 64 0.13% 57.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 63 0.13% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 357 0.73% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 65 0.13% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 64 0.13% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 1 0.00% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 327 0.67% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 64 0.13% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 61 0.13% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 274 0.56% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 69 0.14% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 128 0.26% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 137 0.28% 61.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 323 0.66% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 93 0.19% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 68 0.14% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 57 0.12% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 268 0.55% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 65 0.13% 63.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 65 0.13% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 43 0.09% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 514 1.05% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 42 0.09% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 66 0.14% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 64 0.13% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25408-25415 1 0.00% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 1 0.00% 64.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 264 0.54% 65.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 57 0.12% 65.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 69 0.14% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 95 0.19% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 323 0.66% 66.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 1 0.00% 66.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 137 0.28% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 1 0.00% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 127 0.26% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 68 0.14% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 275 0.56% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 61 0.13% 68.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 64 0.13% 68.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 65 0.13% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 329 0.68% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 65 0.13% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 64 0.13% 69.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 64 0.13% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 356 0.73% 70.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 65 0.13% 70.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 228 0.47% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 64 0.13% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 64 0.13% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 189 0.39% 71.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 321 0.66% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 63 0.13% 72.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 64 0.13% 72.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 673 1.38% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 64 0.13% 73.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 321 0.66% 74.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 189 0.39% 75.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 64 0.13% 75.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 65 0.13% 75.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 229 0.47% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 65 0.13% 76.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 356 0.73% 76.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.13% 76.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 329 0.68% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 65 0.13% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 61 0.13% 78.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 276 0.57% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 68 0.14% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 127 0.26% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 137 0.28% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 322 0.66% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 94 0.19% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 69 0.14% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 57 0.12% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 264 0.54% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40128-40135 1 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 64 0.13% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 65 0.13% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 42 0.09% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 513 1.05% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 43 0.09% 82.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 65 0.13% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 266 0.55% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 57 0.12% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 68 0.14% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 93 0.19% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 323 0.66% 84.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 137 0.28% 84.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 128 0.26% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 69 0.14% 85.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 274 0.56% 85.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 61 0.13% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 86.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 64 0.13% 86.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 86.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 327 0.67% 86.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 64 0.13% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 64 0.13% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 64 0.13% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 356 0.73% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 63 0.13% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 228 0.47% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 64 0.13% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 65 0.13% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 190 0.39% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 322 0.66% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 64 0.13% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4701 9.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48736 # Bytes accessed per row activation +system.physmem.totQLat 326317088000 # Total ticks spent queuing +system.physmem.totMemAccLat 407972525500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67393855000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14261582500 # Total ticks spent accessing banks +system.physmem.avgQLat 24209.71 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1058.08 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30267.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30267.78 # Average memory access latency per DRAM burst system.physmem.avgRdBW 358.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.38 # Average write queue length when enqueuing -system.physmem.readRowHits 13435238 # Number of row buffer hits during reads -system.physmem.writeRowHits 39389 # Number of row buffer hits during writes +system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing +system.physmem.readRowHits 13435330 # Number of row buffer hits during reads +system.physmem.writeRowHits 39380 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.15 # Row buffer hit rate for writes -system.physmem.avgGap 172541.07 # Average gap between requests +system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes +system.physmem.avgGap 172539.89 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.88 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 0.87 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -533,322 +553,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55671057 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13813895 # Transaction distribution -system.membus.trans_dist::ReadResp 13813895 # Transaction distribution -system.membus.trans_dist::WriteReq 432143 # Transaction distribution -system.membus.trans_dist::WriteResp 432143 # Transaction distribution -system.membus.trans_dist::Writeback 17007 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2353 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2353 # Transaction distribution -system.membus.trans_dist::ReadExReq 27827 # Transaction distribution -system.membus.trans_dist::ReadExResp 27827 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731520 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951111 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1682851 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886592 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26886592 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28569443 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070524 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5806364 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107546368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107546368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113352732 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133814850 # Total data (bytes) +system.membus.throughput 55671828 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13814146 # Transaction distribution +system.membus.trans_dist::ReadResp 13814146 # Transaction distribution +system.membus.trans_dist::WriteReq 432166 # Transaction distribution +system.membus.trans_dist::WriteResp 432166 # Transaction distribution +system.membus.trans_dist::Writeback 16999 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2355 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2355 # Transaction distribution +system.membus.trans_dist::ReadExReq 27802 # Transaction distribution +system.membus.trans_dist::ReadExResp 27802 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731808 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951163 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1683185 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26886752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28569937 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735681 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5806173 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107547008 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107547008 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113353181 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133816795 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416796500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416936000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 205000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 202000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14608293500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14607946000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1594356888 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1594364889 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30359701500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30360976750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63223 # number of replacements -system.l2c.tags.tagsinuse 50383.450720 # Cycle average of tags in use -system.l2c.tags.total_refs 1749716 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128619 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.603869 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375590593500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36838.052028 # Average occupied blocks per requestor +system.l2c.tags.replacements 63237 # number of replacements +system.l2c.tags.tagsinuse 50379.569066 # Cycle average of tags in use +system.l2c.tags.total_refs 1749643 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128631 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.602032 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375594870500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36839.610574 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5233.374732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3836.748090 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 504.839969 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 688.402361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.761256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1676.159647 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1594.119177 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562104 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5231.934240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3832.971184 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 504.116293 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 687.425497 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.900489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1683.581513 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1591.035818 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562128 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058544 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079833 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058486 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007703 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010504 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000164 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025576 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024324 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768790 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65391 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.007692 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010489 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025689 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024277 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768731 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65392 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55892 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997787 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17682479 # Number of tag accesses -system.l2c.tags.data_accesses 17682479 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8678 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3134 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 467928 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 176815 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2613 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1177 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 128266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64331 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4179 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 283323 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 132022 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291084 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597612 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62965.181460 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63158.110353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63201.136854 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63083.660876 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59571.534653 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63097.346862 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63649.226804 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62962.898924 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62965.181460 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1001,52 +1021,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58820773 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1019834 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1019833 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432143 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432143 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265318 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1491 # Transaction distribution +system.toL2Bus.throughput 58818769 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1020134 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1020133 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432166 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432166 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265053 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1493 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80420 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80420 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831638 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419538 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15322 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3318402 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26591040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37381340 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84972 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64078776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141286926 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 98800 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2177097249 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80260 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80260 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831165 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419053 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15627 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52402 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3318247 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26575552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37346205 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85644 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64029309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141280603 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100404 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176001251 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1873558443 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872526171 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1846163669 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1845075146 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9980966 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10168460 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30796222 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31121231 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762593 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13806282 # Transaction distribution -system.iobus.trans_dist::ReadResp 13806282 # Transaction distribution -system.iobus.trans_dist::WriteReq 2774 # Transaction distribution -system.iobus.trans_dist::WriteResp 2774 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762623 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13806510 # Transaction distribution +system.iobus.trans_dist::ReadResp 13806510 # Transaction distribution +system.iobus.trans_dist::WriteReq 2770 # Transaction distribution +system.iobus.trans_dist::WriteResp 2770 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11390 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3024 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716528 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716834 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1062,18 +1082,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731520 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886592 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26886592 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27618112 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26886752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27618560 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15354 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713159 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1089,18 +1109,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107546368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107546368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108281768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209182 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 735681 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107547008 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107547008 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108282689 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209335 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7953000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 1512000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 128000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1108,7 +1128,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358766000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358920000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1140,11 +1160,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443296000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13443376000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 728746000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 729038000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36856311500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36855449250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1169,25 +1189,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7990923 # DTB read hits -system.cpu0.dtb.read_misses 6211 # DTB read misses -system.cpu0.dtb.write_hits 6594140 # DTB write hits -system.cpu0.dtb.write_misses 1982 # DTB write misses +system.cpu0.dtb.read_hits 7998897 # DTB read hits +system.cpu0.dtb.read_misses 6203 # DTB read misses +system.cpu0.dtb.write_hits 6598042 # DTB write hits +system.cpu0.dtb.write_misses 1992 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5674 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5672 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 122 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7997134 # DTB read accesses -system.cpu0.dtb.write_accesses 6596122 # DTB write accesses +system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8005100 # DTB read accesses +system.cpu0.dtb.write_accesses 6600034 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14585063 # DTB hits -system.cpu0.dtb.misses 8193 # DTB misses -system.cpu0.dtb.accesses 14593256 # DTB accesses +system.cpu0.dtb.hits 14596939 # DTB hits +system.cpu0.dtb.misses 8195 # DTB misses +system.cpu0.dtb.accesses 14605134 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1209,433 +1229,433 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32307309 # ITB inst hits -system.cpu0.itb.inst_misses 3464 # ITB inst misses +system.cpu0.itb.inst_hits 32342389 # ITB inst hits +system.cpu0.itb.inst_misses 3452 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2638 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32310773 # ITB inst accesses -system.cpu0.itb.hits 32307309 # DTB hits -system.cpu0.itb.misses 3464 # DTB misses -system.cpu0.itb.accesses 32310773 # DTB accesses -system.cpu0.numCycles 113705948 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32345841 # ITB inst accesses +system.cpu0.itb.hits 32342389 # DTB hits +system.cpu0.itb.misses 3452 # DTB misses +system.cpu0.itb.accesses 32345841 # DTB accesses +system.cpu0.numCycles 113704712 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31835702 # Number of instructions committed -system.cpu0.committedOps 42002663 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37391372 # Number of integer alu accesses +system.cpu0.committedInsts 31867189 # Number of instructions committed +system.cpu0.committedOps 42038889 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37421309 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1198329 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4242666 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37391372 # number of integer instructions +system.cpu0.num_func_calls 1198994 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4247035 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37421309 # number of integer instructions system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193815032 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39491762 # number of times the integer registers were written +system.cpu0.num_int_register_reads 193973220 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39529492 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15252645 # number of memory refs -system.cpu0.num_load_insts 8359351 # Number of load instructions -system.cpu0.num_store_insts 6893294 # Number of store instructions -system.cpu0.num_idle_cycles 111019314.623883 # Number of idle cycles -system.cpu0.num_busy_cycles 2686633.376117 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023628 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976372 # Percentage of idle cycles -system.cpu0.Branches 5610345 # Number of branches fetched +system.cpu0.num_mem_refs 15264742 # number of memory refs +system.cpu0.num_load_insts 8367651 # Number of load instructions +system.cpu0.num_store_insts 6897091 # Number of store instructions +system.cpu0.num_idle_cycles 111017320.581957 # Number of idle cycles +system.cpu0.num_busy_cycles 2687391.418043 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023635 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976365 # Percentage of idle cycles +system.cpu0.Branches 5615714 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891892 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.603893 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43639057 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892404 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.900562 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8180676250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.451765 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.618297 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.533831 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967679 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014879 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.016668 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 891676 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602493 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43661110 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892188 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.937119 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8187850250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.418624 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.559512 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.624357 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967615 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014765 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.016844 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45447878 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45447878 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31833706 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8062582 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3742769 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43639057 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31833706 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8062582 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3742769 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43639057 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31833706 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8062582 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3742769 # number of overall hits -system.cpu0.icache.overall_hits::total 43639057 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476257 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129542 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 310613 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916412 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476257 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129542 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 310613 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916412 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 476257 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129542 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 310613 # number of overall misses -system.cpu0.icache.overall_misses::total 916412 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1750680500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4190164618 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5940845118 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1750680500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4190164618 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5940845118 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1750680500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4190164618 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5940845118 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32309963 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8192124 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4053382 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44555469 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32309963 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8192124 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4053382 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44555469 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32309963 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8192124 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4053382 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44555469 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014740 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015813 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076631 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020568 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014740 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015813 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076631 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020568 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014740 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015813 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076631 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020568 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.385296 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13489.984701 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6482.722965 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13514.385296 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13489.984701 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6482.722965 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13514.385296 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13489.984701 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6482.722965 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4056 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 45469557 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 45469557 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31868764 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8050810 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3741536 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43661110 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31868764 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8050810 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3741536 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43661110 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31868764 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8050810 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3741536 # number of overall hits +system.cpu0.icache.overall_hits::total 43661110 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 476273 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 130180 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 309800 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916253 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 476273 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 130180 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 309800 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916253 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 476273 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 130180 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 309800 # number of overall misses +system.cpu0.icache.overall_misses::total 916253 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1759106250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4179473576 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5938579826 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1759106250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4179473576 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5938579826 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1759106250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4179473576 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5938579826 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32345037 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8180990 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4051336 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44577363 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32345037 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8180990 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4051336 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44577363 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32345037 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8180990 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4051336 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44577363 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014725 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015912 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076469 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020554 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014725 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015912 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076469 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13512.876402 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13490.876617 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6481.375587 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4072 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 221 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.588832 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.425339 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11890.991766 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.818028 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24058 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24058 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24058 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24058 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24058 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24058 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130180 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285742 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 415922 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 130180 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 285742 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 415922 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 130180 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 285742 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 415922 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1498352750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3400846060 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4899198810 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1498352750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3400846060 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4899198810 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1498352750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3400846060 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4899198810 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009330 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009330 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009330 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.128803 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.128803 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.128803 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629794 # number of replacements +system.cpu0.dcache.tags.replacements 629840 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23221016 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630306 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.840861 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23225212 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630352 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.844830 # 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Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015816 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013335 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 98822314 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 98822314 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6860309 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1818197 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4643556 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13322062 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5962720 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1310571 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2137098 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9410389 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131686 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33079 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73392 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238157 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138288 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34722 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74384 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247394 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13167902 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3221029 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7661595 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24050526 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13167902 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3221029 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7661595 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24050526 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 13179582 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3221577 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7650427 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24051586 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13179582 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3221577 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7650427 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24051586 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025130 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033845 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055262 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037021 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033890 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055130 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027407 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021334 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221859 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078885 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046638 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050327 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048365 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021347 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221342 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078646 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046743 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050400 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.047987 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047634 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28553530500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55951926500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442155991 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13334829583 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14776985574 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840551991 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41888360083 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70728912074 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033845 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026708 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014093 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021334 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019411 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008015 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050327 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043165 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020321 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1740534513 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3558356592 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5298891105 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1740534513 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3558356592 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5298891105 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27401033000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28573458500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55974491500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439106494 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13338859363 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14777965857 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840139494 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41912317863 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70752457357 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033890 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026711 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014085 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019372 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007999 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050400 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042835 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020198 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011511 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011511 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12252.233405 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12964.262413 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12731.654924 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33550.229725 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35063.744813 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34535.653208 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11126.782658 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11539.351457 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11397.038764 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011500 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011500 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12243.190982 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12953.629541 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12721.257134 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33545.252524 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35021.679843 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34504.582515 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11154.428571 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11522.720691 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.119976 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1669,25 +1689,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2095173 # DTB read hits -system.cpu1.dtb.read_misses 2089 # DTB read misses -system.cpu1.dtb.write_hits 1414657 # DTB write hits -system.cpu1.dtb.write_misses 374 # DTB write misses +system.cpu1.dtb.read_hits 2093956 # DTB read hits +system.cpu1.dtb.read_misses 2077 # DTB read misses +system.cpu1.dtb.write_hits 1416211 # DTB write hits +system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1771 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1760 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2097262 # DTB read accesses -system.cpu1.dtb.write_accesses 1415031 # DTB write accesses +system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2096033 # DTB read accesses +system.cpu1.dtb.write_accesses 1416584 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3509830 # DTB hits -system.cpu1.dtb.misses 2463 # DTB misses -system.cpu1.dtb.accesses 3512293 # DTB accesses +system.cpu1.dtb.hits 3510167 # DTB hits +system.cpu1.dtb.misses 2450 # DTB misses +system.cpu1.dtb.accesses 3512617 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1709,61 +1729,61 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8192124 # ITB inst hits -system.cpu1.itb.inst_misses 1194 # ITB inst misses +system.cpu1.itb.inst_hits 8180990 # ITB inst hits +system.cpu1.itb.inst_misses 1185 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 944 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8193318 # ITB inst accesses -system.cpu1.itb.hits 8192124 # DTB hits -system.cpu1.itb.misses 1194 # DTB misses -system.cpu1.itb.accesses 8193318 # DTB accesses -system.cpu1.numCycles 581420474 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8182175 # ITB inst accesses +system.cpu1.itb.hits 8180990 # DTB hits +system.cpu1.itb.misses 1185 # DTB misses +system.cpu1.itb.accesses 8182175 # DTB accesses +system.cpu1.numCycles 581419148 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7979382 # Number of instructions committed -system.cpu1.committedOps 10120569 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9091581 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1987 # Number of float alu accesses -system.cpu1.num_func_calls 304296 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1113753 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9091581 # number of integer instructions -system.cpu1.num_fp_insts 1987 # number of float instructions -system.cpu1.num_int_register_reads 53006739 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9888017 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1409 # number of times the floating registers were read +system.cpu1.committedInsts 7970398 # Number of instructions committed +system.cpu1.committedOps 10116193 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9089557 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses +system.cpu1.num_func_calls 304010 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1112792 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9089557 # number of integer instructions +system.cpu1.num_fp_insts 2019 # number of float instructions +system.cpu1.num_int_register_reads 52989642 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9881584 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3676771 # number of memory refs -system.cpu1.num_load_insts 2188618 # Number of load instructions -system.cpu1.num_store_insts 1488153 # Number of store instructions -system.cpu1.num_idle_cycles 545340562.414449 # Number of idle cycles -system.cpu1.num_busy_cycles 36079911.585551 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062055 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937945 # Percentage of idle cycles -system.cpu1.Branches 1446360 # Number of branches fetched +system.cpu1.num_mem_refs 3676962 # number of memory refs +system.cpu1.num_load_insts 2186992 # Number of load instructions +system.cpu1.num_store_insts 1489970 # Number of store instructions +system.cpu1.num_idle_cycles 545339727.510646 # Number of idle cycles +system.cpu1.num_busy_cycles 36079420.489354 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062054 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937946 # Percentage of idle cycles +system.cpu1.Branches 1445114 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4789734 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3907352 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223904 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3178605 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2529099 # Number of BTB hits +system.cpu2.branchPred.lookups 4780240 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3898194 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223690 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3180058 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2524004 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.566319 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413607 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21727 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.369747 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 414035 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21682 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1787,25 +1807,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10928591 # DTB read hits -system.cpu2.dtb.read_misses 22863 # DTB read misses -system.cpu2.dtb.write_hits 3355192 # DTB write hits -system.cpu2.dtb.write_misses 6501 # DTB write misses +system.cpu2.dtb.read_hits 10926394 # DTB read hits +system.cpu2.dtb.read_misses 23081 # DTB read misses +system.cpu2.dtb.write_hits 3349602 # DTB write hits +system.cpu2.dtb.write_misses 6536 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2326 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 747 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 728 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 164 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 464 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10951454 # DTB read accesses -system.cpu2.dtb.write_accesses 3361693 # DTB write accesses +system.cpu2.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10949475 # DTB read accesses +system.cpu2.dtb.write_accesses 3356138 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14283783 # DTB hits -system.cpu2.dtb.misses 29364 # DTB misses -system.cpu2.dtb.accesses 14313147 # DTB accesses +system.cpu2.dtb.hits 14275996 # DTB hits +system.cpu2.dtb.misses 29617 # DTB misses +system.cpu2.dtb.accesses 14305613 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1827,294 +1847,294 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4054873 # ITB inst hits -system.cpu2.itb.inst_misses 4512 # ITB inst misses +system.cpu2.itb.inst_hits 4052754 # ITB inst hits +system.cpu2.itb.inst_misses 4681 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1691 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1722 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1038 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 963 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4059385 # ITB inst accesses -system.cpu2.itb.hits 4054873 # DTB hits -system.cpu2.itb.misses 4512 # DTB misses -system.cpu2.itb.accesses 4059385 # DTB accesses -system.cpu2.numCycles 88337048 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4057435 # ITB inst accesses +system.cpu2.itb.hits 4052754 # DTB hits +system.cpu2.itb.misses 4681 # DTB misses +system.cpu2.itb.accesses 4057435 # DTB accesses +system.cpu2.numCycles 88329548 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9388767 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32522302 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4789734 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2942706 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6862489 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1760464 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 49990 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19168441 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 508 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 916 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33389 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 724944 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 411 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4053387 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 290500 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37439208 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.044253 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431681 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9368286 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32480016 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4780240 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2938039 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6853051 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1759446 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50956 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19165610 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 867 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33412 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 724302 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4051341 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 290206 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37405927 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.043731 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431289 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30581596 81.68% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385766 1.03% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516570 1.38% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819401 2.19% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 630355 1.68% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341667 0.91% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1045652 2.79% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 230362 0.62% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2887839 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30558019 81.69% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385772 1.03% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 515915 1.38% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819609 2.19% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 625256 1.67% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 342326 0.92% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1044683 2.79% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 230213 0.62% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2884134 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37439208 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054221 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368162 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10012366 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19744012 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6199418 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 325352 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1157163 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 610165 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53442 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36995280 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180745 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1157163 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10561732 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6812365 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11427981 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5960297 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1518769 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34903210 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 326244 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 883069 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37436972 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 161085942 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148506742 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3418 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26572380 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10864591 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285670 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261929 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3326002 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6631520 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3908381 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 522508 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 782143 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32221978 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 504989 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34786596 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55958 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7182504 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19112764 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148353 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37439208 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.929149 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.590514 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37405927 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054118 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367714 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9993670 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19739606 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6190224 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 324742 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1156786 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609493 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53173 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36942390 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178785 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1156786 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10542033 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6802518 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11433975 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5951508 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1518203 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34853467 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 325261 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 883658 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 140 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37388012 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 160878048 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148313673 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3357 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26544776 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10843235 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285604 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261905 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3322163 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6624625 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3901879 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530898 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 772979 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32179363 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 501455 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34749523 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55329 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7166724 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19100923 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 145150 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37405927 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.928984 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.590317 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24741126 66.08% 66.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3984374 10.64% 76.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2311240 6.17% 82.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1973818 5.27% 88.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2779235 7.42% 95.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 969976 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 499460 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 145124 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34855 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24720555 66.09% 66.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3979487 10.64% 76.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2312001 6.18% 82.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1968335 5.26% 88.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2779247 7.43% 95.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 968566 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 497905 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144867 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34964 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37439208 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37405927 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19410 1.27% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1392857 91.45% 92.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110885 7.28% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19427 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1392100 91.45% 92.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110700 7.27% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8329 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19813633 56.96% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28024 0.08% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11412307 32.81% 89.87% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3523902 10.13% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8337 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19784762 56.94% 56.96% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28044 0.08% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.04% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11409832 32.83% 89.88% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3518152 10.12% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34786596 # Type of FU issued -system.cpu2.iq.rate 0.393794 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1523153 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043786 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108613127 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39914727 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28091280 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7607 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3993 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3398 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36297355 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4065 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206023 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34749523 # Type of FU issued +system.cpu2.iq.rate 0.393408 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1522228 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043806 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108504523 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39852721 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28051848 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7496 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3959 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3344 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36259410 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4004 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206643 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1534437 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2089 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9566 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 563640 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1533647 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2027 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9444 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562515 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5283023 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 345372 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5286265 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344866 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1157163 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5185391 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88081 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32809694 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61016 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6631520 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3908381 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362677 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29698 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2464 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9566 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107529 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89869 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197398 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33871170 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11141481 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 915426 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1156786 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5177746 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 87629 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32763326 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61736 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6624625 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3901879 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 359192 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29253 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2415 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9444 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107780 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89787 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197567 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33835206 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11139307 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 914317 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82727 # number of nop insts executed -system.cpu2.iew.exec_refs 14631897 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3767155 # Number of branches executed -system.cpu2.iew.exec_stores 3490416 # Number of stores executed -system.cpu2.iew.exec_rate 0.383431 # Inst execution rate -system.cpu2.iew.wb_sent 33470061 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28094678 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16123172 # num instructions producing a value -system.cpu2.iew.wb_consumers 29138246 # num instructions consuming a value +system.cpu2.iew.exec_nop 82508 # number of nop insts executed +system.cpu2.iew.exec_refs 14623996 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3761047 # Number of branches executed +system.cpu2.iew.exec_stores 3484689 # Number of stores executed +system.cpu2.iew.exec_rate 0.383056 # Inst execution rate +system.cpu2.iew.wb_sent 33433924 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28055192 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16098734 # num instructions producing a value +system.cpu2.iew.wb_consumers 29085804 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.318040 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553334 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317620 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553491 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7139947 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356636 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171258 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36281839 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700541 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.737980 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7134883 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356305 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171320 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36248935 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700393 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.738300 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27358624 75.41% 75.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4439139 12.24% 87.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1255970 3.46% 91.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 641270 1.77% 92.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 512644 1.41% 94.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317320 0.87% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 419851 1.16% 96.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 310411 0.86% 97.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1026610 2.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27340525 75.42% 75.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4430140 12.22% 87.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1255420 3.46% 91.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 637620 1.76% 92.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 510981 1.41% 94.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317875 0.88% 95.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 419132 1.16% 96.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311355 0.86% 97.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1025887 2.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36281839 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20568992 # Number of instructions committed -system.cpu2.commit.committedOps 25416928 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36248935 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20549284 # Number of instructions committed +system.cpu2.commit.committedOps 25388512 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8441824 # Number of memory references committed -system.cpu2.commit.loads 5097083 # Number of loads committed -system.cpu2.commit.membars 94345 # Number of memory barriers committed -system.cpu2.commit.branches 3244670 # Number of branches committed -system.cpu2.commit.fp_insts 3331 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22669662 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295973 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1026610 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8430342 # Number of memory references committed +system.cpu2.commit.loads 5090978 # Number of loads committed +system.cpu2.commit.membars 94231 # Number of memory barriers committed +system.cpu2.commit.branches 3241086 # Number of branches committed +system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22644563 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295800 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1025887 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67290844 # The number of ROB reads -system.cpu2.rob.rob_writes 66314967 # The number of ROB writes -system.cpu2.timesIdled 359753 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50897840 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3553970695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20513640 # Number of Instructions Simulated -system.cpu2.committedOps 25361576 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20513640 # Number of Instructions Simulated -system.cpu2.cpi 4.306259 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.306259 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232220 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232220 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157179181 # number of integer regfile reads -system.cpu2.int_regfile_writes 29907517 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46919 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes -system.cpu2.misc_regfile_reads 66774204 # number of misc regfile reads -system.cpu2.misc_regfile_writes 297147 # number of misc regfile writes +system.cpu2.rob.rob_reads 67225559 # The number of ROB reads +system.cpu2.rob.rob_writes 66247729 # The number of ROB writes +system.cpu2.timesIdled 359329 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50923621 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3554004914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20493925 # Number of Instructions Simulated +system.cpu2.committedOps 25333153 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20493925 # Number of Instructions Simulated +system.cpu2.cpi 4.310036 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.310036 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232017 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232017 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157011420 # number of integer regfile reads +system.cpu2.int_regfile_writes 29864331 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46835 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes +system.cpu2.misc_regfile_reads 66864323 # number of misc regfile reads +system.cpu2.misc_regfile_writes 296992 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2131,10 +2151,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1347815916500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1347815916500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1347826044250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1347826044250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 7a8eccd80..1944dbbec 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,156 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550461 # Number of seconds simulated -sim_ticks 2550460850000 # Number of ticks simulated -final_tick 2550460850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550456 # Number of seconds simulated +sim_ticks 2550455693500 # Number of ticks simulated +final_tick 2550455693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71467 # Simulator instruction rate (inst/s) -host_op_rate 91959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3022122690 # Simulator tick rate (ticks/s) -host_mem_usage 427404 # Number of bytes of host memory used -host_seconds 843.93 # Real time elapsed on the host -sim_insts 60313440 # Number of instructions simulated -sim_ops 77607116 # Number of ops (including micro ops) simulated +host_inst_rate 59744 # Simulator instruction rate (inst/s) +host_op_rate 76873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2526372396 # Simulator tick rate (ticks/s) +host_mem_usage 427472 # Number of bytes of host memory used +host_seconds 1009.53 # Real time elapsed on the host +sim_insts 60313472 # Number of instructions simulated +sim_ops 77606209 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 504512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5067800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 293824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4027288 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 504512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 293824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786560 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494656 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802660 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 504320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5079000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 295488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4015064 # Number of bytes read from this memory +system.physmem.bytes_read::total 131007536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 504320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 295488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1520720 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1495380 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802468 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4591 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 62932 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59165 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380361 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373664 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813190 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47485743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7880 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 62741 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293498 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59162 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380180 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373845 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47485839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 853 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1987013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1579043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51365970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47485743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1991409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1574254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51366325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484585 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596254 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586319 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47485839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 853 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2583550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2165077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54033198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293488 # Number of read requests accepted -system.physmem.writeReqs 813190 # Number of write requests accepted -system.physmem.readBursts 15293488 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813190 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978237376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 545856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6910336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131006896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6802660 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8529 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705216 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4690 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955874 # Per bank write bursts -system.physmem.perBankRdBursts::1 955460 # Per bank write bursts -system.physmem.perBankRdBursts::2 954683 # Per bank write bursts -system.physmem.perBankRdBursts::3 954757 # Per bank write bursts -system.physmem.perBankRdBursts::4 955767 # Per bank write bursts -system.physmem.perBankRdBursts::5 955952 # Per bank write bursts -system.physmem.perBankRdBursts::6 954810 # Per bank write bursts -system.physmem.perBankRdBursts::7 954709 # Per bank write bursts -system.physmem.perBankRdBursts::8 956270 # Per bank write bursts -system.physmem.perBankRdBursts::9 955934 # Per bank write bursts -system.physmem.perBankRdBursts::10 954560 # Per bank write bursts -system.physmem.perBankRdBursts::11 953973 # Per bank write bursts -system.physmem.perBankRdBursts::12 956221 # Per bank write bursts -system.physmem.perBankRdBursts::13 955978 # Per bank write bursts -system.physmem.perBankRdBursts::14 955151 # Per bank write bursts -system.physmem.perBankRdBursts::15 954860 # Per bank write bursts -system.physmem.perBankWrBursts::0 6693 # Per bank write bursts -system.physmem.perBankWrBursts::1 6460 # Per bank write bursts -system.physmem.perBankWrBursts::2 6602 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6566 # Per bank write bursts -system.physmem.perBankWrBursts::5 6824 # Per bank write bursts -system.physmem.perBankWrBursts::6 6825 # Per bank write bursts -system.physmem.perBankWrBursts::7 6757 # Per bank write bursts -system.physmem.perBankWrBursts::8 7131 # Per bank write bursts -system.physmem.perBankWrBursts::9 6880 # Per bank write bursts -system.physmem.perBankWrBursts::10 6546 # Per bank write bursts -system.physmem.perBankWrBursts::11 6195 # Per bank write bursts -system.physmem.perBankWrBursts::12 7145 # Per bank write bursts -system.physmem.perBankWrBursts::13 6763 # Per bank write bursts -system.physmem.perBankWrBursts::14 7046 # Per bank write bursts -system.physmem.perBankWrBursts::15 6906 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 197737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2587663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 115857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2160572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54033483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293498 # Number of read requests accepted +system.physmem.writeReqs 813187 # Number of write requests accepted +system.physmem.readBursts 15293498 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813187 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978241024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 542848 # Total number of bytes read from write queue +system.physmem.bytesWritten 6911808 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131007536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6802468 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8482 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705190 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955869 # Per bank write bursts +system.physmem.perBankRdBursts::1 955539 # Per bank write bursts +system.physmem.perBankRdBursts::2 954667 # Per bank write bursts +system.physmem.perBankRdBursts::3 954789 # Per bank write bursts +system.physmem.perBankRdBursts::4 955759 # Per bank write bursts +system.physmem.perBankRdBursts::5 955951 # Per bank write bursts +system.physmem.perBankRdBursts::6 954859 # Per bank write bursts +system.physmem.perBankRdBursts::7 954668 # Per bank write bursts +system.physmem.perBankRdBursts::8 956272 # Per bank write bursts +system.physmem.perBankRdBursts::9 955769 # Per bank write bursts +system.physmem.perBankRdBursts::10 954516 # Per bank write bursts +system.physmem.perBankRdBursts::11 954114 # Per bank write bursts +system.physmem.perBankRdBursts::12 956222 # Per bank write bursts +system.physmem.perBankRdBursts::13 955973 # Per bank write bursts +system.physmem.perBankRdBursts::14 955087 # Per bank write bursts +system.physmem.perBankRdBursts::15 954962 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6466 # Per bank write bursts +system.physmem.perBankWrBursts::2 6605 # Per bank write bursts +system.physmem.perBankWrBursts::3 6628 # Per bank write bursts +system.physmem.perBankWrBursts::4 6579 # Per bank write bursts +system.physmem.perBankWrBursts::5 6834 # Per bank write bursts +system.physmem.perBankWrBursts::6 6823 # Per bank write bursts +system.physmem.perBankWrBursts::7 6763 # Per bank write bursts +system.physmem.perBankWrBursts::8 7134 # Per bank write bursts +system.physmem.perBankWrBursts::9 6882 # Per bank write bursts +system.physmem.perBankWrBursts::10 6543 # Per bank write bursts +system.physmem.perBankWrBursts::11 6191 # Per bank write bursts +system.physmem.perBankWrBursts::12 7147 # Per bank write bursts +system.physmem.perBankWrBursts::13 6760 # Per bank write bursts +system.physmem.perBankWrBursts::14 7044 # Per bank write bursts +system.physmem.perBankWrBursts::15 6911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550459728500 # Total gap between requests +system.physmem.totGap 2550454486000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 44 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154628 # Read request sizes (log2) +system.physmem.readPktSize::6 154638 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59165 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1189211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1129031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1083368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3689725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2647408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2642045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2653706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59162 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1113468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1067801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3688063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2661485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2656312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2669345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see @@ -165,31 +173,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5216 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 5378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4744 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 4738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -197,394 +205,389 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86806 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11348.833952 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1015.155739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16835.722240 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23589 27.17% 27.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14167 16.32% 43.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2667 3.07% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2091 2.41% 48.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1355 1.56% 50.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1138 1.31% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 864 1.00% 52.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1120 1.29% 54.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 549 0.63% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 610 0.70% 55.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 512 0.59% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 456 0.53% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 243 0.28% 56.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 296 0.34% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 156 0.18% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 592 0.68% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 118 0.14% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 142 0.16% 58.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 67 0.08% 58.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 249 0.29% 58.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 529 0.61% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 292 0.34% 59.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 23 0.03% 59.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 99 0.11% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 19 0.02% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 187 0.22% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 47 0.05% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 18 0.02% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 308 0.35% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 8 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 37 0.04% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 15 0.02% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 167 0.19% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 29 0.03% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 15 0.02% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 19 0.02% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 10 0.01% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 208 0.24% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 29 0.03% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 407 0.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 12 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 20 0.02% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 80 0.09% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 13 0.01% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 84 0.10% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 19 0.02% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 9 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 152 0.18% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 349 0.40% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 12 0.01% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 10 0.01% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 13 0.01% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 21 0.02% 62.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 11 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11341.188281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1014.168764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16824.493217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23628 27.20% 27.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14156 16.30% 43.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2700 3.11% 46.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2166 2.49% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1318 1.52% 50.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1170 1.35% 51.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 896 1.03% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 913 1.05% 54.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 566 0.65% 54.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 606 0.70% 55.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 521 0.60% 55.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 631 0.73% 56.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 271 0.31% 57.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 267 0.31% 57.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 590 0.68% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 110 0.13% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 147 0.17% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 73 0.08% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 151 0.17% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 55 0.06% 58.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 532 0.61% 59.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 32 0.04% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 226 0.26% 59.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 59.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 114 0.13% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 25 0.03% 59.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 112 0.13% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 26 0.03% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 51 0.06% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 19 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 424 0.49% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 10 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 29 0.03% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 12 0.01% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 47 0.05% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 15 0.02% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 23 0.03% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 12 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 153 0.18% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 13 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 30 0.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 14 0.02% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 22 0.03% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 8 0.01% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 344 0.40% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 8 0.01% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 12 0.01% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 150 0.17% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 12 0.01% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 8 0.01% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 14 0.02% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 136 0.16% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.01% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 13 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 10 0.01% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 83 0.10% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 470 0.54% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 13 0.01% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 83 0.10% 62.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 13 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 10 0.01% 62.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4551 11 0.01% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 184 0.21% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 10 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 12 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 8 0.01% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 12 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 273 0.31% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 208 0.24% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 7 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 73 0.08% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 5 0.01% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 17 0.02% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 138 0.16% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.01% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 5 0.01% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 459 0.53% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 4 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 9 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 12 0.01% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 19 0.02% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 4 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 133 0.15% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 6 0.01% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 4 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 263 0.30% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 14 0.02% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 26 0.03% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 188 0.22% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 3 0.00% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 68 0.08% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 5 0.01% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 2 0.00% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 64 0.07% 66.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 184 0.21% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 4 0.00% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 261 0.30% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 128 0.15% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 2 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 3 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 4 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 451 0.52% 67.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 63 0.07% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 194 0.22% 67.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 67.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 259 0.30% 68.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 167 0.19% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 5 0.01% 68.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 322 0.37% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 135 0.16% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 67 0.08% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 55 0.06% 69.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 384 0.44% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 185 0.21% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13767 1 0.00% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 6 0.01% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 126 0.15% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 259 0.30% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 129 0.15% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 129 0.15% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 1 0.00% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 124 0.14% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 385 0.44% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 3 0.00% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 129 0.15% 71.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 67 0.08% 71.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 642 0.74% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16455 1 0.00% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 65 0.07% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 128 0.15% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 384 0.44% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 1 0.00% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 123 0.14% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 129 0.15% 72.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 129 0.15% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 261 0.30% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 126 0.15% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 6 0.01% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 183 0.21% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19264-19271 2 0.00% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 55 0.06% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 67 0.08% 74.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 132 0.15% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 322 0.37% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 6 0.01% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 169 0.19% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 3 0.00% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.29% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 63 0.07% 75.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 64 0.07% 75.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 449 0.52% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 5 0.01% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 3 0.00% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 129 0.15% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 259 0.30% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23623 1 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 4 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 184 0.21% 76.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 1 0.00% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 497 0.57% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 65 0.07% 77.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 186 0.21% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 4 0.00% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 259 0.30% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 130 0.15% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 2 0.00% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 6 0.01% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 449 0.52% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 64 0.07% 78.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 61 0.07% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 194 0.22% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 258 0.30% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 167 0.19% 79.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 5 0.01% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 321 0.37% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 130 0.15% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 66 0.08% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 1 0.00% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 54 0.06% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 384 0.44% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 186 0.21% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 7 0.01% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 127 0.15% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 260 0.30% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 130 0.15% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 128 0.15% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31431 1 0.00% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 123 0.14% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 3 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 65 0.07% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 128 0.15% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 3 0.00% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 123 0.14% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 128 0.15% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 130 0.15% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 260 0.30% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 20 0.02% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 11 0.01% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 7 0.01% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 8 0.01% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 151 0.17% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 397 0.46% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 3 0.00% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 13 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 7 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 18 0.02% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 13 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 10 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 76 0.09% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 6 0.01% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 11 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 208 0.24% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 5 0.01% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 13 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 7 0.01% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 368 0.42% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 3 0.00% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 4 0.00% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 73 0.08% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 137 0.16% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 10 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 24 0.03% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 2 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 60 0.07% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 5 0.01% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 270 0.31% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 5 0.01% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 10 0.01% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 9 0.01% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 215 0.25% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 8 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 21 0.02% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 7 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 8 0.01% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 69 0.08% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 6 0.01% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 602 0.69% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 67 0.08% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 2 0.00% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 203 0.23% 66.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 262 0.30% 66.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9287 1 0.00% 66.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 56 0.06% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 129 0.15% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 354 0.41% 67.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 132 0.15% 67.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 66 0.08% 67.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 2 0.00% 67.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 377 0.43% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 143 0.16% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 1 0.00% 68.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 65 0.07% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 444 0.51% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 65 0.07% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 120 0.14% 69.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 129 0.15% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 321 0.37% 69.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 4 0.00% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 137 0.16% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 5 0.01% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 1 0.00% 69.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 69.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 386 0.44% 70.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 64 0.07% 70.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 71 0.08% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 56 0.06% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 386 0.44% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 121 0.14% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 5 0.01% 71.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 125 0.14% 71.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 641 0.74% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16455 1 0.00% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 125 0.14% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 7 0.01% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 120 0.14% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17223 1 0.00% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 386 0.44% 72.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 54 0.06% 72.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 71 0.08% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 65 0.07% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 384 0.44% 73.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 5 0.01% 73.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 132 0.15% 73.57% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 203 0.23% 76.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 2 0.00% 76.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 76.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 67 0.08% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 495 0.57% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 66 0.08% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 2 0.00% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 204 0.23% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 262 0.30% 78.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 56 0.06% 78.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 129 0.15% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 67 0.08% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 355 0.41% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 1 0.00% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 131 0.15% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 64 0.07% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27335 2 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 3 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 377 0.43% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 143 0.16% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 65 0.07% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 441 0.51% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 65 0.07% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 119 0.14% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 128 0.15% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 321 0.37% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 6 0.01% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 134 0.15% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 4 0.00% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 385 0.44% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 66 0.08% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 71 0.08% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 2 0.00% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 54 0.06% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 385 0.44% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 120 0.14% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 4 0.00% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 124 0.14% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 640 0.74% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 124 0.14% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 4 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 121 0.14% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 386 0.44% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 54 0.06% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 71 0.08% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 66 0.08% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 384 0.44% 84.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::35008-35015 1 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 126 0.15% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 8 0.01% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35520-35527 1 0.00% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 185 0.21% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 384 0.44% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 55 0.06% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 67 0.08% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 130 0.15% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 321 0.37% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 5 0.01% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 165 0.19% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 258 0.30% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 194 0.22% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 60 0.07% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 64 0.07% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 449 0.52% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 5 0.01% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 3 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 128 0.15% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 4 0.00% 88.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 186 0.21% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 65 0.07% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 498 0.57% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 183 0.21% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41671 1 0.00% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 4 0.00% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 258 0.30% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 128 0.15% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 4 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 450 0.52% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 65 0.07% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 59 0.07% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 195 0.22% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 257 0.30% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 2 0.00% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 2 0.00% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 168 0.19% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 1 0.00% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 6 0.01% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 2 0.00% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 327 0.38% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 67 0.08% 91.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 55 0.06% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 386 0.44% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 185 0.21% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 6 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 126 0.15% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 260 0.30% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 129 0.15% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 130 0.15% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 122 0.14% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 386 0.44% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 129 0.15% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 65 0.07% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 2 0.00% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 4 0.00% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 134 0.15% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 5 0.01% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35776-35783 1 0.00% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 321 0.37% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 128 0.15% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 120 0.14% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 65 0.07% 85.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 441 0.51% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 1 0.00% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 143 0.16% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37760-37767 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 377 0.43% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 1 0.00% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38208-38215 1 0.00% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 64 0.07% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38464-38471 1 0.00% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 130 0.15% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 355 0.41% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 66 0.08% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 128 0.15% 87.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 55 0.06% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 261 0.30% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40007 1 0.00% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 203 0.23% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 66 0.08% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 496 0.57% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 67 0.08% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 2 0.00% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 203 0.23% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 1 0.00% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 260 0.30% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 55 0.06% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 1 0.00% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 128 0.15% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 67 0.08% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 1 0.00% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 353 0.41% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 131 0.15% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 65 0.07% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 379 0.44% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 143 0.16% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 2 0.00% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 67 0.08% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 443 0.51% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 67 0.08% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 122 0.14% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 1 0.00% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 130 0.15% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 322 0.37% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 4 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 131 0.15% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 5 0.01% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 384 0.44% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 64 0.07% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 72 0.08% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 54 0.06% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 385 0.44% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 121 0.14% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48583 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 5 0.01% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 123 0.14% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 93.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5210 6.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5211 6.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50112-50119 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86806 # Bytes accessed per row activation -system.physmem.totQLat 369546937250 # Total ticks spent queuing -system.physmem.totMemAccLat 463545387250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76424795000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17573655000 # Total ticks spent accessing banks -system.physmem.avgQLat 24177.16 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1149.74 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51648-51655 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86865 # Bytes accessed per row activation +system.physmem.totQLat 369784547000 # Total ticks spent queuing +system.physmem.totMemAccLat 463560559500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76425080000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17350932500 # Total ticks spent accessing banks +system.physmem.avgQLat 24192.62 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1135.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30326.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30327.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -594,324 +597,293 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15213019 # Number of row buffer hits during reads -system.physmem.writeRowHits 93108 # Number of row buffer hits during writes +system.physmem.readRowHits 15213014 # Number of row buffer hits during reads +system.physmem.writeRowHits 93134 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.23 # Row buffer hit rate for writes -system.physmem.avgGap 158347.97 # Average gap between requests +system.physmem.writeRowHitRate 86.24 # Row buffer hit rate for writes +system.physmem.avgGap 158347.57 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.65 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54973413 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346095 # Transaction distribution -system.membus.trans_dist::ReadResp 16346098 # Transaction distribution -system.membus.trans_dist::WriteReq 763348 # Transaction distribution -system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59165 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4689 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4690 # Transaction distribution -system.membus.trans_dist::ReadExReq 131440 # Transaction distribution -system.membus.trans_dist::ReadExResp 131440 # Transaction distribution +system.membus.throughput 54973753 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346163 # Transaction distribution +system.membus.trans_dist::ReadResp 16346166 # Transaction distribution +system.membus.trans_dist::WriteReq 763365 # Transaction distribution +system.membus.trans_dist::WriteResp 763365 # Transaction distribution +system.membus.trans_dist::Writeback 59162 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4696 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution +system.membus.trans_dist::ReadExReq 131412 # Transaction distribution +system.membus.trans_dist::ReadExResp 131412 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272814 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550323 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550446 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699028 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19097009 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699476 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19097594 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140207537 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140207537 # Total data (bytes) +system.membus.tot_pkt_size::total 140208122 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140208122 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487746500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487391000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3584500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17566438500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566049500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4736460824 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736056592 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34185683234 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34187486731 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64398 # number of replacements -system.l2c.tags.tagsinuse 51440.737713 # Cycle average of tags in use -system.l2c.tags.total_refs 1904463 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129791 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.673306 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2513095359500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36974.659237 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.382027 # Average occupied blocks per requestor +system.l2c.tags.replacements 64408 # number of replacements +system.l2c.tags.tagsinuse 51449.796153 # Cycle average of tags in use +system.l2c.tags.total_refs 1905827 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129798 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.683023 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2540137710500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36969.006628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.725284 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4864.361052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3325.264959 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.733963 # 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mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015066 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.243278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000413 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009854 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.202531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091592 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001025 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.243106 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000452 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000142 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009800 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.202770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091672 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.243278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000413 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009854 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.202531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091592 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62413.381583 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65404.248069 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61895.307716 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61881.625160 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65121.037138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62041.944348 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.871418 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.715168 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62155.866596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61603.993250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61909.751342 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.537692 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.686706 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62421.351588 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61492.320361 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62008.251199 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62379.214261 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61744.106312 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62013.232366 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60132.375676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62379.214261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62489.278752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61744.106312 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62013.232366 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1114,49 +1066,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58420424 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676760 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676762 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 607936 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246118 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246118 # Transaction distribution +system.toL2Bus.throughput 58427801 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677013 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677015 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 607832 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2962 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246108 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246108 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796874 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149966 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952482 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62939648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85542385 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254948 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148791853 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148791853 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 207152 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4962468234 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968942 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796822 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 150646 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7954400 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62968576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85534266 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 258652 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148817782 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148817782 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 199736 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4962135725 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4433875230 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4435783766 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4484319469 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4484209498 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23911393 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23967895 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86679578 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86426354 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48422959 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution -system.iobus.trans_dist::WriteReq 8160 # Transaction distribution -system.iobus.trans_dist::WriteResp 8160 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48423111 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution +system.iobus.trans_dist::WriteReq 8177 # Transaction distribution +system.iobus.trans_dist::WriteResp 8177 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1178,12 +1130,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1205,14 +1157,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500861 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500998 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1258,19 +1210,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41495326766 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41493951269 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7528776 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6012881 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377531 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4829761 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3930404 # Number of BTB hits +system.cpu0.branchPred.lookups 7524637 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6008547 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377377 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4829480 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3929632 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.378851 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 724348 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39225 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.367601 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 723615 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39097 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1294,25 +1246,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25731693 # DTB read hits -system.cpu0.dtb.read_misses 40178 # DTB read misses -system.cpu0.dtb.write_hits 6168711 # DTB write hits -system.cpu0.dtb.write_misses 10337 # DTB write misses +system.cpu0.dtb.read_hits 25732063 # DTB read hits +system.cpu0.dtb.read_misses 40060 # DTB read misses +system.cpu0.dtb.write_hits 6173955 # DTB write hits +system.cpu0.dtb.write_misses 10391 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5677 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1369 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5654 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 265 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25771871 # DTB read accesses -system.cpu0.dtb.write_accesses 6179048 # DTB write accesses +system.cpu0.dtb.perms_faults 665 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25772123 # DTB read accesses +system.cpu0.dtb.write_accesses 6184346 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31900404 # DTB hits -system.cpu0.dtb.misses 50515 # DTB misses -system.cpu0.dtb.accesses 31950919 # DTB accesses +system.cpu0.dtb.hits 31906018 # DTB hits +system.cpu0.dtb.misses 50451 # DTB misses +system.cpu0.dtb.accesses 31956469 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1334,664 +1286,664 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5899860 # ITB inst hits -system.cpu0.itb.inst_misses 7207 # ITB inst misses +system.cpu0.itb.inst_hits 5897367 # ITB inst hits +system.cpu0.itb.inst_misses 7084 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2688 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2660 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1562 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1482 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5907067 # ITB inst accesses -system.cpu0.itb.hits 5899860 # DTB hits -system.cpu0.itb.misses 7207 # DTB misses -system.cpu0.itb.accesses 5907067 # DTB accesses -system.cpu0.numCycles 242297109 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5904451 # ITB inst accesses +system.cpu0.itb.hits 5897367 # DTB hits +system.cpu0.itb.misses 7084 # DTB misses +system.cpu0.itb.accesses 5904451 # DTB accesses +system.cpu0.numCycles 242280954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15555542 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45617593 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7528776 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4654752 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10311247 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2439507 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 83051 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50330649 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2002 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 48587 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1491133 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 722 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5897866 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368478 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3041 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79507031 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722707 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.070799 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15560897 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45618983 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7524637 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4653247 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10311307 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2438027 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 82681 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50295736 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2004 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 47904 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1479659 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 328 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5895435 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368728 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79463748 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.723138 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.071375 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69202528 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 678265 0.85% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 875305 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1177307 1.48% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1118218 1.41% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 557082 0.70% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1282023 1.61% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 381348 0.48% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4234955 5.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69159455 87.03% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 678650 0.85% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 874708 1.10% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1176149 1.48% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1117399 1.41% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558232 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1283192 1.61% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 380865 0.48% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4235098 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79507031 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031072 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.188271 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16656471 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51363244 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9231902 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 659908 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1593273 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1005882 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91811 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54700033 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 305616 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1593273 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17552192 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20324540 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27741870 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8932000 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3360998 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52127379 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 375 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 510306 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2174045 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 221 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53799249 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241745694 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 220537236 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5112 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39397526 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14401722 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 594296 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 542687 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6992906 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10039494 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6994522 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1049493 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1384753 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48432856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1029992 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62172633 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89012 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9963233 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24631985 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 276940 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79507031 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.781977 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.500620 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79463748 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031057 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.188290 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16659746 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51317609 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9233971 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 657554 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1592691 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1005769 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91409 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54704033 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 304298 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1592691 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17554490 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20340792 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27693159 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8932278 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3348216 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52126479 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 377 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 497478 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2175969 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 155 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53794326 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241736924 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 220533984 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5031 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39400219 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14394106 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 593139 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 541531 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6973197 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10037020 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7000202 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1050357 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1288163 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48430994 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1028168 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62176930 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89712 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9957065 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24599714 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 276838 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79463748 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.782457 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.501316 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56951176 71.63% 71.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7375765 9.28% 80.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3517120 4.42% 85.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2922983 3.68% 89.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6158188 7.75% 96.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1492282 1.88% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 793715 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 229189 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66613 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56925517 71.64% 71.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7350450 9.25% 80.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3522799 4.43% 85.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2913274 3.67% 88.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6168473 7.76% 96.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1495817 1.88% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 789992 0.99% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231277 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66149 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79507031 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79463748 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30271 0.68% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4195541 94.33% 95.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221720 4.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30568 0.69% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4194749 94.30% 94.98% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 223174 5.02% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15963 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29223949 47.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47621 0.08% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1246 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26409062 42.48% 89.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6474770 10.41% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15922 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29222200 47.00% 47.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47810 0.08% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1242 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26409099 42.47% 89.58% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6480639 10.42% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62172633 # Type of FU issued -system.cpu0.iq.rate 0.256597 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4447534 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071535 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208427694 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59435167 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43384407 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11467 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6219 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5237 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66598153 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6051 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 313701 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62176930 # Type of FU issued +system.cpu0.iq.rate 0.256632 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4448493 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071546 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208394864 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59425365 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43388237 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11204 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6101 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5139 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66603600 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5901 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 313863 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2134408 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15882 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 849708 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2132926 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15826 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 851086 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17067409 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348218 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17067174 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 347980 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1593273 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15683016 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239861 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49569735 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107283 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10039494 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6994522 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 730989 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55378 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15882 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184147 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145491 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 329638 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61106002 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26080146 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1066631 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1592691 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15703960 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239689 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49567887 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107700 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10037020 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7000202 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 730031 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54998 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4795 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15826 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184371 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145167 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 329538 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61108768 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26079506 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1068162 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 106887 # number of nop insts executed -system.cpu0.iew.exec_refs 32497006 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5987699 # Number of branches executed -system.cpu0.iew.exec_stores 6416860 # Number of stores executed -system.cpu0.iew.exec_rate 0.252195 # Inst execution rate -system.cpu0.iew.wb_sent 60612995 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43389644 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23417175 # num instructions producing a value -system.cpu0.iew.wb_consumers 43060015 # num instructions consuming a value +system.cpu0.iew.exec_nop 108725 # number of nop insts executed +system.cpu0.iew.exec_refs 32501673 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5985971 # Number of branches executed +system.cpu0.iew.exec_stores 6422167 # Number of stores executed +system.cpu0.iew.exec_rate 0.252223 # Inst execution rate +system.cpu0.iew.wb_sent 60615706 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43393376 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23422073 # num instructions producing a value +system.cpu0.iew.wb_consumers 43067972 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.179076 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543826 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.179104 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543840 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9791777 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 753052 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 287149 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77913758 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.504003 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.469415 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9785974 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 751330 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 287324 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77871057 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.504327 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472133 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63454715 81.44% 81.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7423327 9.53% 90.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1988141 2.55% 93.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1098394 1.41% 94.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 861624 1.11% 96.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 581195 0.75% 96.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 738806 0.95% 97.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 351756 0.45% 98.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1415800 1.82% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63445664 81.48% 81.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7408180 9.51% 90.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1965702 2.52% 93.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1101219 1.41% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 850042 1.09% 96.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 579839 0.74% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 741280 0.95% 97.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 350840 0.45% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1428291 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77913758 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30063645 # Number of instructions committed -system.cpu0.commit.committedOps 39268790 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77871057 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30068673 # Number of instructions committed +system.cpu0.commit.committedOps 39272492 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14049900 # Number of memory references committed -system.cpu0.commit.loads 7905086 # Number of loads committed -system.cpu0.commit.membars 209983 # Number of memory barriers committed -system.cpu0.commit.branches 5182251 # Number of branches committed -system.cpu0.commit.fp_insts 5199 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34974968 # Number of committed integer instructions. -system.cpu0.commit.function_calls 508855 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1415800 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14053210 # 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Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29991762 # Number of Instructions Simulated -system.cpu0.committedOps 39196907 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29991762 # Number of Instructions Simulated -system.cpu0.cpi 8.078789 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.078789 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123781 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123781 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 277582728 # number of integer regfile reads -system.cpu0.int_regfile_writes 44079568 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44948 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42562 # number of floating regfile writes -system.cpu0.misc_regfile_reads 138472263 # number of misc regfile reads -system.cpu0.misc_regfile_writes 583698 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983976 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.534971 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10503842 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984488 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.669345 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7011386250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.535325 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.999646 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620186 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378906 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999092 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124525442 # The number of ROB reads +system.cpu0.rob.rob_writes 99752707 # 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number of floating regfile reads +system.cpu0.fp_regfile_writes 42488 # number of floating regfile writes +system.cpu0.misc_regfile_reads 138395505 # number of misc regfile reads +system.cpu0.misc_regfile_writes 582325 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984398 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.534546 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10515921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984910 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.677037 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7008829000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 316.868268 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.666278 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.618883 # 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number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 507875 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065712 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 557837 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 507875 # number of overall misses -system.cpu0.icache.overall_misses::total 1065712 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7709624467 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6833167274 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14542791741 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7709624467 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6833167274 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14542791741 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7709624467 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6833167274 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14542791741 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5897743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5671811 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11569554 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5897743 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5671811 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11569554 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5897743 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5671811 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5686445 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11581755 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5895310 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5686445 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11581755 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094666 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089291 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092027 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094666 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089291 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092027 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11837809961 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6271733613 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5566076348 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11837809961 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6271733613 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5566076348 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11837809961 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8638250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8638250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8638250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 8638250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085095 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085095 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087393 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082705 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085095 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12010.000889 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.517382 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11850.110095 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12010.000889 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087491 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082504 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085042 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087491 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082504 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085042 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087491 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082504 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085042 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12159.612576 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.045674 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12018.825492 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12159.612576 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.045674 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12018.825492 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12159.612576 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.045674 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12018.825492 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643555 # number of replacements +system.cpu0.dcache.tags.replacements 643530 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.993287 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21527522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644067 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.424352 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21531295 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644042 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.431508 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43200250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.501132 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.492155 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500979 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499008 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.568714 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 254.424573 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503064 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.496923 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101636995 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101636995 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7028225 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6743962 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13772187 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3755786 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3505627 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261413 # 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number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1987963 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1722242 # number of overall misses +system.cpu0.dcache.overall_misses::total 3710205 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5452544877 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5973510192 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11426055069 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85021863209 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64469772613 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 149491635822 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 108104498 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79946495 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 188050993 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 78000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 116501 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89990745047 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 70766386337 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 160757131384 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89990745047 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 70766386337 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 160757131384 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127597 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247653 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12767027 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11976847 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24743874 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12767027 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11976847 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24743874 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046023 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057197 # miss rate for ReadReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16804462881 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527132501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90809770250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336902751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13691854278 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13083150967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26775005245 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 141500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 141500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105221034522 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103878551972 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209099586494 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025543 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027639 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026576 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023406 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054282 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040929 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047428 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000033 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105218986779 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103892921217 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209111907996 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025563 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027602 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023377 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054402 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040743 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025657 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025657 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13954.086330 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13285.710326 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13611.653829 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47027.142187 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45575.250598 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46368.672796 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12619.397523 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11614.686445 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12174.353840 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025419 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025902 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13933.898543 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13286.722972 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.612056 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47179.018143 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45492.118665 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46415.738360 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12622.287317 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11506.045192 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12128.292757 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12562.375000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27891.681728 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24982.400005 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26470.223994 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2006,15 +1958,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7298811 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5882879 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 344498 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4442454 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3749763 # Number of BTB hits +system.cpu1.branchPred.lookups 7303181 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5881126 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 346154 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4653929 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3750959 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.407469 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 676814 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34330 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 80.597684 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 679679 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34597 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2038,25 +1990,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25485052 # DTB read hits -system.cpu1.dtb.read_misses 36401 # DTB read misses -system.cpu1.dtb.write_hits 5542090 # DTB write hits -system.cpu1.dtb.write_misses 8345 # DTB write misses +system.cpu1.dtb.read_hits 25488049 # DTB read hits +system.cpu1.dtb.read_misses 36227 # DTB read misses +system.cpu1.dtb.write_hits 5538132 # DTB write hits +system.cpu1.dtb.write_misses 8320 # DTB write misses system.cpu1.dtb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5452 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1278 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25521453 # DTB read accesses -system.cpu1.dtb.write_accesses 5550435 # DTB write accesses +system.cpu1.dtb.perms_faults 677 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25524276 # DTB read accesses +system.cpu1.dtb.write_accesses 5546452 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31027142 # DTB hits -system.cpu1.dtb.misses 44746 # DTB misses -system.cpu1.dtb.accesses 31071888 # DTB accesses +system.cpu1.dtb.hits 31026181 # DTB hits +system.cpu1.dtb.misses 44547 # DTB misses +system.cpu1.dtb.accesses 31070728 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2078,124 +2030,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5673835 # ITB inst hits -system.cpu1.itb.inst_misses 6882 # ITB inst misses +system.cpu1.itb.inst_hits 5688452 # ITB inst hits +system.cpu1.itb.inst_misses 7006 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2658 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2704 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1447 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1448 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5680717 # ITB inst accesses -system.cpu1.itb.hits 5673835 # DTB hits -system.cpu1.itb.misses 6882 # DTB misses -system.cpu1.itb.accesses 5680717 # DTB accesses -system.cpu1.numCycles 236975623 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5695458 # ITB inst accesses +system.cpu1.itb.hits 5688452 # DTB hits +system.cpu1.itb.misses 7006 # DTB misses +system.cpu1.itb.accesses 5695458 # DTB accesses +system.cpu1.numCycles 236990378 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14429172 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45037398 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7298811 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4426577 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9907364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2282600 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82705 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49394158 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1073 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 44118 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1230431 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5671812 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352198 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3013 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76664255 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.724522 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076690 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14445279 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45031495 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7303181 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4430638 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9912685 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2288075 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 85272 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49385810 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1038 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1883 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 43903 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1235955 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5686448 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352687 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3068 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76688585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.724367 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076407 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66765211 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 630389 0.82% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 841220 1.10% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1125492 1.47% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 998152 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 547084 0.71% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1279264 1.67% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 367549 0.48% 94.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4109894 5.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66784675 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 633491 0.83% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 843387 1.10% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1127901 1.47% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 993338 1.30% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 549443 0.72% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1277588 1.67% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 369483 0.48% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4109279 5.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76664255 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030800 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190051 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15533095 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50132740 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8857878 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 647971 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1490380 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 961231 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85259 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 52933701 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 285543 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1490380 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16375879 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19322833 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27622785 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8617835 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3232383 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50467558 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 173 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 596710 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2000524 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 626 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52901652 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233465152 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213426027 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5240 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39335356 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13566296 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 577962 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 535418 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6495060 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9746539 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6334911 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 894923 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1137674 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 46958643 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 959615 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60863950 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 85447 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9232783 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23424311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 229955 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76664255 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793903 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.504568 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76688585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030816 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190014 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15549027 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50133952 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8864377 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 645129 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1493916 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 964413 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85194 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 52934695 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 283965 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1493916 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16391230 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19303163 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27652687 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8622958 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3222506 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50466149 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 593171 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 1994496 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 690 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52886950 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233487672 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213429055 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5328 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39332432 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13554518 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 579559 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 536966 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6477487 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9753455 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6333018 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 895982 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1122035 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 46958561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 957421 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60864798 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 86364 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9232524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23424717 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 226140 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76688585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793662 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.504660 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54480181 71.06% 71.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7304682 9.53% 80.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3460273 4.51% 85.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2866704 3.74% 88.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6125054 7.99% 96.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1372858 1.79% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 769548 1.00% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 222824 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62131 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54509370 71.08% 71.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7300848 9.52% 80.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3460717 4.51% 85.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2863086 3.73% 88.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6124123 7.99% 96.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1373475 1.79% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 772006 1.01% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 222325 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62635 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76664255 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76688585 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29010 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28981 0.66% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available @@ -2224,13 +2176,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4179738 94.96% 95.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 192807 4.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4176523 94.96% 95.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 192832 4.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12555 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28808011 47.33% 47.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45980 0.08% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12596 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28808168 47.33% 47.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45770 0.08% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued @@ -2247,7 +2199,7 @@ system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.43% # Ty system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued @@ -2256,116 +2208,116 @@ system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Ty system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 867 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26140692 42.95% 90.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5855817 9.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26145062 42.96% 90.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5852305 9.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60863950 # Type of FU issued -system.cpu1.iq.rate 0.256836 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4401559 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072318 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 202912608 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57159577 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42178137 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11121 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6181 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5062 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65247126 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5828 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 310626 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60864798 # Type of FU issued +system.cpu1.iq.rate 0.256824 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4398340 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072264 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 202935847 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57156855 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42177968 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11410 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6319 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5146 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65244557 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5985 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 312441 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1995012 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2960 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15279 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 746422 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2001655 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2943 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15220 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 749307 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17045290 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332871 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17042804 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332523 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1490380 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14881654 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 224199 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48035025 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 95776 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9746539 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6334911 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 685011 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49572 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 5137 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15279 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166909 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 134382 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 301291 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59839107 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25823960 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1024843 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1493916 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14868856 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 223350 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48029034 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96518 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9753455 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6333018 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 681732 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49156 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5134 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15220 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 168778 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 134493 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 303271 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59837987 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25827716 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1026811 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 116767 # number of nop insts executed -system.cpu1.iew.exec_refs 31629946 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5849908 # Number of branches executed -system.cpu1.iew.exec_stores 5805986 # Number of stores executed -system.cpu1.iew.exec_rate 0.252512 # Inst execution rate -system.cpu1.iew.wb_sent 59372558 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42183199 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23508004 # num instructions producing a value -system.cpu1.iew.wb_consumers 42759548 # num instructions consuming a value +system.cpu1.iew.exec_nop 113052 # number of nop insts executed +system.cpu1.iew.exec_refs 31629861 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5852394 # Number of branches executed +system.cpu1.iew.exec_stores 5802145 # Number of stores executed +system.cpu1.iew.exec_rate 0.252491 # Inst execution rate +system.cpu1.iew.wb_sent 59370669 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42183114 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23501476 # num instructions producing a value +system.cpu1.iew.wb_consumers 42733790 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178006 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549772 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177995 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549951 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9155270 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 729660 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260542 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75173875 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.511996 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.483358 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9169088 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 731281 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 262316 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75194669 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.511793 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.483255 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60919870 81.04% 81.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7446257 9.91% 90.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1922213 2.56% 93.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1068282 1.42% 94.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 820469 1.09% 96.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 498258 0.66% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 699309 0.93% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 369578 0.49% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1429639 1.90% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60941986 81.05% 81.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7448338 9.91% 90.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1921902 2.56% 93.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1064941 1.42% 94.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 820613 1.09% 96.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 497482 0.66% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 699016 0.93% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 369953 0.49% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1430438 1.90% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75173875 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30400176 # Number of instructions committed -system.cpu1.commit.committedOps 38488707 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75194669 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30395180 # Number of instructions committed +system.cpu1.commit.committedOps 38484098 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13340016 # Number of memory references committed -system.cpu1.commit.loads 7751527 # Number of loads committed -system.cpu1.commit.membars 193715 # Number of memory barriers committed -system.cpu1.commit.branches 5124652 # Number of branches committed -system.cpu1.commit.fp_insts 5013 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34222153 # Number of committed integer instructions. -system.cpu1.commit.function_calls 482564 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1429639 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13335511 # Number of memory references committed +system.cpu1.commit.loads 7751800 # Number of loads committed +system.cpu1.commit.membars 194141 # Number of memory barriers committed +system.cpu1.commit.branches 5126394 # Number of branches committed +system.cpu1.commit.fp_insts 5109 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34219487 # Number of committed integer instructions. +system.cpu1.commit.function_calls 483277 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1430438 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120517356 # The number of ROB reads -system.cpu1.rob.rob_writes 96821590 # The number of ROB writes -system.cpu1.timesIdled 866519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160311368 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2319089759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30321678 # Number of Instructions Simulated -system.cpu1.committedOps 38410209 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30321678 # Number of Instructions Simulated -system.cpu1.cpi 7.815386 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.815386 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127953 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127953 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271574951 # number of integer regfile reads -system.cpu1.int_regfile_writes 43566618 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45165 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42266 # number of floating regfile writes -system.cpu1.misc_regfile_reads 132802747 # number of misc regfile reads -system.cpu1.misc_regfile_writes 590318 # number of misc regfile writes +system.cpu1.rob.rob_reads 120543738 # The number of ROB reads +system.cpu1.rob.rob_writes 96843723 # The number of ROB writes +system.cpu1.timesIdled 866392 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160301793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2319061347 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30318400 # Number of Instructions Simulated +system.cpu1.committedOps 38407318 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30318400 # Number of Instructions Simulated +system.cpu1.cpi 7.816718 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.816718 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127931 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127931 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271568545 # number of integer regfile reads +system.cpu1.int_regfile_writes 43555908 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45194 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42320 # number of floating regfile writes +system.cpu1.misc_regfile_reads 132647791 # number of misc regfile reads +system.cpu1.misc_regfile_writes 591619 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2382,17 +2334,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518508564766 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518508564766 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518507680269 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518507680269 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518507680269 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83065 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e3505e39d..31d2c1779 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629734 # Number of seconds simulated -sim_ticks 2629733911500 # Number of ticks simulated -final_tick 2629733911500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629750 # Number of seconds simulated +sim_ticks 2629749511500 # Number of ticks simulated +final_tick 2629749511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 461706 # Simulator instruction rate (inst/s) -host_op_rate 587514 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20164609948 # Simulator tick rate (ticks/s) -host_mem_usage 422284 # Number of bytes of host memory used -host_seconds 130.41 # Real time elapsed on the host -sim_insts 60212552 # Number of instructions simulated -sim_ops 76619667 # Number of ops (including micro ops) simulated +host_inst_rate 406352 # Simulator instruction rate (inst/s) +host_op_rate 517075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17746353667 # Simulator tick rate (ticks/s) +host_mem_usage 422316 # Number of bytes of host memory used +host_seconds 148.19 # Real time elapsed on the host +sim_insts 60215342 # Number of instructions simulated +sim_ops 76622873 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 300040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4644312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 298760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4637400 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 404420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4416276 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 300040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 404420 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405700 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4423316 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 298760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405700 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 704460 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3689920 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1526984 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1489296 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706200 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3690048 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1524460 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1491820 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 72603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10880 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72495 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 69039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690912 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57655 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 381746 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 372324 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811725 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47250505 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6355 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 69149 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690914 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57657 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381115 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372955 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811727 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250225 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 114095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1766077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113608 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1763438 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 153787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1679362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50963900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 114095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 153787 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 580661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 566330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550144 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47250505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 154273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1682029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50963646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113608 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 154273 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267881 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 579698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 567286 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550177 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250225 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 114095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2346738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2343136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 153787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2245692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53514044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690912 # Number of read requests accepted -system.physmem.writeReqs 811725 # Number of write requests accepted -system.physmem.readBursts 15690912 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811725 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216512 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 154273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2249315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53513824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690914 # Number of read requests accepted +system.physmem.writeReqs 811727 # Number of write requests accepted +system.physmem.readBursts 15690914 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811727 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216640 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6837440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706200 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706328 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704890 # Number of DRAM write bursts merged with an existing one +system.physmem.mergedWrBursts 704891 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts -system.physmem.perBankRdBursts::1 980205 # Per bank write bursts +system.physmem.perBankRdBursts::1 980206 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts system.physmem.perBankRdBursts::3 980431 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts @@ -91,52 +91,52 @@ system.physmem.perBankRdBursts::11 979558 # Pe system.physmem.perBankRdBursts::12 980153 # Per bank write bursts system.physmem.perBankRdBursts::13 980093 # Per bank write bursts system.physmem.perBankRdBursts::14 980167 # Per bank write bursts -system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6735 # Per bank write bursts -system.physmem.perBankWrBursts::1 6596 # Per bank write bursts -system.physmem.perBankWrBursts::2 6612 # Per bank write bursts +system.physmem.perBankRdBursts::15 980110 # Per bank write bursts +system.physmem.perBankWrBursts::0 6736 # Per bank write bursts +system.physmem.perBankWrBursts::1 6598 # Per bank write bursts +system.physmem.perBankWrBursts::2 6606 # Per bank write bursts system.physmem.perBankWrBursts::3 6671 # Per bank write bursts -system.physmem.perBankWrBursts::4 6747 # Per bank write bursts -system.physmem.perBankWrBursts::5 7052 # Per bank write bursts -system.physmem.perBankWrBursts::6 7031 # Per bank write bursts -system.physmem.perBankWrBursts::7 6880 # Per bank write bursts -system.physmem.perBankWrBursts::8 6999 # Per bank write bursts +system.physmem.perBankWrBursts::4 6749 # Per bank write bursts +system.physmem.perBankWrBursts::5 7050 # Per bank write bursts +system.physmem.perBankWrBursts::6 7030 # Per bank write bursts +system.physmem.perBankWrBursts::7 6882 # Per bank write bursts +system.physmem.perBankWrBursts::8 6998 # Per bank write bursts system.physmem.perBankWrBursts::9 6828 # Per bank write bursts -system.physmem.perBankWrBursts::10 6320 # Per bank write bursts -system.physmem.perBankWrBursts::11 6125 # Per bank write bursts -system.physmem.perBankWrBursts::12 6609 # Per bank write bursts -system.physmem.perBankWrBursts::13 6397 # Per bank write bursts -system.physmem.perBankWrBursts::14 6618 # Per bank write bursts -system.physmem.perBankWrBursts::15 6615 # Per bank write bursts +system.physmem.perBankWrBursts::10 6323 # Per bank write bursts +system.physmem.perBankWrBursts::11 6124 # Per bank write bursts +system.physmem.perBankWrBursts::12 6612 # Per bank write bursts +system.physmem.perBankWrBursts::13 6392 # Per bank write bursts +system.physmem.perBankWrBursts::14 6620 # Per bank write bursts +system.physmem.perBankWrBursts::15 6617 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629729480000 # Total gap between requests +system.physmem.totGap 2629745080000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6718 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152162 # Read request sizes (log2) +system.physmem.readPktSize::6 152164 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57655 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1274921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1118631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1118848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3789956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2706257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2705513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2723130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57874 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57657 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1279103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1122938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1123139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3790711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2702315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2701600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2718927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 20508 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 20484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20457 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 20388 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 20349 # What read queue length does an incoming req see @@ -157,28 +157,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4787 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4718 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4690 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -189,317 +189,323 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90412 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11182.734327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1029.544171 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16746.961445 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23519 26.01% 26.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14711 16.27% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2935 3.25% 45.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2119 2.34% 47.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1367 1.51% 49.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1185 1.31% 50.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 943 1.04% 51.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1073 1.19% 52.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 614 0.68% 53.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 515 0.57% 54.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 541 0.60% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 575 0.64% 55.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 297 0.33% 55.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 299 0.33% 56.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 230 0.25% 56.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 594 0.66% 56.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 170 0.19% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 148 0.16% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 128 0.14% 57.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 277 0.31% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 134 0.15% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 229 0.25% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 52 0.06% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 35 0.04% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 49 0.05% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 107 0.12% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 29 0.03% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 27 0.03% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 349 0.39% 61.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 23 0.03% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 21 0.02% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 26 0.03% 61.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 89 0.10% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 16 0.02% 61.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.02% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 22 0.02% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 90 0.10% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 13 0.01% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 10 0.01% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 21 0.02% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 65 0.07% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 15 0.02% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 14 0.02% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 339 0.37% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 16 0.02% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 12 0.01% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 10 0.01% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 148 0.16% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 5 0.01% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 16 0.02% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 11 0.01% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 140 0.15% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 13 0.01% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 37 0.04% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 139 0.15% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 14 0.02% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 9 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 13 0.01% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 357 0.39% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 6 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 7 0.01% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 77 0.09% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 8 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 79 0.09% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 9 0.01% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 6 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 18 0.02% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 10 0.01% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 276 0.31% 64.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 64.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 9 0.01% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 76 0.08% 64.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 164 0.18% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 1 0.00% 64.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 301 0.33% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 129 0.14% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 456 0.50% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 69 0.08% 65.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 1 0.00% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 2 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 268 0.30% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 68 0.08% 65.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 129 0.14% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 66 0.07% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 512 0.57% 66.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 67 0.07% 66.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 130 0.14% 66.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 68 0.08% 66.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 266 0.29% 67.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 2 0.00% 67.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 69 0.08% 67.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 72 0.08% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 456 0.50% 67.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 130 0.14% 68.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 301 0.33% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 64 0.07% 68.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 271 0.30% 68.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 6 0.01% 68.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 73 0.08% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11847 1 0.00% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 68 0.08% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 341 0.38% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 2 0.00% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 127 0.14% 69.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 128 0.14% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 133 0.15% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 322 0.36% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 57 0.06% 70.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 77 0.09% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 324 0.36% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 72 0.08% 70.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 126 0.14% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 141 0.16% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 387 0.43% 71.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 74 0.08% 71.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 1 0.00% 71.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 66 0.07% 71.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 651 0.72% 72.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 66 0.07% 72.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16967 1 0.00% 72.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 72 0.08% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 390 0.43% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 142 0.16% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 127 0.14% 73.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 70 0.08% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 321 0.36% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 68 0.08% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 58 0.06% 73.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 323 0.36% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 131 0.14% 74.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 131 0.14% 74.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 129 0.14% 74.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 345 0.38% 75.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 68 0.08% 75.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 71 0.08% 75.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 5 0.01% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 267 0.30% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 64 0.07% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 302 0.33% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 133 0.15% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 456 0.50% 76.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 69 0.08% 76.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 68 0.08% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 265 0.29% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 131 0.14% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 514 0.57% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 67 0.07% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 129 0.14% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 67 0.07% 78.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 1 0.00% 78.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 262 0.29% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 69 0.08% 78.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 69 0.08% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 455 0.50% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 130 0.14% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 301 0.33% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 64 0.07% 79.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 267 0.30% 80.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 80.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 4 0.00% 80.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 73 0.08% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 69 0.08% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 341 0.38% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 128 0.14% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 130 0.14% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 132 0.15% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 322 0.36% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29760-29767 1 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 57 0.06% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 76 0.08% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 2 0.00% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 68 0.08% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 322 0.36% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 72 0.08% 82.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 126 0.14% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 141 0.16% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 387 0.43% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 71 0.08% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 67 0.07% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 652 0.72% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 72 0.08% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 3 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 71 0.08% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 90358 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11189.419509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1031.170467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16748.902235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23468 25.97% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14751 16.33% 42.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2914 3.22% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2094 2.32% 47.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1353 1.50% 49.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1190 1.32% 50.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 937 1.04% 51.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1064 1.18% 52.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 629 0.70% 53.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 518 0.57% 54.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 534 0.59% 54.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 581 0.64% 55.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 314 0.35% 55.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 296 0.33% 56.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 233 0.26% 56.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 596 0.66% 56.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 187 0.21% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.16% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 114 0.13% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 279 0.31% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 129 0.14% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2228 2.47% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 121 0.13% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 211 0.23% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 45 0.05% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 43 0.05% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 36 0.04% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 110 0.12% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 48 0.05% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 23 0.03% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 356 0.39% 61.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 15 0.02% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 22 0.02% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 30 0.03% 61.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 81 0.09% 61.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 12 0.01% 61.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 26 0.03% 61.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 20 0.02% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 19 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 10 0.01% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 26 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 61 0.07% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 22 0.02% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 332 0.37% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 20 0.02% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 10 0.01% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 9 0.01% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 157 0.17% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 5 0.01% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 12 0.01% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 18 0.02% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 140 0.15% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.01% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 18 0.02% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 30 0.03% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 133 0.15% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 19 0.02% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 8 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 8 0.01% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 364 0.40% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 3 0.00% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 3 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 18 0.02% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 73 0.08% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 14 0.02% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 77 0.09% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 17 0.02% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 5 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 26 0.03% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 15 0.02% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 270 0.30% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 15 0.02% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 3 0.00% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 73 0.08% 64.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 165 0.18% 64.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 1 0.00% 64.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 245 0.27% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 129 0.14% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 396 0.44% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 186 0.21% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 1 0.00% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 2 0.00% 65.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 266 0.29% 65.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 68 0.08% 65.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 129 0.14% 66.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 66 0.07% 66.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 514 0.57% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 66 0.07% 66.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 130 0.14% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 68 0.08% 66.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 264 0.29% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 2 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 69 0.08% 67.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 190 0.21% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 395 0.44% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 130 0.14% 68.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 245 0.27% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 65 0.07% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 270 0.30% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 6 0.01% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 73 0.08% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11847 1 0.00% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 68 0.08% 68.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 342 0.38% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 2 0.00% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 127 0.14% 69.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 69.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 128 0.14% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 133 0.15% 69.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 321 0.36% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 57 0.06% 70.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 77 0.09% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 324 0.36% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 72 0.08% 70.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 127 0.14% 70.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 141 0.16% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 387 0.43% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 73 0.08% 71.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 1 0.00% 71.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 65 0.07% 71.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 651 0.72% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 66 0.07% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 2 0.00% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16967 1 0.00% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 72 0.08% 72.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 389 0.43% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 142 0.16% 73.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 126 0.14% 73.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 70 0.08% 73.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 321 0.36% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 69 0.08% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 59 0.07% 73.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 322 0.36% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 131 0.14% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 131 0.14% 74.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 129 0.14% 74.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 344 0.38% 75.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 69 0.08% 75.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 72 0.08% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 6 0.01% 75.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 266 0.29% 75.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 64 0.07% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 246 0.27% 75.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 133 0.15% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 396 0.44% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 186 0.21% 76.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 68 0.08% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 1 0.00% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 265 0.29% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 130 0.14% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 65 0.07% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 512 0.57% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 66 0.07% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 129 0.14% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 67 0.07% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 1 0.00% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 264 0.29% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 69 0.08% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 185 0.20% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 394 0.44% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 130 0.14% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 246 0.27% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 65 0.07% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 267 0.30% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 2 0.00% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 4 0.00% 80.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 73 0.08% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 69 0.08% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 339 0.38% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 128 0.14% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 130 0.14% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 133 0.15% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 322 0.36% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29760-29767 1 0.00% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 57 0.06% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 76 0.08% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 2 0.00% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 68 0.08% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 322 0.36% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 72 0.08% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 126 0.14% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 141 0.16% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 387 0.43% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 71 0.08% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 1 0.00% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 66 0.07% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 652 0.72% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 71 0.08% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 3 0.00% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 71 0.08% 83.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::33792-33799 386 0.43% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 141 0.16% 84.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 125 0.14% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 72 0.08% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 321 0.36% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 57 0.06% 85.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 321 0.36% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 131 0.14% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 129 0.14% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 128 0.14% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 340 0.38% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 69 0.08% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 72 0.08% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 4 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37696-37703 1 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 269 0.30% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 64 0.07% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 301 0.33% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 129 0.14% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 455 0.50% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 69 0.08% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 67 0.07% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 262 0.29% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 141 0.16% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 126 0.14% 84.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 72 0.08% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 320 0.35% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 68 0.08% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 57 0.06% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 321 0.36% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 132 0.15% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 129 0.14% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 128 0.14% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 338 0.37% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 69 0.08% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 72 0.08% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 4 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 2 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 269 0.30% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 65 0.07% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 246 0.27% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 129 0.14% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 394 0.44% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 185 0.20% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 67 0.07% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 264 0.29% 88.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::40192-40199 67 0.07% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 129 0.14% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 66 0.07% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 514 0.57% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 129 0.14% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 65 0.07% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 512 0.57% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::41472-41479 129 0.14% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 264 0.29% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 68 0.08% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 69 0.08% 89.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 456 0.50% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 132 0.15% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 302 0.33% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 64 0.07% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 267 0.30% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 264 0.29% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 1 0.00% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 68 0.08% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 186 0.21% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 395 0.44% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 132 0.15% 90.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 246 0.27% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 64 0.07% 90.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 266 0.29% 91.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 5 0.01% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 71 0.08% 91.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 68 0.08% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 341 0.38% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 6 0.01% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 71 0.08% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 69 0.08% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 340 0.38% 91.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::45312-45319 129 0.14% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 130 0.14% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 130 0.14% 92.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::45824-45831 131 0.14% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 321 0.36% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 57 0.06% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 320 0.35% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 58 0.06% 92.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::46592-46599 74 0.08% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 69 0.08% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 70 0.08% 92.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::47104-47111 320 0.35% 93.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::47360-47367 72 0.08% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 128 0.14% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 128 0.14% 93.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::47872-47879 142 0.16% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 391 0.43% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 73 0.08% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 1 0.00% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 388 0.43% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 73 0.08% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 2 0.00% 93.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::48896-48903 66 0.07% 94.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5357 5.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90412 # Bytes accessed per row activation -system.physmem.totQLat 377428295750 # Total ticks spent queuing -system.physmem.totMemAccLat 474604408250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454415000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18721697500 # Total ticks spent accessing banks -system.physmem.avgQLat 24053.99 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1193.16 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::49152-49159 5356 5.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90358 # Bytes accessed per row activation +system.physmem.totQLat 377355345750 # Total ticks spent queuing +system.physmem.totMemAccLat 474591583250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454425000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18781812500 # Total ticks spent accessing banks +system.physmem.avgQLat 24049.33 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1196.99 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30247.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30246.32 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s @@ -510,11 +516,11 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616374 # Number of row buffer hits during reads -system.physmem.writeRowHits 90932 # Number of row buffer hits during writes +system.physmem.readRowHits 15616397 # Number of row buffer hits during reads +system.physmem.writeRowHits 90966 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes -system.physmem.avgGap 159352.08 # Average gap between requests +system.physmem.writeRowHitRate 85.15 # Row buffer hit rate for writes +system.physmem.avgGap 159352.98 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -529,72 +535,72 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54425977 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743649 # Transaction distribution -system.membus.trans_dist::ReadResp 16743649 # Transaction distribution -system.membus.trans_dist::WriteReq 763424 # Transaction distribution -system.membus.trans_dist::WriteResp 763424 # Transaction distribution -system.membus.trans_dist::Writeback 57655 # Transaction distribution +system.membus.throughput 54425810 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743683 # Transaction distribution +system.membus.trans_dist::ReadResp 16743683 # Transaction distribution +system.membus.trans_dist::WriteReq 763441 # Transaction distribution +system.membus.trans_dist::WriteResp 763441 # Transaction distribution +system.membus.trans_dist::Writeback 57657 # Transaction distribution system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 131340 # Transaction distribution -system.membus.trans_dist::ReadExResp 131340 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 131342 # Transaction distribution +system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279449 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892593 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279557 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343513 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343621 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869581 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869990 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143125837 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143125837 # Total data (bytes) +system.membus.tot_pkt_size::total 143126246 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126246 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225677000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225748500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3756500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3758000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171612500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171669500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4990561725 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990674222 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35076949500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35076241500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62045 # number of replacements -system.l2c.tags.tagsinuse 51605.891965 # Cycle average of tags in use -system.l2c.tags.total_refs 1699472 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127428 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336723 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574797983500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38210.959857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2799.685375 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3087.560110 # Average occupied blocks per requestor +system.l2c.tags.replacements 62047 # number of replacements +system.l2c.tags.tagsinuse 51602.841569 # Cycle average of tags in use +system.l2c.tags.total_refs 1699505 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127430 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336773 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574813583500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38208.002352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2774.091625 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3066.452073 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4221.092196 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3286.593539 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583053 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4246.643785 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3307.650843 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583008 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.042720 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.047112 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.042329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046790 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.064409 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050149 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.064799 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050471 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787397 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id @@ -602,186 +608,186 @@ system.l2c.tags.age_task_id_blocks_1024::2 2131 # system.l2c.tags.age_task_id_blocks_1024::3 6484 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277894 # Number of tag accesses -system.l2c.tags.data_accesses 17277894 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9810 # number of ReadReq hits +system.l2c.tags.tag_accesses 17278266 # Number of tag accesses +system.l2c.tags.data_accesses 17278266 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9823 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 412170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183158 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 411412 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183126 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10084 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 3595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 432364 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187312 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242106 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596455 # number of Writeback hits -system.l2c.Writeback_hits::total 596455 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 433138 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187347 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242132 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596464 # number of Writeback hits +system.l2c.Writeback_hits::total 596464 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57198 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57329 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114527 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9810 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::cpu0.data 57116 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57419 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114535 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9823 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 412170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 411412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10084 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 3595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 432364 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 244641 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356633 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9810 # number of overall hits +system.l2c.demand_hits::cpu1.inst 433138 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 244766 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356667 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9823 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3607 # number of overall hits -system.l2c.overall_hits::cpu0.inst 412170 # number of overall hits -system.l2c.overall_hits::cpu0.data 240356 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10090 # number of overall hits +system.l2c.overall_hits::cpu0.inst 411412 # number of overall hits +system.l2c.overall_hits::cpu0.data 240242 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10084 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 3595 # number of overall hits -system.l2c.overall_hits::cpu1.inst 432364 # number of overall hits -system.l2c.overall_hits::cpu1.data 244641 # number of overall hits -system.l2c.overall_hits::total 1356633 # number of overall hits +system.l2c.overall_hits::cpu1.inst 433138 # number of overall hits +system.l2c.overall_hits::cpu1.data 244766 # number of overall hits +system.l2c.overall_hits::total 1356667 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4274 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5319 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4254 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5302 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6318 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4908 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6338 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4925 # number of ReadReq misses system.l2c.ReadReq_misses::total 20822 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1344 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1536 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2880 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68023 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 64953 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 67932 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 65046 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 132978 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4274 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73342 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4254 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73234 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 371456750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4098046359 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9024696136 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344358750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83697263750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83703872750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82980883500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167023348500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8440281008 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8259993501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16700274509 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82981576250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167030650250 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8433139011 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8270681501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16703820512 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344358750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92137544758 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92137011761 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91240877001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183723623009 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91252257751 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183734470762 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028221 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010234 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028138 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025533 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014422 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025615 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.016487 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990420 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991607 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.991053 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543224 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.531174 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537270 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543247 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.531140 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537257 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.233798 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.222132 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101824 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014422 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.222316 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101823 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.233798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014402 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.222132 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101824 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014422 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.222316 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101823 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61523.312653 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61746.463599 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63601.874491 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60674.094708 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63532.131980 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60649.001057 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58520.607397 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58362.209736 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58443.237020 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58539.598819 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58191.904329 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58369.524553 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58738.373333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58771.769629 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58730.316042 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58745.262526 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58567.783210 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58678.128322 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59145.882078 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58738.373333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58979.783733 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58771.769629 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58715.534979 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58730.316042 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58745.262526 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58607.881035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58567.783210 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58678.128322 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -933,44 +939,44 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52790764 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471959 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471959 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596455 # Transaction distribution +system.toL2Bus.throughput 52791444 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2472019 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2472019 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763441 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763441 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596464 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2906 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2906 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247503 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247503 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753809 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadExReq 247513 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247513 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725197 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753946 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20259 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50570 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549803 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83792621 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549986 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54755680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83794182 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138655697 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138655697 # Total data (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138658310 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138658310 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 169964 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808655500 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 4808748000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865656500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865724000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4421145525 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421241528 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 13055000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30669250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30676250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48159493 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution -system.iobus.trans_dist::WriteReq 8167 # Transaction distribution -system.iobus.trans_dist::WriteResp 8167 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48159266 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution +system.iobus.trans_dist::WriteReq 8184 # Transaction distribution +system.iobus.trans_dist::WriteResp 8184 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) @@ -993,11 +999,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383092 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 33447156 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) @@ -1020,12 +1026,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390550 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646653 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 126646806 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646806 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1073,9 +1079,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42582472500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42583156500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1100,25 +1106,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7421892 # DTB read hits -system.cpu0.dtb.read_misses 6825 # DTB read misses -system.cpu0.dtb.write_hits 5624028 # DTB write hits -system.cpu0.dtb.write_misses 1832 # DTB write misses +system.cpu0.dtb.read_hits 7421730 # DTB read hits +system.cpu0.dtb.read_misses 6821 # DTB read misses +system.cpu0.dtb.write_hits 5623030 # DTB write hits +system.cpu0.dtb.write_misses 1843 # DTB write misses system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6408 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6415 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7428717 # DTB read accesses -system.cpu0.dtb.write_accesses 5625860 # DTB write accesses +system.cpu0.dtb.read_accesses 7428551 # DTB read accesses +system.cpu0.dtb.write_accesses 5624873 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13045920 # DTB hits -system.cpu0.dtb.misses 8657 # DTB misses -system.cpu0.dtb.accesses 13054577 # DTB accesses +system.cpu0.dtb.hits 13044760 # DTB hits +system.cpu0.dtb.misses 8664 # DTB misses +system.cpu0.dtb.accesses 13053424 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1140,7 +1146,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30611798 # ITB inst hits +system.cpu0.itb.inst_hits 30640130 # ITB inst hits system.cpu0.itb.inst_misses 3559 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1157,108 +1163,108 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30615357 # ITB inst accesses -system.cpu0.itb.hits 30611798 # DTB hits +system.cpu0.itb.inst_accesses 30643689 # ITB inst accesses +system.cpu0.itb.hits 30640130 # DTB hits system.cpu0.itb.misses 3559 # DTB misses -system.cpu0.itb.accesses 30615357 # DTB accesses -system.cpu0.numCycles 2628262709 # number of cpu cycles simulated +system.cpu0.itb.accesses 30643689 # DTB accesses +system.cpu0.numCycles 2628262208 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29989968 # Number of instructions committed -system.cpu0.committedOps 38153430 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34435324 # Number of integer alu accesses +system.cpu0.committedInsts 30017324 # Number of instructions committed +system.cpu0.committedOps 38175915 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34451316 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4807 # Number of float alu accesses -system.cpu0.num_func_calls 1060090 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3967783 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34435324 # number of integer instructions +system.cpu0.num_func_calls 1059150 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3975405 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34451316 # number of integer instructions system.cpu0.num_fp_insts 4807 # number of float instructions -system.cpu0.num_int_register_reads 199674548 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37122022 # number of times the integer registers were written +system.cpu0.num_int_register_reads 199768149 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37153826 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3633 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1176 # number of times the floating registers were written -system.cpu0.num_mem_refs 13619078 # number of memory refs -system.cpu0.num_load_insts 7744657 # Number of load instructions -system.cpu0.num_store_insts 5874421 # Number of store instructions -system.cpu0.num_idle_cycles 2288628005.429596 # Number of idle cycles -system.cpu0.num_busy_cycles 339634703.570404 # Number of busy cycles -system.cpu0.not_idle_fraction 0.129224 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.870776 # Percentage of idle cycles -system.cpu0.Branches 5125799 # Number of branches fetched +system.cpu0.num_mem_refs 13618692 # number of memory refs +system.cpu0.num_load_insts 7744625 # Number of load instructions +system.cpu0.num_store_insts 5874067 # Number of store instructions +system.cpu0.num_idle_cycles 2288630899.609074 # Number of idle cycles +system.cpu0.num_busy_cycles 339631308.390926 # Number of busy cycles +system.cpu0.not_idle_fraction 0.129223 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.870777 # Percentage of idle cycles +system.cpu0.Branches 5132509 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856230 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.852804 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60649877 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.791297 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20177865250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.225698 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.627106 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424269 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573490 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997759 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 856246 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.851832 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60652701 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856758 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.793271 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20193023250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.639655 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 292.212178 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.427031 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.570727 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997757 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62363363 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62363363 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30194610 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30455267 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60649877 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30194610 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30455267 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60649877 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30194610 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30455267 # number of overall hits -system.cpu0.icache.overall_hits::total 60649877 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 417188 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 439555 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856743 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 417188 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 439555 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856743 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 417188 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 439555 # number of overall misses -system.cpu0.icache.overall_misses::total 856743 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5699086500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6114552750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11813639250 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5699086500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6114552750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11813639250 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5699086500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6114552750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11813639250 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30611798 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30894822 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61506620 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30611798 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30894822 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61506620 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30611798 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30894822 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61506620 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013628 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014227 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 62366219 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62366219 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30223720 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30428981 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60652701 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30223720 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30428981 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60652701 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30223720 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30428981 # number of overall hits +system.cpu0.icache.overall_hits::total 60652701 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 416410 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 440349 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856759 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 416410 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 440349 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856759 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 416410 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 440349 # number of overall misses +system.cpu0.icache.overall_misses::total 856759 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5686967000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6125458750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11812425750 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5686967000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6125458750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11812425750 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5686967000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6125458750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11812425750 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30640130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30869330 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61509460 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30640130 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30869330 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61509460 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30640130 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30869330 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61509460 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013590 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014265 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013628 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014227 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013590 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014265 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013628 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014227 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013590 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014265 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13660.715313 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.779652 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13789.011699 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13789.011699 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13789.011699 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.133594 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.463632 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13787.337804 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.133594 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.463632 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13787.337804 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.133594 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.463632 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13787.337804 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1267,48 +1273,48 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 417188 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 439555 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856743 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 417188 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 439555 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856743 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 417188 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 439555 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856743 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4863118500 # 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number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013590 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014265 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013628 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014227 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013590 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.889644 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11782.628779 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11653.339257 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.889644 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11782.628779 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1316,120 +1322,120 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # 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Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97784872 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97784872 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6520567 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6678544 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13199111 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4990810 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4984176 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974986 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118420 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123415 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247773 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124411 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123361 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124360 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123412 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11820442 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11973181 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793623 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11820442 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11973181 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793623 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027224 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027185 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027205 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024735 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024243 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024489 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048147 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045313 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046736 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026147 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025930 # miss rate for demand accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11819956 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11974343 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23794299 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11819956 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11974343 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23794299 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027219 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027189 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024703 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024276 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048119 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046732 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026129 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025946 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026037 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026147 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025930 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026129 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025946 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026037 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14924.019245 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14771.616300 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14846.962481 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46309.758576 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45456.304520 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45887.712766 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13491.402337 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27774.509942 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26985.635712 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27378.900097 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1438,77 +1444,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596455 # number of writebacks -system.cpu0.dcache.writebacks::total 596455 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90647011250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13263386492 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12973041499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236427991 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104688854242 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103620052749 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208308906991 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027224 # 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number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91432491750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90647732000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080223750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13248714489 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12991485999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26240200488 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104681206239 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103639217999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208320424238 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027219 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027189 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024703 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024276 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048119 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045335 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026129 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025946 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026129 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025946 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12916.725575 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12766.148261 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12840.591872 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44100.375887 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43254.890577 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43682.270741 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11490.567613 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12195.125224 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.677893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12917.411644 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12770.113619 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12842.918040 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44111.713374 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43163.887585 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43642.325399 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11491.059492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12194.057194 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.749633 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25684.542864 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.953565 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25292.084827 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25684.542864 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.953565 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25292.084827 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1542,25 +1548,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7578222 # DTB read hits -system.cpu1.dtb.read_misses 7256 # DTB read misses -system.cpu1.dtb.write_hits 5608824 # DTB write hits -system.cpu1.dtb.write_misses 1858 # DTB write misses +system.cpu1.dtb.read_hits 7578931 # DTB read hits +system.cpu1.dtb.read_misses 7259 # DTB read misses +system.cpu1.dtb.write_hits 5610002 # DTB write hits +system.cpu1.dtb.write_misses 1852 # DTB write misses system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6698 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6696 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 234 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7585478 # DTB read accesses -system.cpu1.dtb.write_accesses 5610682 # DTB write accesses +system.cpu1.dtb.read_accesses 7586190 # DTB read accesses +system.cpu1.dtb.write_accesses 5611854 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13187046 # DTB hits -system.cpu1.dtb.misses 9114 # DTB misses -system.cpu1.dtb.accesses 13196160 # DTB accesses +system.cpu1.dtb.hits 13188933 # DTB hits +system.cpu1.dtb.misses 9111 # DTB misses +system.cpu1.dtb.accesses 13198044 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1582,7 +1588,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 30894839 # ITB inst hits +system.cpu1.itb.inst_hits 30869347 # ITB inst hits system.cpu1.itb.inst_misses 3806 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1599,33 +1605,33 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30898645 # ITB inst accesses -system.cpu1.itb.hits 30894839 # DTB hits +system.cpu1.itb.inst_accesses 30873153 # ITB inst accesses +system.cpu1.itb.hits 30869347 # DTB hits system.cpu1.itb.misses 3806 # DTB misses -system.cpu1.itb.accesses 30898645 # DTB accesses -system.cpu1.numCycles 2631205114 # number of cpu cycles simulated +system.cpu1.itb.accesses 30873153 # DTB accesses +system.cpu1.numCycles 2631236815 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30222584 # Number of instructions committed -system.cpu1.committedOps 38466237 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34785148 # Number of integer alu accesses +system.cpu1.committedInsts 30198018 # Number of instructions committed +system.cpu1.committedOps 38446958 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34771949 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5462 # Number of float alu accesses -system.cpu1.num_func_calls 1080322 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3981720 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34785148 # number of integer instructions +system.cpu1.num_func_calls 1081332 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3974549 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34771949 # number of integer instructions system.cpu1.num_fp_insts 5462 # number of float instructions -system.cpu1.num_int_register_reads 201769035 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37410979 # number of times the integer registers were written +system.cpu1.num_int_register_reads 201690852 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37382680 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3860 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1604 # number of times the floating registers were written -system.cpu1.num_mem_refs 13781482 # number of memory refs -system.cpu1.num_load_insts 7919681 # Number of load instructions -system.cpu1.num_store_insts 5861801 # Number of store instructions -system.cpu1.num_idle_cycles 2292298207.924829 # Number of idle cycles -system.cpu1.num_busy_cycles 338906906.075172 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128803 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871197 # Percentage of idle cycles -system.cpu1.Branches 5184020 # Number of branches fetched +system.cpu1.num_mem_refs 13782650 # number of memory refs +system.cpu1.num_load_insts 7920272 # Number of load instructions +system.cpu1.num_store_insts 5862378 # Number of store instructions +system.cpu1.num_idle_cycles 2292306354.384825 # Number of idle cycles +system.cpu1.num_busy_cycles 338930460.615175 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128810 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871190 # Percentage of idle cycles +system.cpu1.Branches 5177848 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1644,10 +1650,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557253805500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557253805500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557250761500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557250761500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557250761500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557250761500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 49d7eb553..49e1054f0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.912097 # Number of seconds simulated -sim_ticks 912096767500 # Number of ticks simulated -final_tick 912096767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.912098 # Number of seconds simulated +sim_ticks 912098398000 # Number of ticks simulated +final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734225 # Simulator instruction rate (inst/s) -host_op_rate 945306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10865482551 # Simulator tick rate (ticks/s) -host_mem_usage 476960 # Number of bytes of host memory used -host_seconds 83.94 # Real time elapsed on the host -sim_insts 61634065 # Number of instructions simulated -sim_ops 79353129 # Number of ops (including micro ops) simulated +host_inst_rate 1169212 # Simulator instruction rate (inst/s) +host_op_rate 1505339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17301899059 # Simulator tick rate (ticks/s) +host_mem_usage 421332 # Number of bytes of host memory used +host_seconds 52.72 # Real time elapsed on the host +sim_insts 61636937 # Number of instructions simulated +sim_ops 79356422 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -35,76 +35,76 @@ system.physmem.bytes_read::realview.clcd 39321600 # Nu system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6235196 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3364536 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 97499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 52599 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082824 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 550621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6836112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 235278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3688793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 550621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 235278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 785899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4600143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4600143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 550621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6854751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 235278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6988978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62341477 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 64986682 # Throughput (bytes/s) -system.membus.data_through_bus 59274143 # Total data (bytes) +system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 64987015 # Throughput (bytes/s) +system.membus.data_through_bus 59274552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 70658 # number of replacements -system.l2c.tags.tagsinuse 51560.149479 # Cycle average of tags in use -system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. +system.l2c.tags.replacements 70660 # number of replacements +system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use +system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.694836 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.955623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.444990 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.451280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.922652 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy @@ -112,7 +112,7 @@ system.l2c.tags.occ_percent::cpu0.data 0.037879 # Av system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id @@ -124,46 +124,46 @@ system.l2c.tags.age_task_id_blocks_1024::3 12549 # system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16908094 # Number of tag accesses -system.l2c.tags.data_accesses 16908094 # Number of data accesses +system.l2c.tags.tag_accesses 16908072 # Number of tag accesses +system.l2c.tags.data_accesses 16908072 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits -system.l2c.Writeback_hits::total 567807 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits +system.l2c.Writeback_hits::total 567806 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits -system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits +system.l2c.demand_hits::total 1317462 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits -system.l2c.overall_hits::cpu0.data 233336 # number of overall hits +system.l2c.overall_hits::cpu0.data 233332 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits system.l2c.overall_hits::cpu1.data 219723 # number of overall hits -system.l2c.overall_hits::total 1317466 # number of overall hits +system.l2c.overall_hits::total 1317462 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses @@ -178,63 +178,63 @@ system.l2c.UpgradeReq_misses::total 9391 # nu system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 92465 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 48373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140838 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses -system.l2c.demand_misses::total 163290 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses +system.l2c.demand_misses::total 163292 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses -system.l2c.overall_misses::cpu0.data 98856 # number of overall misses +system.l2c.overall_misses::cpu0.data 98857 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses -system.l2c.overall_misses::cpu1.data 53648 # number of overall misses -system.l2c.overall_misses::total 163290 # number of overall misses +system.l2c.overall_misses::cpu1.data 53649 # number of overall misses +system.l2c.overall_misses::total 163292 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses @@ -249,25 +249,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.880544 # mi system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -276,8 +276,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65559 # number of writebacks -system.l2c.writebacks::total 65559 # number of writebacks +system.l2c.writebacks::writebacks 65561 # number of writebacks +system.l2c.writebacks::total 65561 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -285,11 +285,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 154019994 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140481139 # Total data (bytes) +system.toL2Bus.throughput 154019817 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140481228 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 45730949 # Throughput (bytes/s) -system.iobus.data_through_bus 41711051 # Total data (bytes) +system.iobus.throughput 45731035 # Throughput (bytes/s) +system.iobus.data_through_bus 41711204 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,9 +313,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7977216 # DTB read hits +system.cpu0.dtb.read_hits 7977762 # DTB read hits system.cpu0.dtb.read_misses 3611 # DTB read misses -system.cpu0.dtb.write_hits 5966960 # DTB write hits +system.cpu0.dtb.write_hits 5967140 # DTB write hits system.cpu0.dtb.write_misses 672 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -326,12 +326,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7980827 # DTB read accesses -system.cpu0.dtb.write_accesses 5967632 # DTB write accesses +system.cpu0.dtb.read_accesses 7981373 # DTB read accesses +system.cpu0.dtb.write_accesses 5967812 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13944176 # DTB hits +system.cpu0.dtb.hits 13944902 # DTB hits system.cpu0.dtb.misses 4283 # DTB misses -system.cpu0.dtb.accesses 13948459 # DTB accesses +system.cpu0.dtb.accesses 13949185 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -353,7 +353,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30245736 # ITB inst hits +system.cpu0.itb.inst_hits 30248608 # ITB inst hits system.cpu0.itb.inst_misses 2175 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -370,74 +370,74 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30247911 # ITB inst accesses -system.cpu0.itb.hits 30245736 # DTB hits +system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses +system.cpu0.itb.hits 30248608 # DTB hits system.cpu0.itb.misses 2175 # DTB misses -system.cpu0.itb.accesses 30247911 # DTB accesses -system.cpu0.numCycles 1823671415 # number of cpu cycles simulated +system.cpu0.itb.accesses 30250783 # DTB accesses +system.cpu0.numCycles 1823674676 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29756754 # Number of instructions committed -system.cpu0.committedOps 39137733 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34752271 # Number of integer alu accesses +system.cpu0.committedInsts 29759626 # Number of instructions committed +system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses -system.cpu0.num_func_calls 1242676 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4045310 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34752271 # number of integer instructions +system.cpu0.num_func_calls 1242746 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34755088 # number of integer instructions system.cpu0.num_fp_insts 5449 # number of float instructions -system.cpu0.num_int_register_reads 179899233 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36833612 # number of times the integer registers were written +system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_mem_refs 14629077 # number of memory refs -system.cpu0.num_load_insts 8358676 # Number of load instructions -system.cpu0.num_store_insts 6270401 # Number of store instructions -system.cpu0.num_idle_cycles 1783997907.577739 # Number of idle cycles -system.cpu0.num_busy_cycles 39673507.422261 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021755 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978245 # Percentage of idle cycles -system.cpu0.Branches 5491598 # Number of branches fetched +system.cpu0.num_mem_refs 14629859 # number of memory refs +system.cpu0.num_load_insts 8359235 # Number of load instructions +system.cpu0.num_store_insts 6270624 # Number of store instructions +system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles +system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles +system.cpu0.Branches 5492144 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.015213 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29818047 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.496541 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64537144000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015213 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 30676165 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 30676165 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29818047 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29818047 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29818047 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29818047 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29818047 # number of overall hits -system.cpu0.icache.overall_hits::total 29818047 # number of overall hits +system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits +system.cpu0.icache.overall_hits::total 29820919 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses system.cpu0.icache.overall_misses::total 429059 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30247106 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 30247106 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30247106 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 30247106 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30247106 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 30247106 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014185 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014185 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014185 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014185 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014185 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014185 # miss rate for overall accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,68 +447,68 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 323609 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763093 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12469292 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.487726 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 323608 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51682637 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51682637 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6513463 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6513463 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5631258 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5631258 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12144721 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12144721 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12144721 # number of overall hits -system.cpu0.dcache.overall_hits::total 12144721 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits +system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167351 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 167351 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 364518 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 364518 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 364518 # number of overall misses -system.cpu0.dcache.overall_misses::total 364518 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6710630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6710630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798609 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses +system.cpu0.dcache.overall_misses::total 364517 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12509239 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12509239 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12509239 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12509239 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029381 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029381 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029140 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029140 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029140 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029140 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,8 +517,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks -system.cpu0.dcache.writebacks::total 300958 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks +system.cpu0.dcache.writebacks::total 300957 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -604,7 +604,7 @@ system.cpu1.itb.inst_accesses 32415891 # IT system.cpu1.itb.hits 32413691 # DTB hits system.cpu1.itb.misses 2200 # DTB misses system.cpu1.itb.accesses 32415891 # DTB accesses -system.cpu1.numCycles 1824193536 # number of cpu cycles simulated +system.cpu1.numCycles 1824196797 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 31877311 # Number of instructions committed @@ -622,7 +622,7 @@ system.cpu1.num_fp_register_writes 1416 # nu system.cpu1.num_mem_refs 13371151 # number of memory refs system.cpu1.num_load_insts 7642991 # Number of load instructions system.cpu1.num_store_insts 5728160 # Number of store instructions -system.cpu1.num_idle_cycles 1783399616.755682 # Number of idle cycles +system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles @@ -630,14 +630,14 @@ system.cpu1.Branches 5037975 # Nu system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 433942 # number of replacements -system.cpu1.icache.tags.tagsinuse 475.447911 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 69967761000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447911 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id @@ -680,46 +680,46 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 294289 # number of replacements -system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11708150 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.715435 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67293491000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 48419345 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 48419345 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7002503 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7002503 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4520265 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4520265 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11522768 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11522768 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11522768 # number of overall hits -system.cpu1.dcache.overall_hits::total 11522768 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 126066 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 126066 # number of WriteReq misses +system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits +system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 324341 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 324341 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324341 # number of overall misses -system.cpu1.dcache.overall_misses::total 324341 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses +system.cpu1.dcache.overall_misses::total 324342 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) @@ -734,8 +734,8 @@ system.cpu1.dcache.overall_accesses::cpu1.data 11847109 system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027132 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index ead7e7aa6..101d25ddf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810269000 # Number of ticks simulated -final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332812 # Number of seconds simulated +sim_ticks 2332811899500 # Number of ticks simulated +final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 702757 # Simulator instruction rate (inst/s) -host_op_rate 903702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27138460197 # Simulator tick rate (ticks/s) -host_mem_usage 475940 # Number of bytes of host memory used -host_seconds 85.96 # Real time elapsed on the host -sim_insts 60408649 # Number of instructions simulated -sim_ops 77681829 # Number of ops (including micro ops) simulated +host_inst_rate 1065837 # Simulator instruction rate (inst/s) +host_op_rate 1370594 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41157671581 # Simulator tick rate (ticks/s) +host_mem_usage 420236 # Number of bytes of host memory used +host_seconds 56.68 # Real time elapsed on the host +sim_insts 60411489 # Number of instructions simulated +sim_ops 77685090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory @@ -29,42 +29,42 @@ system.physmem.bytes_read::realview.clcd 111673344 # Nu system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071768 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3703424 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719240 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 141782 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57866 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811820 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3888770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1292781 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969605 # Throughput (bytes/s) -system.membus.data_through_bus 130566470 # Total data (bytes) +system.physmem.bw_total::cpu.data 5181551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942288 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55969769 # Throughput (bytes/s) +system.membus.data_through_bus 130566943 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -72,8 +72,8 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48895252 # Throughput (bytes/s) -system.iobus.data_through_bus 114063346 # Total data (bytes) +system.iobus.throughput 48895283 # Throughput (bytes/s) +system.iobus.data_through_bus 114063499 # Total data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -98,9 +98,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971217 # DTB read hits +system.cpu.dtb.read_hits 14971763 # DTB read hits system.cpu.dtb.read_misses 7294 # DTB read misses -system.cpu.dtb.write_hits 11217004 # DTB write hits +system.cpu.dtb.write_hits 11217184 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -111,12 +111,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14978511 # DTB read accesses -system.cpu.dtb.write_accesses 11219185 # DTB write accesses +system.cpu.dtb.read_accesses 14979057 # DTB read accesses +system.cpu.dtb.write_accesses 11219365 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188221 # DTB hits +system.cpu.dtb.hits 26188947 # DTB hits system.cpu.dtb.misses 9475 # DTB misses -system.cpu.dtb.accesses 26197696 # DTB accesses +system.cpu.dtb.accesses 26198422 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61431840 # ITB inst hits +system.cpu.itb.inst_hits 61434680 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -155,42 +155,42 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61436311 # ITB inst accesses -system.cpu.itb.hits 61431840 # DTB hits +system.cpu.itb.inst_accesses 61439151 # ITB inst accesses +system.cpu.itb.hits 61434680 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61436311 # DTB accesses -system.cpu.numCycles 4665620539 # number of cpu cycles simulated +system.cpu.itb.accesses 61439151 # DTB accesses +system.cpu.numCycles 4665623800 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60408649 # Number of instructions committed -system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses +system.cpu.committedInsts 60411489 # Number of instructions committed +system.cpu.committedOps 77685090 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69133554 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2136008 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls -system.cpu.num_int_insts 69130761 # number of integer instructions +system.cpu.num_func_calls 2136078 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7942566 # number of instructions that are conditional controls +system.cpu.num_int_insts 69133554 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read -system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written +system.cpu.num_int_register_reads 355910547 # number of times the integer registers were read +system.cpu.num_int_register_writes 74442273 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27361639 # number of memory refs -system.cpu.num_load_insts 15639529 # Number of load instructions -system.cpu.num_store_insts 11722110 # Number of store instructions -system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles -system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles -system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983111 # Percentage of idle cycles -system.cpu.Branches 10298723 # Number of branches fetched +system.cpu.num_mem_refs 27362421 # number of memory refs +system.cpu.num_load_insts 15640088 # Number of load instructions +system.cpu.num_store_insts 11722333 # Number of store instructions +system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles +system.cpu.num_busy_cycles 78801726.992856 # Number of busy cycles +system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983110 # Percentage of idle cycles +system.cpu.Branches 10299261 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu.icache.tags.replacements 850590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60586338 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor +system.cpu.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678462 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -199,32 +199,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 78 system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62285702 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62285702 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits -system.cpu.icache.overall_hits::total 60583498 # number of overall hits +system.cpu.icache.tags.tag_accesses 62288542 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62288542 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60586338 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60586338 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60586338 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60586338 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60586338 # number of overall hits +system.cpu.icache.overall_hits::total 60586338 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses system.cpu.icache.overall_misses::total 851102 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 61437440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61437440 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61437440 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013853 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -234,23 +234,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62243 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62245 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50007.460447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669929 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127630 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.084142 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36899.777920 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960146 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.716487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.011961 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563046 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.763053 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id @@ -261,15 +261,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17035899 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17035899 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 17035991 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17035991 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 366775 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1216282 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 592648 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 592648 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits @@ -277,13 +277,13 @@ system.cpu.l2cache.ReadExReq_hits::total 113739 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 480514 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1330021 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits -system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 480514 # number of overall hits +system.cpu.l2cache.overall_hits::total 1330021 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses @@ -291,39 +291,39 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133470 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133470 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143341 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153953 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses -system.cpu.l2cache.overall_misses::total 153951 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143341 # number of overall misses +system.cpu.l2cache.overall_misses::total 153953 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 376646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1236765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 592648 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 592648 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247209 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247209 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 623855 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1483974 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 623855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1483974 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses @@ -331,18 +331,18 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539908 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.539908 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103744 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103744 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,14 +351,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks -system.cpu.l2cache.writebacks::total 57863 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57866 # number of writebacks +system.cpu.l2cache.writebacks::total 57866 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 623337 # number of replacements +system.cpu.dcache.tags.replacements 623343 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 23629012 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.875808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -368,44 +368,44 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97632617 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97632617 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 97635323 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97635323 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13180574 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13180574 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9962233 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9962233 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits -system.cpu.dcache.overall_hits::total 23142138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 23142807 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23142807 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23142807 # number of overall hits +system.cpu.dcache.overall_hits::total 23142807 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 365463 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 365463 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250154 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses -system.cpu.dcache.overall_misses::total 615611 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 615617 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 615617 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615617 # number of overall misses +system.cpu.dcache.overall_misses::total 615617 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13546037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13546037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10212387 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23758424 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23758424 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23758424 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23758424 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses @@ -422,11 +422,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks -system.cpu.dcache.writebacks::total 592643 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592648 # number of writebacks +system.cpu.dcache.writebacks::total 592648 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes) +system.cpu.toL2Bus.throughput 59102995 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137876171 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index dfe5d9e95..786f029ca 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196139 # Number of seconds simulated -sim_ticks 1196139241000 # Number of ticks simulated -final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196143 # Number of seconds simulated +sim_ticks 1196142873000 # Number of ticks simulated +final_tick 1196142873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 363491 # Simulator instruction rate (inst/s) -host_op_rate 463152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7074263356 # Simulator tick rate (ticks/s) -host_mem_usage 480032 # Number of bytes of host memory used -host_seconds 169.08 # Real time elapsed on the host -sim_insts 61460236 # Number of instructions simulated -sim_ops 78311148 # Number of ops (including micro ops) simulated +host_inst_rate 497666 # Simulator instruction rate (inst/s) +host_op_rate 634118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9685782626 # Simulator tick rate (ticks/s) +host_mem_usage 425428 # Number of bytes of host memory used +host_seconds 123.49 # Real time elapsed on the host +sim_insts 61459155 # Number of instructions simulated +sim_ops 78310163 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -34,141 +34,141 @@ system.realview.nvmem.bw_total::total 57 # To system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4714556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4724988 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4804536 # Number of bytes read from this memory -system.physmem.bytes_read::total 62141956 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4110528 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 324292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4798584 # Number of bytes read from this memory +system.physmem.bytes_read::total 62146244 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393356 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 324292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4113152 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7137872 # Number of bytes written to this memory +system.physmem.bytes_written::total 7140496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12374 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73902 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75099 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64227 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75006 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654512 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64268 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821063 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43393369 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821104 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43393238 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 328694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3941478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 328854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3950187 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 271437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4016703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51952109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 328694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 271437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3436496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 271115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4011715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51955536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 328854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 271115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 599968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3438680 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5967426 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3436496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43393369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516709 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5969601 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3438680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43393238 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 328694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3955690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 328854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3964399 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 271437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6533420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57919534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654445 # Number of read requests accepted -system.physmem.writeReqs 821063 # Number of write requests accepted -system.physmem.readBursts 6654445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821063 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425854976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 29504 # Total number of bytes read from write queue -system.physmem.bytesWritten 7264576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62141956 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7137872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707541 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12043 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415328 # Per bank write bursts -system.physmem.perBankRdBursts::1 415204 # Per bank write bursts -system.physmem.perBankRdBursts::2 415403 # Per bank write bursts -system.physmem.perBankRdBursts::3 415627 # Per bank write bursts -system.physmem.perBankRdBursts::4 422407 # Per bank write bursts -system.physmem.perBankRdBursts::5 415617 # Per bank write bursts -system.physmem.perBankRdBursts::6 415785 # Per bank write bursts -system.physmem.perBankRdBursts::7 415500 # Per bank write bursts -system.physmem.perBankRdBursts::8 416027 # Per bank write bursts -system.physmem.perBankRdBursts::9 415632 # Per bank write bursts -system.physmem.perBankRdBursts::10 415316 # Per bank write bursts -system.physmem.perBankRdBursts::11 414840 # Per bank write bursts -system.physmem.perBankRdBursts::12 415044 # Per bank write bursts -system.physmem.perBankRdBursts::13 415557 # Per bank write bursts -system.physmem.perBankRdBursts::14 415554 # Per bank write bursts -system.physmem.perBankRdBursts::15 415143 # Per bank write bursts -system.physmem.perBankWrBursts::0 6946 # Per bank write bursts -system.physmem.perBankWrBursts::1 6844 # Per bank write bursts -system.physmem.perBankWrBursts::2 7080 # Per bank write bursts -system.physmem.perBankWrBursts::3 7140 # Per bank write bursts -system.physmem.perBankWrBursts::4 7438 # Per bank write bursts -system.physmem.perBankWrBursts::5 7223 # Per bank write bursts -system.physmem.perBankWrBursts::6 7431 # Per bank write bursts -system.physmem.perBankWrBursts::7 7190 # Per bank write bursts -system.physmem.perBankWrBursts::8 7575 # Per bank write bursts -system.physmem.perBankWrBursts::9 7264 # Per bank write bursts -system.physmem.perBankWrBursts::10 7139 # Per bank write bursts -system.physmem.perBankWrBursts::11 6649 # Per bank write bursts -system.physmem.perBankWrBursts::12 6729 # Per bank write bursts -system.physmem.perBankWrBursts::13 7011 # Per bank write bursts -system.physmem.perBankWrBursts::14 7090 # Per bank write bursts -system.physmem.perBankWrBursts::15 6760 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 271115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6528424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57925137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654512 # Number of read requests accepted +system.physmem.writeReqs 821104 # Number of write requests accepted +system.physmem.readBursts 6654512 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425857728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue +system.physmem.bytesWritten 7268800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62146244 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7140496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707525 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12040 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415388 # Per bank write bursts +system.physmem.perBankRdBursts::1 415219 # Per bank write bursts +system.physmem.perBankRdBursts::2 415339 # Per bank write bursts +system.physmem.perBankRdBursts::3 415675 # Per bank write bursts +system.physmem.perBankRdBursts::4 422392 # Per bank write bursts +system.physmem.perBankRdBursts::5 415542 # Per bank write bursts +system.physmem.perBankRdBursts::6 415783 # Per bank write bursts +system.physmem.perBankRdBursts::7 415483 # Per bank write bursts +system.physmem.perBankRdBursts::8 416074 # Per bank write bursts +system.physmem.perBankRdBursts::9 415577 # Per bank write bursts +system.physmem.perBankRdBursts::10 415249 # Per bank write bursts +system.physmem.perBankRdBursts::11 414844 # Per bank write bursts +system.physmem.perBankRdBursts::12 415143 # Per bank write bursts +system.physmem.perBankRdBursts::13 415555 # Per bank write bursts +system.physmem.perBankRdBursts::14 415561 # Per bank write bursts +system.physmem.perBankRdBursts::15 415203 # Per bank write bursts +system.physmem.perBankWrBursts::0 6999 # Per bank write bursts +system.physmem.perBankWrBursts::1 6843 # Per bank write bursts +system.physmem.perBankWrBursts::2 7018 # Per bank write bursts +system.physmem.perBankWrBursts::3 7170 # Per bank write bursts +system.physmem.perBankWrBursts::4 7419 # Per bank write bursts +system.physmem.perBankWrBursts::5 7182 # Per bank write bursts +system.physmem.perBankWrBursts::6 7433 # Per bank write bursts +system.physmem.perBankWrBursts::7 7180 # Per bank write bursts +system.physmem.perBankWrBursts::8 7611 # Per bank write bursts +system.physmem.perBankWrBursts::9 7217 # Per bank write bursts +system.physmem.perBankWrBursts::10 7107 # Per bank write bursts +system.physmem.perBankWrBursts::11 6660 # Per bank write bursts +system.physmem.perBankWrBursts::12 6804 # Per bank write bursts +system.physmem.perBankWrBursts::13 7009 # Per bank write bursts +system.physmem.perBankWrBursts::14 7096 # Per bank write bursts +system.physmem.perBankWrBursts::15 6827 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196134740000 # Total gap between requests +system.physmem.totGap 1196138285000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159532 # Read request sizes (log2) +system.physmem.readPktSize::6 159599 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64227 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 627903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 474579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 475456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1579907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1133019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1127067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1123495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64268 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 628282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 475071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 476093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1580129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1132007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1126499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1123122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8860 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -183,29 +183,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5163 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -215,727 +215,726 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5818.973345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 397.615709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13075.139994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25664 34.48% 34.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15269 20.51% 54.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3288 4.42% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2378 3.19% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1591 2.14% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1326 1.78% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1035 1.39% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1141 1.53% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 724 0.97% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 588 0.79% 71.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 595 0.80% 72.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 643 0.86% 72.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 322 0.43% 73.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 287 0.39% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 216 0.29% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 358 0.48% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 180 0.24% 74.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 137 0.18% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 152 0.20% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2272 3.05% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 131 0.18% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 156 0.21% 78.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 73 0.10% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 70 0.09% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 130 0.17% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 52 0.07% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 26 0.03% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 15 0.02% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 134 0.18% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 21 0.03% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 27 0.04% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 25 0.03% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 22 0.03% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 23 0.03% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 8 0.01% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 25 0.03% 80.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 35 0.05% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 11 0.01% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 26 0.03% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 8 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 105 0.14% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 6 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 41 0.06% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 26 0.03% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 85 0.11% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 29 0.04% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 86 0.12% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 19 0.03% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 202 0.27% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 3 0.00% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 6 0.01% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 18 0.02% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 2 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 20 0.03% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 17 0.02% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 92 0.12% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 17 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 96 0.13% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 30 0.04% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 172 0.23% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 8 0.01% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 88 0.12% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 223 0.30% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 29 0.04% 82.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 24 0.03% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 22 0.03% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 74541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5810.577695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 397.196541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 13066.067638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25758 34.56% 34.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15237 20.44% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3243 4.35% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2416 3.24% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1619 2.17% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1307 1.75% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1041 1.40% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1103 1.48% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 718 0.96% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 614 0.82% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 577 0.77% 71.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 705 0.95% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 343 0.46% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 280 0.38% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 211 0.28% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 365 0.49% 74.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 178 0.24% 74.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.19% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 160 0.21% 75.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2248 3.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 145 0.19% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 165 0.22% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 59 0.08% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 66 0.09% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 116 0.16% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 27 0.04% 79.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 17 0.02% 79.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 120 0.16% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 29 0.04% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 31 0.04% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 12 0.02% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 26 0.03% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 23 0.03% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 24 0.03% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 12 0.02% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 29 0.04% 80.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 10 0.01% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 25 0.03% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 133 0.18% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 12 0.02% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 45 0.06% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 4 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 21 0.03% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.01% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 31 0.04% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 79 0.11% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 3 0.00% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 183 0.25% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 2 0.00% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 24 0.03% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 3 0.00% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 17 0.02% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 18 0.02% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 95 0.13% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 11 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 5 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 100 0.13% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 4 0.01% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 16 0.02% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 174 0.23% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 9 0.01% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 93 0.12% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 3 0.00% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 214 0.29% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 32 0.04% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 12 0.02% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 160 0.21% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 82.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 33 0.04% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 14 0.02% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 10 0.01% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 260 0.35% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 7 0.01% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 14 0.02% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 33 0.04% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 155 0.21% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 2 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 19 0.03% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 22 0.03% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 27 0.04% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 223 0.30% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 89 0.12% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 6 0.01% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 22 0.03% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 98 0.13% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 76 0.10% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 19 0.03% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 15 0.02% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 169 0.23% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 85 0.11% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 80 0.11% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13511 1 0.00% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 22 0.03% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14023 1 0.00% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 7 0.01% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 2 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 95 0.13% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 100 0.13% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 2 0.00% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 74 0.10% 85.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 18 0.02% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 105 0.14% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 76 0.10% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 18 0.02% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 76 0.10% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 161 0.22% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 2 0.00% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 77 0.10% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 23 0.03% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 72 0.10% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 107 0.14% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 15 0.02% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 76 0.10% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 97 0.13% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 102 0.14% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 2 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 4 0.01% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 78 0.10% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 82 0.11% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 16 0.02% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 83 0.11% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 81 0.11% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 176 0.24% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 2 0.00% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 17 0.02% 87.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 73 0.10% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 87 0.12% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 10 0.01% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 223 0.30% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 27 0.04% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.18% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 86 0.12% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 12 0.02% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 17 0.02% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 106 0.14% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 81 0.11% 84.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 14 0.02% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 16 0.02% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 3 0.00% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 158 0.21% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 76 0.10% 84.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 84 0.11% 84.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 29 0.04% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 105 0.14% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13383 1 0.00% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 26 0.03% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 13 0.02% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 92 0.12% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 80 0.11% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 81 0.11% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 16 0.02% 85.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 110 0.15% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 77 0.10% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15815 1 0.00% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 13 0.02% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 82 0.11% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 155 0.21% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 83 0.11% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 8 0.01% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 77 0.10% 86.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 119 0.16% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 21 0.03% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 82 0.11% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 80 0.11% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 83 0.11% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 3 0.00% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 10 0.01% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 1 0.00% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 83 0.11% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 103 0.14% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 25 0.03% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 80 0.11% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 1 0.00% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 73 0.10% 87.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 155 0.21% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 19 0.03% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 16 0.02% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 81 0.11% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 95 0.13% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 10 0.01% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 9 0.01% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 219 0.29% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 30 0.04% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 30 0.04% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 16 0.02% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 8 0.01% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 269 0.36% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 5 0.01% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 32 0.04% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 144 0.19% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 22 0.03% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 1 0.00% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 20 0.03% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 26 0.03% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 224 0.30% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 85 0.11% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26944-26951 1 0.00% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 6 0.01% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 26 0.03% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 2 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 89 0.12% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 73 0.10% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 18 0.02% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 16 0.02% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 161 0.22% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 2 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 84 0.11% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 80 0.11% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 15 0.02% 90.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 89 0.12% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 19 0.03% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 82 0.11% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 5 0.01% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 93 0.12% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 97 0.13% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 74 0.10% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 1 0.00% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 16 0.02% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 105 0.14% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 2 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 73 0.10% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 21 0.03% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 75 0.10% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 157 0.21% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 81 0.11% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 29 0.04% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 73 0.10% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 105 0.14% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 16 0.02% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 71 0.10% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 97 0.13% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34759 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 90 0.12% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 3 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 81 0.11% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 18 0.02% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 87 0.12% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 13 0.02% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 79 0.11% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36672-36679 2 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 156 0.21% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37056-37063 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 14 0.02% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 16 0.02% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 75 0.10% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 86 0.12% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 24 0.03% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 6 0.01% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 85 0.11% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 221 0.30% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 25 0.03% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39360-39367 3 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 18 0.02% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 2 0.00% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 142 0.19% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 1 0.00% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 32 0.04% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 5 0.01% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 265 0.36% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 6 0.01% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 13 0.02% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 2 0.00% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 31 0.04% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 24 0.03% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 20 0.03% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 27 0.04% 94.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 221 0.30% 95.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 85 0.11% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 22 0.03% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 84 0.11% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 73 0.10% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 13 0.02% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 166 0.22% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 79 0.11% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 1 0.00% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.11% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 15 0.02% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 87 0.12% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 22 0.03% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 6 0.01% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 93 0.12% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 1 0.00% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 101 0.14% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 79 0.11% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 16 0.02% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 127 0.17% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 87 0.12% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 17 0.02% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48704-48711 1 0.00% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 76 0.10% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 12 0.02% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 5 0.01% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2061 2.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74432 # Bytes accessed per row activation -system.physmem.totQLat 159552537250 # Total ticks spent queuing -system.physmem.totMemAccLat 202473692250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33269920000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9651235000 # Total ticks spent accessing banks -system.physmem.avgQLat 23978.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1450.44 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::23808-23815 22 0.03% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23879 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 13 0.02% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 3 0.00% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 273 0.37% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 26 0.03% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 2 0.00% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 24 0.03% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 143 0.19% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 12 0.02% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 28 0.04% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 214 0.29% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 90 0.12% 89.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 13 0.02% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 92 0.12% 89.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 79 0.11% 89.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 14 0.02% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 19 0.03% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 159 0.21% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 74 0.10% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 82 0.11% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 26 0.03% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 2 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 92 0.12% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 27 0.04% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 80 0.11% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 9 0.01% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 85 0.11% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 81 0.11% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 79 0.11% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 18 0.02% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 112 0.15% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 76 0.10% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 8 0.01% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 82 0.11% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 154 0.21% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 83 0.11% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33095 1 0.00% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 23 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 76 0.10% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 112 0.15% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 18 0.02% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 79 0.11% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 80 0.11% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 78 0.10% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35008-35015 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 8 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 80 0.11% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 27 0.04% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 91 0.12% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 82 0.11% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 73 0.10% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 149 0.20% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 15 0.02% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 14 0.02% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 80 0.11% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 93 0.12% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 10 0.01% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 11 0.01% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 90 0.12% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 212 0.28% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 27 0.04% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 11 0.01% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39872-39879 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 144 0.19% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 21 0.03% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 1 0.00% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 25 0.03% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 269 0.36% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 10 0.01% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 23 0.03% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 21 0.03% 94.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 11 0.01% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 1 0.00% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 31 0.04% 94.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 219 0.29% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43072-43079 1 0.00% 95.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 87 0.12% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 11 0.01% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 80 0.11% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 18 0.02% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 149 0.20% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 71 0.10% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 78 0.10% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 1 0.00% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 27 0.04% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 99 0.13% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 83 0.11% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 11 0.01% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 90 0.12% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 82 0.11% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 83 0.11% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 130 0.17% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 2 0.00% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 100 0.13% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48583 1 0.00% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 6 0.01% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 79 0.11% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 5 0.01% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2052 2.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74541 # Bytes accessed per row activation +system.physmem.totQLat 159547739500 # Total ticks spent queuing +system.physmem.totMemAccLat 202481649500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33270135000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9663775000 # Total ticks spent accessing banks +system.physmem.avgQLat 23977.62 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1452.32 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30428.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.95 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30429.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.50 # Average write queue length when enqueuing -system.physmem.readRowHits 6598277 # Number of row buffer hits during reads -system.physmem.writeRowHits 94784 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.60 # Average write queue length when enqueuing +system.physmem.readRowHits 6598250 # Number of row buffer hits during reads +system.physmem.writeRowHits 94811 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.49 # Row buffer hit rate for writes -system.physmem.avgGap 160007.15 # Average gap between requests +system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes +system.physmem.avgGap 160005.31 # Average gap between requests system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 59936382 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703367 # Transaction distribution -system.membus.trans_dist::ReadResp 7703367 # Transaction distribution -system.membus.trans_dist::WriteReq 767572 # Transaction distribution -system.membus.trans_dist::WriteResp 767572 # Transaction distribution -system.membus.trans_dist::Writeback 64227 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31703 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17214 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12043 # Transaction distribution -system.membus.trans_dist::ReadExReq 137706 # Transaction distribution -system.membus.trans_dist::ReadExResp 137264 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382576 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 4.94 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 59942042 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703387 # Transaction distribution +system.membus.trans_dist::ReadResp 7703387 # Transaction distribution +system.membus.trans_dist::WriteReq 767577 # Transaction distribution +system.membus.trans_dist::WriteResp 767577 # Transaction distribution +system.membus.trans_dist::Writeback 64268 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31533 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12040 # Transaction distribution +system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.trans_dist::ReadExResp 137334 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382660 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972063 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4365907 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972105 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366005 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17342035 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17342133 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390026 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20640 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20584 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375316 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19787746 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17382228 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19794734 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71692258 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71692258 # Total data (bytes) +system.membus.tot_pkt_size::total 71699246 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71699246 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224733500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224801500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9246500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9220500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211003500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9211496500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5080947314 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5081612097 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657701499 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657936499 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69413 # number of replacements -system.l2c.tags.tagsinuse 53013.525953 # Cycle average of tags in use -system.l2c.tags.total_refs 1672541 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134599 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.426103 # Average number of references to valid blocks. +system.l2c.tags.replacements 69480 # number of replacements +system.l2c.tags.tagsinuse 52958.538682 # Cycle average of tags in use +system.l2c.tags.total_refs 1674406 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134639 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.436263 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40184.108166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40140.336267 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3710.656491 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4243.565236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2809.342303 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2063.107654 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.613161 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001545 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3711.388388 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4232.378884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2812.770235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2058.918835 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612493 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65879.081350 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61338.254401 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.150437 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.392926 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.936960 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.567857 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.364211 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10006.310145 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54315.569856 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62669.317131 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58655.624576 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66082.158651 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61144.891040 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.632118 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.302446 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.218290 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10017.630473 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.364979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.045933 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54359.154437 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62553.446065 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58607.238626 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1129,67 +1128,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119505667 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535246 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535246 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767572 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767572 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 571037 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30983 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17532 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260644 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260644 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863518 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601780 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6235 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15427 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7672553 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27216160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41363346 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15236 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30075316 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39635324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7636 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138342022 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138342022 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4603396 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4759597686 # Layer occupancy (ticks) +system.toL2Bus.throughput 119544694 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2535779 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535779 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767577 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767577 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 570959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30837 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17592 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260947 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260947 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1227966 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6129 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12680 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940064 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600791 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6258 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15477 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7673967 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27250848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41432384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30058932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39583066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138377350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138377350 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4615184 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4759626187 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1923628472 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1926082966 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1753100289 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1756498781 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8875000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2118090473 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2116921475 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2927544636 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2926499865 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9917499 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 9923499 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45391376 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671402 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671402 # Transaction distribution -system.iobus.trans_dist::WriteReq 7950 # Transaction distribution -system.iobus.trans_dist::WriteResp 7950 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45391348 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671431 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671431 # Transaction distribution +system.iobus.trans_dist::WriteReq 7963 # Transaction distribution +system.iobus.trans_dist::WriteResp 7963 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1206,17 +1205,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382576 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382660 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358704 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358788 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16112 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1233,14 +1232,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390026 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294406 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294538 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4034000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1250,7 +1249,7 @@ system.iobus.reqLayer4.occupancy 27000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) @@ -1286,9 +1285,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374626000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374697000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17778333501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17777962501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1313,25 +1312,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7064121 # DTB read hits -system.cpu0.dtb.read_misses 3756 # DTB read misses -system.cpu0.dtb.write_hits 5649416 # DTB write hits -system.cpu0.dtb.write_misses 801 # DTB write misses +system.cpu0.dtb.read_hits 7070497 # DTB read hits +system.cpu0.dtb.read_misses 3747 # DTB read misses +system.cpu0.dtb.write_hits 5655659 # DTB write hits +system.cpu0.dtb.write_misses 806 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1708 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7067877 # DTB read accesses -system.cpu0.dtb.write_accesses 5650217 # DTB write accesses +system.cpu0.dtb.read_accesses 7074244 # DTB read accesses +system.cpu0.dtb.write_accesses 5656465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12713537 # DTB hits -system.cpu0.dtb.misses 4557 # DTB misses -system.cpu0.dtb.accesses 12718094 # DTB accesses +system.cpu0.dtb.hits 12726156 # DTB hits +system.cpu0.dtb.misses 4553 # DTB misses +system.cpu0.dtb.accesses 12730709 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1353,7 +1352,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29561361 # ITB inst hits +system.cpu0.itb.inst_hits 29571351 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1370,88 +1369,88 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29563566 # ITB inst accesses -system.cpu0.itb.hits 29561361 # DTB hits +system.cpu0.itb.inst_accesses 29573556 # ITB inst accesses +system.cpu0.itb.hits 29571351 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29563566 # DTB accesses -system.cpu0.numCycles 2392278482 # number of cpu cycles simulated +system.cpu0.itb.accesses 29573556 # DTB accesses +system.cpu0.numCycles 2392285746 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28863304 # Number of instructions committed -system.cpu0.committedOps 37189208 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33114268 # Number of integer alu accesses +system.cpu0.committedInsts 28873226 # Number of instructions committed +system.cpu0.committedOps 37212709 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33137047 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241816 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4372124 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33114268 # number of integer instructions +system.cpu0.num_func_calls 1242091 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373605 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33137047 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 192166322 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36246326 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192300691 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36265278 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13380719 # number of memory refs -system.cpu0.num_load_insts 7401377 # Number of load instructions -system.cpu0.num_store_insts 5979342 # Number of store instructions -system.cpu0.num_idle_cycles 2246536230.490122 # Number of idle cycles -system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles -system.cpu0.Branches 5599941 # Number of branches fetched +system.cpu0.num_mem_refs 13394015 # number of memory refs +system.cpu0.num_load_insts 7407936 # Number of load instructions +system.cpu0.num_store_insts 5986079 # Number of store instructions +system.cpu0.num_idle_cycles 2246427166.466122 # Number of idle cycles +system.cpu0.num_busy_cycles 145858579.533878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.060970 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.939030 # Percentage of idle cycles +system.cpu0.Branches 5601726 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 424872 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.359183 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29135959 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425384 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.493312 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359183 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 46915 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 425414 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.356883 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29145407 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425926 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.428335 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76234819000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.356883 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994838 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994838 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29986729 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29986729 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29135959 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29135959 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29135959 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29135959 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29135959 # number of overall hits -system.cpu0.icache.overall_hits::total 29135959 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425385 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425385 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425385 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425385 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425385 # number of overall misses -system.cpu0.icache.overall_misses::total 425385 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5898245722 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5898245722 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5898245722 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5898245722 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5898245722 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5898245722 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29561344 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29561344 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29561344 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29561344 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29561344 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29561344 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014390 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014390 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014390 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014390 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014390 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014390 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13865.664567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13865.664567 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13865.664567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13865.664567 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 29997261 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 29997261 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29145407 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29145407 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29145407 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29145407 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29145407 # number of overall hits +system.cpu0.icache.overall_hits::total 29145407 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425927 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425927 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425927 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425927 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425927 # number of overall misses +system.cpu0.icache.overall_misses::total 425927 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899388216 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5899388216 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5899388216 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5899388216 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5899388216 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5899388216 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29571334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29571334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29571334 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29571334 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29571334 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29571334 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014403 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014403 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014403 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014403 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014403 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014403 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13850.702623 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13850.702623 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13850.702623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13850.702623 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1460,128 +1459,128 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425385 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425385 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425385 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425385 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425385 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425385 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045266278 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045266278 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045266278 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5045266278 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045266278 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5045266278 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425927 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425927 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425927 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425927 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425927 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425927 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045293784 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045293784 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045293784 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5045293784 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045293784 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5045293784 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014390 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014390 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014390 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11860.470581 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014403 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014403 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014403 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11845.442491 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # 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Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.775151 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890186 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.890186 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.093016 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.888854 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.888854 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50852132 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50852132 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6594161 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6594161 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5344638 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5344638 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148004 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 148004 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157135 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157135 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12307709 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12307709 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12307709 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12307709 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033355 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033355 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025770 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025770 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059354 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059354 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047609 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047609 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029974 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029974 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029974 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029974 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14535.775483 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14535.775483 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40086.927723 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40086.927723 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.064033 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.064033 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5914.391124 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5914.391124 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24327.440240 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24327.440240 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 50903218 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50903218 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6600273 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6600273 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5350518 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5350518 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147975 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147975 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149621 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149621 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11950791 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11950791 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11950791 # number of overall hits +system.cpu0.dcache.overall_hits::total 11950791 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227769 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227769 # 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number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5686464712 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5686464712 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92538750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 92538750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44740069 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44740069 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8996176962 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8996176962 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8996176962 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8996176962 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6828042 # 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miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029990 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029990 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14531.004000 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14531.004000 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40127.193457 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40127.193457 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9876.067236 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9876.067236 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5939.998540 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5939.998540 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24348.210896 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24348.210896 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1590,62 +1589,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305670 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8203963021 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8203963021 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8203963021 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13556999000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13556999000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167889500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167889500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14724888500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14724888500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025770 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025770 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059354 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059354 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047596 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047596 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12527.282394 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12527.282394 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37868.212226 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37868.212226 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7962.870757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7962.870757 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.822971 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.822971 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306085 # number of writebacks +system.cpu0.dcache.writebacks::total 306085 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227769 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227769 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141711 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141711 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369480 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369480 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369480 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369480 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2852244750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2852244750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372105288 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5372105288 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73750250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73750250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29678931 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29678931 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8224350038 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8224350038 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8224350038 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8224350038 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13565968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13565968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170779500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170779500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14736748000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14736748000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025802 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025802 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047915 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047915 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029990 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029990 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.532698 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.532698 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37908.879960 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37908.879960 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7870.891142 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7870.891142 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3941.425100 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3941.425100 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1676,25 +1675,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8319266 # DTB read hits -system.cpu1.dtb.read_misses 3647 # DTB read misses -system.cpu1.dtb.write_hits 5834802 # DTB write hits -system.cpu1.dtb.write_misses 1433 # DTB write misses +system.cpu1.dtb.read_hits 8312417 # DTB read hits +system.cpu1.dtb.read_misses 3644 # DTB read misses +system.cpu1.dtb.write_hits 5828126 # DTB write hits +system.cpu1.dtb.write_misses 1438 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1864 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8322913 # DTB read accesses -system.cpu1.dtb.write_accesses 5836235 # DTB write accesses +system.cpu1.dtb.read_accesses 8316061 # DTB read accesses +system.cpu1.dtb.write_accesses 5829564 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14154068 # DTB hits -system.cpu1.dtb.misses 5080 # DTB misses -system.cpu1.dtb.accesses 14159148 # DTB accesses +system.cpu1.dtb.hits 14140543 # DTB hits +system.cpu1.dtb.misses 5082 # DTB misses +system.cpu1.dtb.accesses 14145625 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1716,7 +1715,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33207997 # ITB inst hits +system.cpu1.itb.inst_hits 33196912 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1733,87 +1732,87 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33210168 # ITB inst accesses -system.cpu1.itb.hits 33207997 # DTB hits +system.cpu1.itb.inst_accesses 33199083 # ITB inst accesses +system.cpu1.itb.hits 33196912 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33210168 # DTB accesses -system.cpu1.numCycles 2390803785 # number of cpu cycles simulated +system.cpu1.itb.accesses 33199083 # DTB accesses +system.cpu1.numCycles 2390815191 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32596932 # Number of instructions committed -system.cpu1.committedOps 41121940 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37644247 # Number of integer alu accesses +system.cpu1.committedInsts 32585929 # Number of instructions committed +system.cpu1.committedOps 41097454 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37620588 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962790 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735035 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37644247 # number of integer instructions +system.cpu1.num_func_calls 962436 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3733629 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37620588 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 218344706 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39781553 # number of times the integer registers were written +system.cpu1.num_int_register_reads 218203394 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39762349 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14692820 # number of memory refs -system.cpu1.num_load_insts 8641241 # Number of load instructions -system.cpu1.num_store_insts 6051579 # Number of store instructions -system.cpu1.num_idle_cycles 1874235342.195830 # Number of idle cycles -system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles -system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles -system.cpu1.Branches 4947677 # Number of branches fetched +system.cpu1.num_mem_refs 14678716 # number of memory refs +system.cpu1.num_load_insts 8634369 # Number of load instructions +system.cpu1.num_store_insts 6044347 # Number of store instructions +system.cpu1.num_idle_cycles 1874341984.155535 # Number of idle cycles +system.cpu1.num_busy_cycles 516473206.844465 # Number of busy cycles +system.cpu1.not_idle_fraction 0.216024 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.783976 # Percentage of idle cycles +system.cpu1.Branches 4945874 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469929 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.566840 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32737552 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470441 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.589071 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93987616500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.566840 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934701 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 469670 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.560169 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32726726 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 470182 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.604379 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 94003216500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.560169 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934688 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33678434 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33678434 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32737552 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32737552 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32737552 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32737552 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32737552 # number of overall hits -system.cpu1.icache.overall_hits::total 32737552 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470441 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470441 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470441 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470441 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470441 # number of overall misses -system.cpu1.icache.overall_misses::total 470441 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6446126723 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6446126723 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6446126723 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6446126723 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6446126723 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6446126723 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33207993 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33207993 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33207993 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33207993 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33207993 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33207993 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13702.306395 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13702.306395 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13702.306395 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13702.306395 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33667090 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33667090 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32726726 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32726726 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32726726 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32726726 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32726726 # number of overall hits +system.cpu1.icache.overall_hits::total 32726726 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 470182 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 470182 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 470182 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 470182 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 470182 # number of overall misses +system.cpu1.icache.overall_misses::total 470182 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443403725 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6443403725 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6443403725 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6443403725 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6443403725 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6443403725 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196908 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33196908 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33196908 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33196908 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33196908 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13704.062948 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1822,126 +1821,126 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470441 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 470441 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 470441 # 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average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292485 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.346411 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11976402 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292833 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.898403 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 85276695250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.346411 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920598 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920598 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 49497647 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 49497647 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 6954137 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6954137 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4834149 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4834149 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82001 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 82001 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82789 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82789 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11788286 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11788286 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11788286 # 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Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 361 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 49443351 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 49443351 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6947316 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6947316 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4827697 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4827697 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82016 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 82016 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52014971 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8788375265 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8788375265 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8788375265 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8788375265 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118051 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7118051 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977770 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4977770 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93240 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 93240 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92801 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92801 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095821 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095821 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095821 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095821 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023986 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023986 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030149 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030149 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120378 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120378 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108436 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108436 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026522 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026522 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026522 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026522 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13002.735221 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13002.735221 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43767.721489 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 43767.721489 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8600.877584 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8600.877584 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5168.932823 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5168.932823 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27394.501587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27394.501587 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1950,62 +1949,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265367 # number of writebacks -system.cpu1.dcache.writebacks::total 265367 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170721 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170721 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150254 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150254 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10053 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10053 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320975 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320975 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320975 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320975 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877186006 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877186006 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6262088987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6262088987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74982000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74982000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31903526 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31903526 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8139274993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8139274993 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8139274993 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8139274993 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608498500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608498500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182871345 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182871345 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791369845 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791369845 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023961 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023961 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108280 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108280 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10995.636190 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10995.636190 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41676.687389 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41676.687389 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6650.878127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6650.878127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3173.532876 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3173.532876 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 264874 # number of writebacks +system.cpu1.dcache.writebacks::total 264874 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170735 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170735 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150073 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150073 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11224 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11224 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320808 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320808 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320808 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320808 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877877002 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877877002 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6244849733 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6244849733 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74077750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74077750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31889029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31889029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8122726735 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8122726735 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8122726735 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8122726735 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168606064250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168606064250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182609871 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182609871 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193788674121 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193788674121 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023986 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023986 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030149 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030149 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120378 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120378 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108426 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108426 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026522 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026522 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10998.781749 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10998.781749 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41612.080341 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41612.080341 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6599.942088 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6599.942088 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3169.253528 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3169.253528 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2029,10 +2028,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651805197501 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651805197501 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651805197501 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651805197501 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651823594501 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651823594501 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651823594501 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651823594501 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 48b455079..524da38ff 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616536 # Number of seconds simulated -sim_ticks 2616536483000 # Number of ticks simulated -final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616552 # Number of seconds simulated +sim_ticks 2616552083000 # Number of ticks simulated +final_tick 2616552083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 317845 # Simulator instruction rate (inst/s) -host_op_rate 404472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13815397020 # Simulator tick rate (ticks/s) -host_mem_usage 476964 # Number of bytes of host memory used -host_seconds 189.39 # Real time elapsed on the host -sim_insts 60197590 # Number of instructions simulated -sim_ops 76603983 # Number of ops (including micro ops) simulated +host_inst_rate 423166 # Simulator instruction rate (inst/s) +host_op_rate 538494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18392483259 # Simulator tick rate (ticks/s) +host_mem_usage 421292 # Number of bytes of host memory used +host_seconds 142.26 # Real time elapsed on the host +sim_insts 60200379 # Number of instructions simulated +sim_ops 76607188 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory @@ -29,59 +29,59 @@ system.physmem.bytes_read::realview.clcd 122683392 # Nu system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089752 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089880 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477664 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142063 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494705 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142065 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494707 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46887426 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3473963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50630877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152689 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46887426 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4626660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53200016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494705 # Number of read requests accepted -system.physmem.writeReqs 811927 # Number of write requests accepted -system.physmem.readBursts 15494705 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991556032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue -system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 269035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53199797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494707 # Number of read requests accepted +system.physmem.writeReqs 811929 # Number of write requests accepted +system.physmem.readBursts 15494707 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991550144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 111104 # Total number of bytes read from write queue +system.physmem.bytesWritten 6844864 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1736 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704958 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 967983 # Per bank write bursts -system.physmem.perBankRdBursts::1 967714 # Per bank write bursts +system.physmem.perBankRdBursts::1 967715 # Per bank write bursts system.physmem.perBankRdBursts::2 967672 # Per bank write bursts system.physmem.perBankRdBursts::3 967769 # Per bank write bursts system.physmem.perBankRdBursts::4 974609 # Per bank write bursts system.physmem.perBankRdBursts::5 968229 # Per bank write bursts -system.physmem.perBankRdBursts::6 967807 # Per bank write bursts +system.physmem.perBankRdBursts::6 967819 # Per bank write bursts system.physmem.perBankRdBursts::7 967736 # Per bank write bursts system.physmem.perBankRdBursts::8 968546 # Per bank write bursts system.physmem.perBankRdBursts::9 968137 # Per bank write bursts @@ -89,58 +89,58 @@ system.physmem.perBankRdBursts::10 967949 # Pe system.physmem.perBankRdBursts::11 967746 # Per bank write bursts system.physmem.perBankRdBursts::12 967851 # Per bank write bursts system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967778 # Per bank write bursts -system.physmem.perBankRdBursts::15 967796 # Per bank write bursts -system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankRdBursts::14 967672 # Per bank write bursts +system.physmem.perBankRdBursts::15 967797 # Per bank write bursts +system.physmem.perBankWrBursts::0 6609 # Per bank write bursts system.physmem.perBankWrBursts::1 6410 # Per bank write bursts -system.physmem.perBankWrBursts::2 6422 # Per bank write bursts -system.physmem.perBankWrBursts::3 6344 # Per bank write bursts -system.physmem.perBankWrBursts::4 6906 # Per bank write bursts -system.physmem.perBankWrBursts::5 7096 # Per bank write bursts -system.physmem.perBankWrBursts::6 6901 # Per bank write bursts -system.physmem.perBankWrBursts::7 6892 # Per bank write bursts -system.physmem.perBankWrBursts::8 7193 # Per bank write bursts -system.physmem.perBankWrBursts::9 6845 # Per bank write bursts -system.physmem.perBankWrBursts::10 6667 # Per bank write bursts -system.physmem.perBankWrBursts::11 6550 # Per bank write bursts -system.physmem.perBankWrBursts::12 6596 # Per bank write bursts -system.physmem.perBankWrBursts::13 6392 # Per bank write bursts -system.physmem.perBankWrBursts::14 6532 # Per bank write bursts -system.physmem.perBankWrBursts::15 6576 # Per bank write bursts +system.physmem.perBankWrBursts::2 6425 # Per bank write bursts +system.physmem.perBankWrBursts::3 6343 # Per bank write bursts +system.physmem.perBankWrBursts::4 6914 # Per bank write bursts +system.physmem.perBankWrBursts::5 7103 # Per bank write bursts +system.physmem.perBankWrBursts::6 6905 # Per bank write bursts +system.physmem.perBankWrBursts::7 6899 # Per bank write bursts +system.physmem.perBankWrBursts::8 7185 # Per bank write bursts +system.physmem.perBankWrBursts::9 6844 # Per bank write bursts +system.physmem.perBankWrBursts::10 6668 # Per bank write bursts +system.physmem.perBankWrBursts::11 6551 # Per bank write bursts +system.physmem.perBankWrBursts::12 6595 # Per bank write bursts +system.physmem.perBankWrBursts::13 6390 # Per bank write bursts +system.physmem.perBankWrBursts::14 6535 # Per bank write bursts +system.physmem.perBankWrBursts::15 6575 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2616532122000 # Total gap between requests +system.physmem.totGap 2616547722000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15335424 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152617 # Read request sizes (log2) +system.physmem.readPktSize::6 152619 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57909 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1247001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2684241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2677986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2686359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 161 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57911 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1246677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1099488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1103361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2684438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2678406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2686634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 54458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20429 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 160 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,28 +156,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4864 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4863 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4863 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4862 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -188,453 +188,464 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11133.405772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1028.811660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16712.159564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23202 25.87% 25.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14564 16.24% 42.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2857 3.19% 45.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2044 2.28% 47.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1359 1.52% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1218 1.36% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 957 1.07% 51.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1129 1.26% 52.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 646 0.72% 53.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 589 0.66% 54.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 513 0.57% 54.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 690 0.77% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 338 0.38% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 262 0.29% 56.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 213 0.24% 56.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 156 0.17% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 151 0.17% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 136 0.15% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 156 0.17% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 102 0.11% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2292 2.56% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 63 0.07% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 60 0.07% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 44 0.05% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 30 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 303 0.34% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 33 0.04% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.01% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 97 0.11% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 22 0.02% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 14 0.02% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 28 0.03% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 19 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 14 0.02% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 14 0.02% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 9 0.01% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 370 0.41% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 11 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 17 0.02% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 15 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 14 0.02% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 12 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 37 0.04% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 13 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 11 0.01% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 225 0.25% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 10 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 165 0.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 83 0.09% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 88 0.10% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 435 0.49% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 9 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 6 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 9 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 26 0.03% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 67 0.07% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 280 0.31% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 72 0.08% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 269 0.30% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 83 0.09% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 89706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11129.630393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1027.657053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16709.623735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23265 25.93% 25.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14539 16.21% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2841 3.17% 45.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2049 2.28% 47.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1384 1.54% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1206 1.34% 50.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 956 1.07% 51.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1124 1.25% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 653 0.73% 53.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 549 0.61% 54.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 562 0.63% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 672 0.75% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 328 0.37% 55.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 247 0.28% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 203 0.23% 56.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 737 0.82% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 166 0.19% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 147 0.16% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 151 0.17% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 100 0.11% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2290 2.55% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 54 0.06% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 47 0.05% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 132 0.15% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 20 0.02% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 30 0.03% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 15 0.02% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 101 0.11% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 16 0.02% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 24 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 89 0.10% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 22 0.02% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 154 0.17% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 15 0.02% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 13 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 380 0.42% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 15 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 13 0.01% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 16 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 17 0.02% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 10 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 98 0.11% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 14 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 34 0.04% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 92 0.10% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 11 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 10 0.01% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 228 0.25% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 8 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 164 0.18% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 10 0.01% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 80 0.09% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 9 0.01% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 8 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 90 0.10% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 9 0.01% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 436 0.49% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 7 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 68 0.08% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 11 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 70 0.08% 65.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 270 0.30% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 82 0.09% 65.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6791 3 0.00% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 142 0.16% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 2 0.00% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 412 0.46% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.09% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 29 0.03% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 143 0.16% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 1 0.00% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 2 0.00% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 411 0.46% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 87 0.10% 66.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 21 0.02% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 66.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 77 0.09% 66.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 78 0.09% 66.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 401 0.45% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 24 0.03% 66.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 82 0.09% 66.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 407 0.45% 67.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 149 0.17% 67.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 402 0.45% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 81 0.09% 66.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 23 0.03% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 84 0.09% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 405 0.45% 67.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 148 0.16% 67.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::9728-9735 87 0.10% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 18 0.02% 67.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 20 0.02% 67.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::10240-10247 273 0.30% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 68 0.08% 68.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 146 0.16% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 19 0.02% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 68.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 69 0.08% 68.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 145 0.16% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 1 0.00% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 18 0.02% 68.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 6 0.01% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 429 0.48% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 85 0.09% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 79 0.09% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 7 0.01% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 431 0.48% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 83 0.09% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 80 0.09% 68.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::12160-12167 2 0.00% 69.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::12288-12295 208 0.23% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 83 0.09% 69.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 89 0.10% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 144 0.16% 69.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 350 0.39% 70.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 2 0.00% 70.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 146 0.16% 70.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 72 0.08% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 82 0.09% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 280 0.31% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 93 0.10% 70.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 70.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 92 0.10% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 1 0.00% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 13 0.01% 70.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 4 0.00% 70.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 493 0.55% 71.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 74 0.08% 71.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 2 0.00% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 141 0.16% 71.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 76 0.08% 71.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 534 0.60% 72.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 75 0.08% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 148 0.17% 72.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 79 0.09% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 3 0.00% 69.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 82 0.09% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 88 0.10% 69.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 148 0.16% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 354 0.39% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 2 0.00% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 141 0.16% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13639 1 0.00% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 73 0.08% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 83 0.09% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14279 1 0.00% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 279 0.31% 70.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 93 0.10% 70.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 70.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 91 0.10% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 15 0.02% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 4 0.00% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 490 0.55% 71.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 72 0.08% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 2 0.00% 71.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 143 0.16% 71.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 77 0.09% 71.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 10 0.01% 71.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 534 0.60% 72.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 75 0.08% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 145 0.16% 72.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 76 0.08% 72.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::17280-17287 3 0.00% 72.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::17408-17415 492 0.55% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 15 0.02% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 73.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 16 0.02% 73.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 2 0.00% 73.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 100 0.11% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 2 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 274 0.31% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 95 0.11% 73.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 275 0.31% 73.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 80 0.09% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 72 0.08% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 144 0.16% 74.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 3 0.00% 74.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 2 0.00% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 350 0.39% 74.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 81 0.09% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 73 0.08% 74.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 143 0.16% 74.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 1 0.00% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 347 0.39% 74.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::19584-19591 2 0.00% 74.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 134 0.15% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 136 0.15% 74.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 89 0.10% 74.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 88 0.10% 74.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 82 0.09% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 84 0.09% 74.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::20352-20359 5 0.01% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 2 0.00% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 211 0.24% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 216 0.24% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20551 1 0.00% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 82 0.09% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 2 0.00% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 418 0.47% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 17 0.02% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 143 0.16% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22215 1 0.00% 76.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 76 0.08% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 5 0.01% 76.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 24 0.03% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 79 0.09% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 5 0.01% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 419 0.47% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 21 0.02% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 147 0.16% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 72 0.08% 76.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 4 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 265 0.30% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 21 0.02% 76.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::23040-23047 84 0.09% 76.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 139 0.16% 76.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 3 0.00% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 413 0.46% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 81 0.09% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 25 0.03% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 79 0.09% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 398 0.44% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 141 0.16% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 5 0.01% 76.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 410 0.46% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 87 0.10% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 18 0.02% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 80 0.09% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 395 0.44% 78.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 75 0.08% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 20 0.02% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 86 0.10% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 3 0.00% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 76 0.08% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 19 0.02% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 88 0.10% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 78.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 89 0.10% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25927 2 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 88 0.10% 78.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 21 0.02% 78.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 20 0.02% 78.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::26496-26503 3 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 271 0.30% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 2 0.00% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 70 0.08% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 141 0.16% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 22 0.02% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 415 0.46% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 1 0.00% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 83 0.09% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 2 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 75 0.08% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 159 0.18% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 210 0.23% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 77 0.09% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 347 0.39% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 141 0.16% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 71 0.08% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 80 0.09% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 2 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 274 0.31% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 90 0.10% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 17 0.02% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 485 0.54% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 77 0.09% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 143 0.16% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 84 0.09% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 538 0.60% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 2 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 86 0.10% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 150 0.17% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 80 0.09% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 484 0.54% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 12 0.01% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 69 0.08% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 144 0.16% 79.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 23 0.03% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 414 0.46% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 80 0.09% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 2 0.00% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 76 0.08% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 158 0.18% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 213 0.24% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 78 0.09% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 137 0.15% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 346 0.39% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 142 0.16% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 72 0.08% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 82 0.09% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 276 0.31% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 88 0.10% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 20 0.02% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 482 0.54% 82.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 73 0.08% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 142 0.16% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.09% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32704-32711 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 535 0.60% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 89 0.10% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 149 0.17% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 76 0.08% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 481 0.54% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 15 0.02% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 88 0.10% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 94 0.10% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34624-34631 3 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 264 0.29% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 79 0.09% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 2 0.00% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 71 0.08% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35392-35399 1 0.00% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.42% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 86 0.10% 86.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 78 0.09% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 204 0.23% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 155 0.17% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 74 0.08% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37575 2 0.00% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 89 0.10% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 419 0.47% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 79 0.09% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 207 0.23% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37056-37063 1 0.00% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 154 0.17% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 75 0.08% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 87 0.10% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 418 0.47% 87.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 18 0.02% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 140 0.16% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 2 0.00% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 266 0.30% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 19 0.02% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 88 0.10% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 20 0.02% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38208-38215 1 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 142 0.16% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 267 0.30% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 18 0.02% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 85 0.09% 87.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 145 0.16% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 410 0.46% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 83 0.09% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 2 0.00% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 17 0.02% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 397 0.44% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 75 0.08% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.24% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 79 0.09% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 395 0.44% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 17 0.02% 89.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::41600-41607 3 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 83 0.09% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 408 0.45% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 140 0.16% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 25 0.03% 90.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 2 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 89 0.10% 89.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 405 0.45% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42048-42055 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 142 0.16% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 22 0.02% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 265 0.30% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 73 0.08% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 142 0.16% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 17 0.02% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 418 0.47% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 82 0.09% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 69 0.08% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 144 0.16% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 21 0.02% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 417 0.46% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 79 0.09% 91.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::44544-44551 77 0.09% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 156 0.17% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 198 0.22% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 81 0.09% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 90 0.10% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 154 0.17% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 203 0.23% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 82 0.09% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 88 0.10% 91.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 133 0.15% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 135 0.15% 92.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::45952-45959 2 0.00% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 350 0.39% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 348 0.39% 92.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 72 0.08% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 3 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 83 0.09% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 73 0.08% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 84 0.09% 92.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 266 0.30% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 97 0.11% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 5 0.01% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 17 0.02% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 515 0.57% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 100 0.11% 94.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 142 0.16% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89676 # Bytes accessed per row activation -system.physmem.totQLat 373682624750 # Total ticks spent queuing -system.physmem.totMemAccLat 469595819750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77465315000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18447880000 # Total ticks spent accessing banks -system.physmem.avgQLat 24119.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1190.72 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::47104-47111 268 0.30% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 92 0.10% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 511 0.57% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 2 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 90 0.10% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 140 0.16% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 6 0.01% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 6 0.01% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5078 5.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89706 # Bytes accessed per row activation +system.physmem.totQLat 373696644500 # Total ticks spent queuing +system.physmem.totMemAccLat 469604897000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77464855000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18443397500 # Total ticks spent accessing banks +system.physmem.avgQLat 24120.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1190.44 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30310.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30310.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s @@ -643,45 +654,45 @@ system.physmem.busUtil 2.98 # Da system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 15419173 # Number of row buffer hits during reads -system.physmem.writeRowHits 91146 # Number of row buffer hits during writes +system.physmem.avgWrQLen 14.55 # Average write queue length when enqueuing +system.physmem.readRowHits 15419069 # Number of row buffer hits during reads +system.physmem.writeRowHits 91147 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes -system.physmem.avgGap 160458.16 # Average gap between requests -system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.writeRowHitRate 85.21 # Row buffer hit rate for writes +system.physmem.avgGap 160459.07 # Average gap between requests +system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54116538 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546563 # Transaction distribution -system.membus.trans_dist::ReadResp 16546563 # Transaction distribution -system.membus.trans_dist::WriteReq 763368 # Transaction distribution -system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57909 # Transaction distribution +system.membus.throughput 54116372 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546597 # Transaction distribution +system.membus.trans_dist::ReadResp 16546597 # Transaction distribution +system.membus.trans_dist::WriteReq 763385 # Transaction distribution +system.membus.trans_dist::WriteResp 763385 # Transaction distribution +system.membus.trans_dist::Writeback 57911 # Transaction distribution system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132216 # Transaction distribution -system.membus.trans_dist::ReadExResp 132216 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 132218 # Transaction distribution +system.membus.trans_dist::ReadExResp 132218 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893537 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893543 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280493 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951233 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951341 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914505 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914914 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141597897 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141597897 # Total data (bytes) +system.membus.tot_pkt_size::total 141598306 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141598306 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206226000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -689,11 +700,11 @@ system.membus.reqLayer2.occupancy 3614000 # La system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910622000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910626500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950375335 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950468826 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34635984750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -701,12 +712,12 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47801275 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution -system.iobus.trans_dist::WriteReq 8166 # Transaction distribution -system.iobus.trans_dist::WriteResp 8166 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.throughput 47801049 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution +system.iobus.trans_dist::WriteReq 8183 # Transaction distribution +system.iobus.trans_dist::WriteResp 8183 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) @@ -729,11 +740,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 33053936 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) @@ -756,12 +767,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390542 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073781 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 125073934 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073934 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -809,9 +820,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42035727250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -837,9 +848,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995647 # DTB read hits +system.cpu.dtb.read_hits 14996193 # DTB read hits system.cpu.dtb.read_misses 7334 # DTB read misses -system.cpu.dtb.write_hits 11230146 # DTB write hits +system.cpu.dtb.write_hits 11230326 # DTB write hits system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -850,12 +861,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002981 # DTB read accesses -system.cpu.dtb.write_accesses 11232358 # DTB write accesses +system.cpu.dtb.read_accesses 15003527 # DTB read accesses +system.cpu.dtb.write_accesses 11232538 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26225793 # DTB hits +system.cpu.dtb.hits 26226519 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 26235339 # DTB accesses +system.cpu.dtb.accesses 26236065 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -877,7 +888,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61491413 # ITB inst hits +system.cpu.itb.inst_hits 61494253 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -894,88 +905,88 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495884 # ITB inst accesses -system.cpu.itb.hits 61491413 # DTB hits +system.cpu.itb.inst_accesses 61498724 # ITB inst accesses +system.cpu.itb.hits 61494253 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495884 # DTB accesses -system.cpu.numCycles 5233072966 # number of cpu cycles simulated +system.cpu.itb.accesses 61498724 # DTB accesses +system.cpu.numCycles 5233104166 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197590 # Number of instructions committed -system.cpu.committedOps 76603983 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69206189 # Number of integer alu accesses +system.cpu.committedInsts 60200379 # Number of instructions committed +system.cpu.committedOps 76607188 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69208982 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140403 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948249 # number of instructions that are conditional controls -system.cpu.num_int_insts 69206189 # number of integer instructions +system.cpu.num_func_calls 2140473 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948700 # number of instructions that are conditional controls +system.cpu.num_int_insts 69208982 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 401354573 # number of times the integer registers were read -system.cpu.num_int_register_writes 74515956 # number of times the integer registers were written +system.cpu.num_int_register_reads 401369988 # number of times the integer registers were read +system.cpu.num_int_register_writes 74519463 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393282 # number of memory refs -system.cpu.num_load_insts 15659729 # Number of load instructions -system.cpu.num_store_insts 11733553 # Number of store instructions -system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles -system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles -system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875495 # Percentage of idle cycles -system.cpu.Branches 10308279 # Number of branches fetched +system.cpu.num_mem_refs 27394064 # number of memory refs +system.cpu.num_load_insts 15660288 # Number of load instructions +system.cpu.num_store_insts 11733776 # Number of store instructions +system.cpu.num_idle_cycles 4581523252.608249 # Number of idle cycles +system.cpu.num_busy_cycles 651580913.391751 # Number of busy cycles +system.cpu.not_idle_fraction 0.124511 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875489 # Percentage of idle cycles +system.cpu.Branches 10308817 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed system.cpu.icache.tags.replacements 856260 # number of replacements -system.cpu.icache.tags.tagsinuse 510.868407 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 510.867590 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60637481 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.868407 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.icache.tags.avg_refs 70.774350 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19998571250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.867590 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997788 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997788 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62348185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62348185 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60634641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60634641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60634641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60634641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60634641 # number of overall hits -system.cpu.icache.overall_hits::total 60634641 # number of overall hits +system.cpu.icache.tags.tag_accesses 62351025 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62351025 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60637481 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60637481 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60637481 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60637481 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60637481 # number of overall hits +system.cpu.icache.overall_hits::total 60637481 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses system.cpu.icache.overall_misses::total 856772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774021000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11774021000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11774021000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11774021000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11774021000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11774021000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774299750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11774299750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11774299750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11774299750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11774299750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11774299750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61494253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61494253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61494253 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61494253 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61494253 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61494253 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.303670 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13742.303670 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13742.303670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13742.303670 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.629019 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13742.629019 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13742.629019 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13742.629019 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -990,12 +1001,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856772 system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10056430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10056430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056430000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10056430000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056704250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056704250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056704250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056704250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056704250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056704250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435943750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435943750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435943750 # number of overall MSHR uncacheable cycles @@ -1006,34 +1017,34 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.580126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.580126 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.900223 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.900223 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62509 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50754.656257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37718.394097 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62511 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50754.773862 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1682280 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127893 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.153808 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2565659385000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.578019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884348 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400068 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977018 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.361988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.948805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106710 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.774456 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id @@ -1044,15 +1055,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6898 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56267 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17137304 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17137304 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 17137404 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17137404 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 369631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226419 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595233 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595233 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226424 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595238 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595238 # 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miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses @@ -1133,37 +1144,37 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025851 system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991138 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991138 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541331 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541331 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541335 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541335 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # 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number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses @@ -1227,37 +1238,37 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541331 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541331 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541335 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541335 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103227 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103228 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103228 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58568.351441 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62600.316036 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60504.889466 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58593.930090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62701.498624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60566.810450 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59371.424247 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59371.424247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59379.438498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59379.438498 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1267,13 +1278,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626139 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.876590 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 626146 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.876591 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23656108 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626658 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.749631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 664772250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.876590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.876591 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1281,54 +1292,54 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97755015 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97755015 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972594 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972594 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 97757722 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97757722 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13196248 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196248 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972755 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972755 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236393 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236393 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168335 # number of overall hits -system.cpu.dcache.overall_hits::total 23168335 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368054 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368054 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250145 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250145 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 23169003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23169003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23169003 # number of overall hits +system.cpu.dcache.overall_hits::total 23169003 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250147 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618199 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses -system.cpu.dcache.overall_misses::total 618199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5415523000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5415523000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621830515 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11621830515 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158390000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158390000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17037353515 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17037353515 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17037353515 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17037353515 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 618206 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618206 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618206 # number of overall misses +system.cpu.dcache.overall_misses::total 618206 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416606500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5416606500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11623055265 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11623055265 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158362000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158362000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17039661765 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17039661765 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17039661765 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17039661765 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564307 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564307 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222902 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222902 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23786534 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23786534 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23786534 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23786534 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787209 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787209 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787209 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787209 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027134 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027134 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses @@ -1337,16 +1348,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.935999 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.935999 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46460.375042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46460.375042 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13910.943264 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13910.943264 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27559.658807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27559.658807 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14716.679934 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14716.679934 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46464.899699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46464.899699 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13908.484103 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13908.484103 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27563.080535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27563.080535 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1355,36 +1366,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595233 # number of writebacks -system.cpu.dcache.writebacks::total 595233 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368054 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368054 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250145 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 595238 # number of writebacks +system.cpu.dcache.writebacks::total 595238 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250147 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618199 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677118000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677118000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069604485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069604485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135564000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135564000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15746722485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15746722485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15746722485 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15746722485 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050737750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050737750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284890100 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284890100 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 618206 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618206 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618206 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618206 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678192500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678192500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11070820735 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11070820735 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135536000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135536000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15749013235 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15749013235 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15749013235 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15749013235 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058328250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058328250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26237936841 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26237936841 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208296265091 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208296265091 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027134 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027134 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses @@ -1393,16 +1404,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12707.695066 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12707.695066 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44252.751344 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44252.751344 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11906.200597 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11906.200597 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12710.441804 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12710.441804 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44257.259671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44257.259671 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11903.741437 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11903.741437 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1410,33 +1421,33 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965212 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution +system.cpu.toL2Bus.throughput 52965248 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 595238 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247213 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749353 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749474 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514534 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614893 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615814 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138419097 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138419097 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138420018 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138420018 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008588500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3008633500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295451750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295454000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534384415 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534439174 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1458,10 +1469,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1538393065750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1538393065750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1538398399250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1538398399250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 4226653cc..e35c391b5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810269000 # Number of ticks simulated -final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332812 # Number of seconds simulated +sim_ticks 2332811899500 # Number of ticks simulated +final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1221068 # Simulator instruction rate (inst/s) -host_op_rate 1570218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47154151043 # Simulator tick rate (ticks/s) -host_mem_usage 421264 # Number of bytes of host memory used -host_seconds 49.47 # Real time elapsed on the host -sim_insts 60408649 # Number of instructions simulated -sim_ops 77681829 # Number of ops (including micro ops) simulated +host_inst_rate 1003640 # Simulator instruction rate (inst/s) +host_op_rate 1290613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38755909714 # Simulator tick rate (ticks/s) +host_mem_usage 421296 # Number of bytes of host memory used +host_seconds 60.19 # Real time elapsed on the host +sim_insts 60411489 # Number of instructions simulated +sim_ops 77685090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 492744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6494808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 212416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2577132 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 492744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 212416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6490328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2581740 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450892 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1405784 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1610060 # Number of bytes written to this memory -system.physmem.bytes_written::total 6718884 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1610064 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719076 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 101517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3319 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 40278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118198 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 351446 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 402515 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811821 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 13912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 101447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 40350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118200 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 351445 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 402516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811824 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2784113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 91056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1104733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 91056 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 211251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2782191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 91028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1106707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52062017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 211251 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 91028 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587373 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 602614 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 690180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 602612 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 690182 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3386727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 211251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3384803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1796889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942264 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -76,31 +76,31 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969581 # Throughput (bytes/s) -system.membus.data_through_bus 130566414 # Total data (bytes) +system.membus.throughput 55969745 # Throughput (bytes/s) +system.membus.data_through_bus 130566887 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62242 # number of replacements -system.l2c.tags.tagsinuse 50006.300115 # Cycle average of tags in use -system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.571374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor +system.l2c.tags.replacements 62244 # number of replacements +system.l2c.tags.tagsinuse 50006.487761 # Cycle average of tags in use +system.l2c.tags.total_refs 1678458 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127629 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151071 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.766383 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993822 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4917.298409 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3152.525305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2097.421521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2936.495752 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4918.263908 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3149.549186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2096.452041 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2939.468488 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563061 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.031989 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044853 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763038 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id @@ -111,132 +111,132 @@ system.l2c.tags.age_task_id_blocks_1024::3 9187 # system.l2c.tags.age_task_id_blocks_1024::4 52391 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17104735 # Number of tag accesses -system.l2c.tags.data_accesses 17104735 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 473132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 196968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 365739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169796 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1224842 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 592682 # number of Writeback hits -system.l2c.Writeback_hits::total 592682 # number of Writeback hits +system.l2c.tags.tag_accesses 17104555 # Number of tag accesses +system.l2c.tags.data_accesses 17104555 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 473060 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 196973 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4855 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2031 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 365811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 169795 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1224812 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592687 # number of Writeback hits +system.l2c.Writeback_hits::total 592687 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63334 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50404 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 63344 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 50394 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9005 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 473132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 260302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4875 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 365739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 220200 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338580 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9005 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3277 # number of overall hits -system.l2c.overall_hits::cpu0.inst 473132 # number of overall hits -system.l2c.overall_hits::cpu0.data 260302 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4875 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2050 # number of overall hits -system.l2c.overall_hits::cpu1.inst 365739 # number of overall hits -system.l2c.overall_hits::cpu1.data 220200 # number of overall hits -system.l2c.overall_hits::total 1338580 # number of overall hits +system.l2c.demand_hits::cpu0.dtb.walker 9008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 473060 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 260317 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4855 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2031 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 365811 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 220189 # number of demand (read+write) hits +system.l2c.demand_hits::total 1338550 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9008 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3279 # number of overall hits +system.l2c.overall_hits::cpu0.inst 473060 # number of overall hits +system.l2c.overall_hits::cpu0.data 260317 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4855 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2031 # number of overall hits +system.l2c.overall_hits::cpu1.inst 365811 # number of overall hits +system.l2c.overall_hits::cpu1.data 220189 # number of overall hits +system.l2c.overall_hits::total 1338550 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5807 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3319 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4065 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7286 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5804 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3318 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4068 # number of ReadReq misses system.l2c.ReadReq_misses::total 20481 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1520 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1399 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1525 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1394 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 96488 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 36984 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133472 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 96422 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 37052 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133474 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 102295 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3319 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 41049 # number of demand (read+write) misses -system.l2c.demand_misses::total 153953 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7286 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 102226 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3318 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 41120 # number of demand (read+write) misses +system.l2c.demand_misses::total 153955 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7285 # number of overall misses -system.l2c.overall_misses::cpu0.data 102295 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3319 # number of overall misses -system.l2c.overall_misses::cpu1.data 41049 # number of overall misses -system.l2c.overall_misses::total 153953 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9007 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3280 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 480417 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 202775 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4875 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2050 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 369058 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173861 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1245323 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 592682 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 592682 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1532 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 7286 # number of overall misses +system.l2c.overall_misses::cpu0.data 102226 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3318 # number of overall misses +system.l2c.overall_misses::cpu1.data 41120 # number of overall misses +system.l2c.overall_misses::total 153955 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9010 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3282 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 480346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 202777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4855 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 369129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 173863 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1245293 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592687 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592687 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1537 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1408 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 159822 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 87388 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247210 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9007 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3280 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 480417 # 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number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015164 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028638 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008993 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023381 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992167 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990092 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000914 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015168 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028623 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008989 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.023398 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016447 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992193 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990057 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.603722 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.423216 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539913 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.603520 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.423713 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539917 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015164 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.282118 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157126 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000914 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015168 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008989 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.157362 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103152 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015164 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.282118 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157126 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000914 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015168 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008989 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.157362 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103152 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57860 # number of writebacks -system.l2c.writebacks::total 57860 # number of writebacks +system.l2c.writebacks::writebacks 57863 # number of writebacks +system.l2c.writebacks::total 57863 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -254,11 +254,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59119271 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137914042 # Total data (bytes) +system.toL2Bus.throughput 59119535 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137914755 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 48895252 # Throughput (bytes/s) -system.iobus.data_through_bus 114063346 # Total data (bytes) +system.iobus.throughput 48895283 # Throughput (bytes/s) +system.iobus.data_through_bus 114063499 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -282,25 +282,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7929199 # DTB read hits -system.cpu0.dtb.read_misses 6444 # DTB read misses -system.cpu0.dtb.write_hits 6437089 # DTB write hits +system.cpu0.dtb.read_hits 7929658 # DTB read hits +system.cpu0.dtb.read_misses 6455 # DTB read misses +system.cpu0.dtb.write_hits 6435419 # DTB write hits system.cpu0.dtb.write_misses 1929 # DTB write misses system.cpu0.dtb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5568 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5575 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7935643 # DTB read accesses -system.cpu0.dtb.write_accesses 6439018 # DTB write accesses +system.cpu0.dtb.read_accesses 7936113 # DTB read accesses +system.cpu0.dtb.write_accesses 6437348 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14366288 # DTB hits -system.cpu0.dtb.misses 8373 # DTB misses -system.cpu0.dtb.accesses 14374661 # DTB accesses +system.cpu0.dtb.hits 14365077 # DTB hits +system.cpu0.dtb.misses 8384 # DTB misses +system.cpu0.dtb.accesses 14373461 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -322,62 +322,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32543256 # ITB inst hits -system.cpu0.itb.inst_misses 3703 # ITB inst misses +system.cpu0.itb.inst_hits 32541992 # ITB inst hits +system.cpu0.itb.inst_misses 3717 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32546959 # ITB inst accesses -system.cpu0.itb.hits 32543256 # DTB hits -system.cpu0.itb.misses 3703 # DTB misses -system.cpu0.itb.accesses 32546959 # DTB accesses -system.cpu0.numCycles 4633654699 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32545709 # ITB inst accesses +system.cpu0.itb.hits 32541992 # DTB hits +system.cpu0.itb.misses 3717 # DTB misses +system.cpu0.itb.accesses 32545709 # DTB accesses +system.cpu0.numCycles 4625561989 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31998107 # Number of instructions committed -system.cpu0.committedOps 41901559 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37244533 # Number of integer alu accesses +system.cpu0.committedInsts 31996828 # Number of instructions committed +system.cpu0.committedOps 41898003 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37241416 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses -system.cpu0.num_func_calls 1207172 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4285554 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37244533 # number of integer instructions +system.cpu0.num_func_calls 1207166 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4285035 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37241416 # number of integer instructions system.cpu0.num_fp_insts 5364 # number of float instructions -system.cpu0.num_int_register_reads 192529528 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39716026 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192512823 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39713188 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu0.num_mem_refs 15013044 # number of memory refs -system.cpu0.num_load_insts 8304661 # Number of load instructions -system.cpu0.num_store_insts 6708383 # Number of store instructions -system.cpu0.num_idle_cycles 4553702806.473283 # Number of idle cycles -system.cpu0.num_busy_cycles 79951892.526717 # Number of busy cycles -system.cpu0.not_idle_fraction 0.017255 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.982745 # Percentage of idle cycles -system.cpu0.Branches 5613939 # Number of branches fetched +system.cpu0.num_mem_refs 15011832 # number of memory refs +system.cpu0.num_load_insts 8305325 # Number of load instructions +system.cpu0.num_store_insts 6706507 # Number of store instructions +system.cpu0.num_idle_cycles 4549718927.235470 # Number of idle cycles +system.cpu0.num_busy_cycles 75843061.764530 # Number of busy cycles +system.cpu0.not_idle_fraction 0.016397 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.983603 # Percentage of idle cycles +system.cpu0.Branches 5613326 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 850590 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60586338 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.509134 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.169458 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868182 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131190 # Average percentage of cache occupancy +system.cpu0.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.500524 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.177938 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868165 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131207 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id @@ -385,44 +385,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 78 system.cpu0.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62285702 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62285702 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32064740 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28518758 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32064740 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28518758 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60583498 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32064740 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 28518758 # number of overall hits -system.cpu0.icache.overall_hits::total 60583498 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 481295 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 369807 # number of ReadReq misses +system.cpu0.icache.tags.tag_accesses 62288542 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62288542 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 32063555 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28522783 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60586338 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32063555 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28522783 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60586338 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32063555 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28522783 # number of overall hits +system.cpu0.icache.overall_hits::total 60586338 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 481227 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 369875 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 851102 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 481295 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 369807 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 481227 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 369875 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 851102 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 481295 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 369807 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 481227 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 369875 # number of overall misses system.cpu0.icache.overall_misses::total 851102 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32546035 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 28888565 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32546035 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 28888565 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32546035 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 28888565 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014788 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012801 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014788 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012801 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014788 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012801 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32544782 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 28892658 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32544782 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 28892658 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32544782 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 28892658 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014787 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012802 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014787 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012802 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014787 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012802 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,90 +432,90 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623334 # number of replacements +system.cpu0.dcache.tags.replacements 623340 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628286 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875190 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23628946 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623852 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875884 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298836 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698194 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291431 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705599 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881429 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118566 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97632374 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97632374 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6995580 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6184442 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13180022 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5776847 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4185218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9962065 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139292 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96744 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 97635044 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97635044 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6996051 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6184470 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13180521 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5775160 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4187066 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9962226 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139339 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96697 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145938 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101280 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145986 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101232 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247218 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12772427 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10369660 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23142087 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12772427 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10369660 # number of overall hits -system.cpu0.dcache.overall_hits::total 23142087 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 196128 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 169325 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 365453 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 161354 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 88801 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250155 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6647 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12771211 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10371536 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23142747 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12771211 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10371536 # number of overall hits +system.cpu0.dcache.overall_hits::total 23142747 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 196129 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 169328 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 365457 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 161303 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 88854 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250157 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6648 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4535 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 357482 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 258126 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 615608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 357482 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 258126 # number of overall misses -system.cpu0.dcache.overall_misses::total 615608 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7191708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353767 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13545475 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938201 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274019 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10212220 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145939 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101280 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 357432 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 258182 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 615614 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 357432 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 258182 # number of overall misses +system.cpu0.dcache.overall_misses::total 615614 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7192180 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353798 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13545978 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5936463 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275920 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10212383 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101232 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145938 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101280 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145986 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101232 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13129909 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10627786 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23757695 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13129909 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10627786 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23757695 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027271 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 13128643 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10629718 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23758361 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13128643 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10629718 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23758361 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027270 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020777 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024496 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045546 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044787 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020780 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045538 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044798 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027227 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024288 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027227 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024288 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027225 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024289 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025911 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027225 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024289 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.025911 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,8 +524,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 592682 # number of writebacks -system.cpu0.dcache.writebacks::total 592682 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 592687 # number of writebacks +system.cpu0.dcache.writebacks::total 592687 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -550,25 +550,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7038606 # DTB read hits -system.cpu1.dtb.read_misses 4220 # DTB read misses -system.cpu1.dtb.write_hits 4778915 # DTB write hits -system.cpu1.dtb.write_misses 1252 # DTB write misses +system.cpu1.dtb.read_hits 7038699 # DTB read hits +system.cpu1.dtb.read_misses 4194 # DTB read misses +system.cpu1.dtb.write_hits 4780763 # DTB write hits +system.cpu1.dtb.write_misses 1254 # DTB write misses system.cpu1.dtb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2946 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2928 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 80 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7042826 # DTB read accesses -system.cpu1.dtb.write_accesses 4780167 # DTB write accesses +system.cpu1.dtb.read_accesses 7042893 # DTB read accesses +system.cpu1.dtb.write_accesses 4782017 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11817521 # DTB hits -system.cpu1.dtb.misses 5472 # DTB misses -system.cpu1.dtb.accesses 11822993 # DTB accesses +system.cpu1.dtb.hits 11819462 # DTB hits +system.cpu1.dtb.misses 5448 # DTB misses +system.cpu1.dtb.accesses 11824910 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -590,50 +590,50 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28886889 # ITB inst hits -system.cpu1.itb.inst_misses 2463 # ITB inst misses +system.cpu1.itb.inst_hits 28890998 # ITB inst hits +system.cpu1.itb.inst_misses 2444 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1658 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1642 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28889352 # ITB inst accesses -system.cpu1.itb.hits 28886889 # DTB hits -system.cpu1.itb.misses 2463 # DTB misses -system.cpu1.itb.accesses 28889352 # DTB accesses -system.cpu1.numCycles 4277971820 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 28893442 # ITB inst accesses +system.cpu1.itb.hits 28890998 # DTB hits +system.cpu1.itb.misses 2444 # DTB misses +system.cpu1.itb.accesses 28893442 # DTB accesses +system.cpu1.numCycles 4282034895 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28410542 # Number of instructions committed -system.cpu1.committedOps 35780270 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31886228 # Number of integer alu accesses +system.cpu1.committedInsts 28414661 # Number of instructions committed +system.cpu1.committedOps 35787087 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 31892138 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses -system.cpu1.num_func_calls 928836 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3656561 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31886228 # number of integer instructions +system.cpu1.num_func_calls 928912 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3657531 # number of instructions that are conditional controls +system.cpu1.num_int_insts 31892138 # number of integer instructions system.cpu1.num_fp_insts 4905 # number of float instructions -system.cpu1.num_int_register_reads 163367229 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34722740 # number of times the integer registers were written +system.cpu1.num_int_register_reads 163397724 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34729085 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu1.num_mem_refs 12348595 # number of memory refs -system.cpu1.num_load_insts 7334868 # Number of load instructions -system.cpu1.num_store_insts 5013727 # Number of store instructions -system.cpu1.num_idle_cycles 4215699127.014197 # Number of idle cycles -system.cpu1.num_busy_cycles 62272692.985803 # Number of busy cycles -system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles -system.cpu1.Branches 4684784 # Number of branches fetched +system.cpu1.num_mem_refs 12350589 # number of memory refs +system.cpu1.num_load_insts 7334763 # Number of load instructions +system.cpu1.num_store_insts 5015826 # Number of store instructions +system.cpu1.num_idle_cycles 4212351630.069436 # Number of idle cycles +system.cpu1.num_busy_cycles 69683264.930565 # Number of busy cycles +system.cpu1.not_idle_fraction 0.016273 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.983727 # Percentage of idle cycles +system.cpu1.Branches 4685935 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements |