diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-01-15 15:30:34 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-01-15 15:30:34 -0800 |
| commit | 6fb521faba37a47ebce2aebb08ac34bd69d29f13 (patch) | |
| tree | e8ba62a0f428fdcb8bb73971dddd5079583f32fd /tests | |
| parent | 371603f12c901df748bdb9d75ea10660bc876e1f (diff) | |
| download | gem5-6fb521faba37a47ebce2aebb08ac34bd69d29f13.tar.xz | |
SPARC: Update stats for the call r15 as source change.
Diffstat (limited to 'tests')
6 files changed, 1715 insertions, 1714 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index d8970ec96..f21f452d2 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 2 2010 15:11:52 -M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase -M5 started Dec 3 2010 12:08:56 -M5 executing on zizzer +M5 compiled Jan 15 2011 04:38:18 +M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip +M5 started Jan 15 2011 04:38:23 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 601459170500 because target called exit() +Exiting @ tick 601459117000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 212079086..1f89fda21 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 193964 # Simulator instruction rate (inst/s) -host_mem_usage 208068 # Number of bytes of host memory used -host_seconds 7246.73 # Real time elapsed on the host -host_tick_rate 82997346 # Simulator tick rate (ticks/s) +host_inst_rate 115319 # Simulator instruction rate (inst/s) +host_mem_usage 220936 # Number of bytes of host memory used +host_seconds 12188.85 # Real time elapsed on the host +host_tick_rate 49345009 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.601459 # Number of seconds simulated -sim_ticks 601459170500 # Number of ticks simulated +sim_ticks 601459117000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 98804477 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 100538318 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 98804472 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 100538302 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 5348297 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 105813048 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 105813048 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 105813027 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 105813027 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 21327804 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 21327805 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1172142474 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1172142381 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 418030495 35.66% 35.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 498323128 42.51% 78.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 52996990 4.52% 82.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 103673808 8.84% 91.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 418030405 35.66% 35.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 498323124 42.51% 78.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 52996988 4.52% 82.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 103673812 8.84% 91.54% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::4 32915552 2.81% 94.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 8294277 0.71% 95.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8294276 0.71% 95.06% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 10946218 0.93% 98.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 21327804 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 10946217 0.93% 98.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 21327805 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1172142474 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1172142381 # Number of insts commited each cycle system.cpu.commit.COM:count 1489523295 # Number of instructions committed system.cpu.commit.COM:loads 402512844 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed @@ -44,22 +44,22 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 5348297 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 219358956 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 219358890 # The number of squashed insts skipped by commit system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated system.cpu.cpi 0.855802 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.855802 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 295702053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14658.341236 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.553744 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_accesses 295702052 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14658.314544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.427114 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 294883757 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11994862000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 11994825500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 818296 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses 818295 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 604804 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1593836000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1593801500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 213492 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 213491 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency @@ -83,127 +83,127 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # m system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 955.149583 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 955.151567 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 462548869 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15269.190131 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10449.986812 # average overall mshr miss latency +system.cpu.dcache.demand_accesses 462548868 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 15269.181916 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency system.cpu.dcache.demand_hits 459964335 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 39463741045 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 39463704545 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2584534 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2584533 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 2102977 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5032264299 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5032229799 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 481557 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 481556 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.424423 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 462548869 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15269.190131 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10449.986812 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4095.424477 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 462548868 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 15269.181916 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 459964335 # number of overall hits -system.cpu.dcache.overall_miss_latency 39463741045 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 39463704545 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2584534 # number of overall misses +system.cpu.dcache.overall_misses 2584533 # number of overall misses system.cpu.dcache.overall_mshr_hits 2102977 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5032264299 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5032229799 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 481557 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 481556 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 477468 # number of replacements -system.cpu.dcache.sampled_refs 481564 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 477467 # number of replacements +system.cpu.dcache.sampled_refs 481563 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.424423 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.424477 # Cycle average of tags in use system.cpu.dcache.total_refs 459965654 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 132275000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428419 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 393632662 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1750743114 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 405697797 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 351108016 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 30410707 # Number of cycles decode is squashing +system.cpu.dcache.warmup_cycle 132267000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 428418 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 393632591 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1750743071 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 405697785 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 351108006 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 30410701 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 21703388 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 105813048 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 173096808 # Number of cache lines fetched -system.cpu.fetch.Cycles 548235409 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1429410 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1755979749 # Number of instructions fetch has processed +system.cpu.fetch.Branches 105813027 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 173096803 # Number of cache lines fetched +system.cpu.fetch.Cycles 548235394 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1429408 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1755979705 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 6170644 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 173096808 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 98804477 # Number of branches that fetch has predicted taken +system.cpu.fetch.icacheStallCycles 173096803 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 98804472 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1202552570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 1202552471 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.464003 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 827414016 68.80% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82887160 6.89% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45822502 3.81% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22740112 1.89% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 827413927 68.80% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 82887157 6.89% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45822503 3.81% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22740108 1.89% 81.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 32824408 2.73% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14992288 1.25% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 32824411 2.73% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14992283 1.25% 88.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 7935666 0.66% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 134104221 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 134104219 11.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1202552570 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 173096808 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35071.906355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35057.573416 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 173095014 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 62919000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1202552471 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 173096803 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35063.545151 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35058.732612 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 173095009 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 62904000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1794 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 45364500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45366000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1294 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 133870.853828 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 133870.849961 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 173096808 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35071.906355 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35057.573416 # average overall mshr miss latency -system.cpu.icache.demand_hits 173095014 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 62919000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 173096803 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35063.545151 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency +system.cpu.icache.demand_hits 173095009 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 62904000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses system.cpu.icache.demand_misses 1794 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 45364500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45366000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1294 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.509485 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1043.425077 # Average occupied blocks per context -system.cpu.icache.overall_accesses 173096808 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35071.906355 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35057.573416 # average overall mshr miss latency +system.cpu.icache.occ_blocks::0 1043.425085 # Average occupied blocks per context +system.cpu.icache.overall_accesses 173096803 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35063.545151 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 173095014 # number of overall hits -system.cpu.icache.overall_miss_latency 62919000 # number of overall miss cycles +system.cpu.icache.overall_hits 173095009 # number of overall hits +system.cpu.icache.overall_miss_latency 62904000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses system.cpu.icache.overall_misses 1794 # number of overall misses system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 45364500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45366000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1294 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -211,39 +211,39 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 158 # number of replacements system.cpu.icache.sampled_refs 1293 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1043.425077 # Cycle average of tags in use -system.cpu.icache.total_refs 173095014 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1043.425085 # Cycle average of tags in use +system.cpu.icache.total_refs 173095009 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 365772 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 89387990 # Number of branches executed -system.cpu.iew.EXEC:nop 102270124 # number of nop insts executed +system.cpu.idleCycles 365764 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 89387997 # Number of branches executed +system.cpu.iew.EXEC:nop 102270118 # number of nop insts executed system.cpu.iew.EXEC:rate 1.226826 # Inst execution rate -system.cpu.iew.EXEC:refs 590483047 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 169844843 # Number of stores executed +system.cpu.iew.EXEC:refs 590483044 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 169844841 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1212158392 # num instructions consuming a value -system.cpu.iew.WB:count 1472499117 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 1212158273 # num instructions consuming a value +system.cpu.iew.WB:count 1472499084 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.958320 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1161635515 # num instructions producing a value +system.cpu.iew.WB:producers 1161635414 # num instructions producing a value system.cpu.iew.WB:rate 1.224106 # insts written-back per cycle -system.cpu.iew.WB:sent 1473870782 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 5524570 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent 1473870749 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 5524544 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 2522826 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 468104287 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2975264 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 4542141 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 188277603 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1708974065 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 420638204 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6158152 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1475771802 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 468104285 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2975263 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4542157 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 188277600 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1708973999 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 420638203 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6158150 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1475771768 # Number of executed instructions system.cpu.iew.iewIQFullEvents 67057 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 9806 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 30410707 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 30410701 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 130988 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked @@ -253,15 +253,15 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 65591443 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 21429461 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 65591441 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 21429458 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 648508 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 648482 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.168495 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.168495 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685461 59.70% 59.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685428 59.70% 59.70% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618266 0.18% 59.87% # Type of FU issued @@ -290,15 +290,15 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87% system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 423845993 28.60% 88.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780234 11.52% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 423845992 28.60% 88.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780232 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1481929954 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 3245028 # FU busy when requested +system.cpu.iq.ISSUE:FU_type_0::total 1481929918 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 3245029 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 213199 6.57% 6.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 213200 6.57% 6.57% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 176159 5.43% 12.00% # attempts to use FU when none available @@ -331,31 +331,31 @@ system.cpu.iq.ISSUE:fu_full::MemRead 2529947 77.96% 89.96% # at system.cpu.iq.ISSUE:fu_full::MemWrite 325723 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1202552570 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1202552471 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232320 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127769 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 320558018 26.66% 26.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 511599251 42.54% 69.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 219311196 18.24% 87.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 94899600 7.89% 95.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 39949792 3.32% 98.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 10701863 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5167479 0.43% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 226814 0.02% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 320557937 26.66% 26.66% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 511599256 42.54% 69.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 219311183 18.24% 87.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 94899588 7.89% 95.33% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 39949785 3.32% 98.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 10701869 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5167481 0.43% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 226815 0.02% 99.99% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 138557 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1202552570 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 1202552471 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.231946 # Inst issue rate -system.cpu.iq.iqInstsAdded 1603628020 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1481929954 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3075921 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 200595245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqInstsAdded 1603627961 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1481929918 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 3075920 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 200595189 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 67507 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 832250 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 279093413 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 832249 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 279093354 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.623615 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.356706 # average ReadExReq mshr miss latency @@ -366,87 +366,87 @@ system.cpu.l2cache.ReadExReq_misses 60470 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893881500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 214778 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.356888 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.002969 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 214777 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.417352 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.032810 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1146344500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.156813 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33680 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044248500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156813 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33680 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 428419 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 428419 # number of Writeback hits +system.cpu.l2cache.ReadReq_miss_latency 1146312500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.156809 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33679 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1044218500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156809 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33679 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 428418 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 428418 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.114590 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.114484 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482858 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34274.811471 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.903877 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 482857 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34274.835633 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3226973500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 3226941500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.194983 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 94149 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2938130000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2938100000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.194983 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 94149 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.060598 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1985.675951 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15675.618394 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34274.811471 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.903877 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 1985.676117 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15675.618625 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 482857 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34274.835633 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 388708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3226973500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 94150 # number of overall misses +system.cpu.l2cache.overall_miss_latency 3226941500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.194983 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 94149 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2938130000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2938100000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.194983 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 94149 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 75916 # number of replacements -system.cpu.l2cache.sampled_refs 91430 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 91428 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17661.294345 # Cycle average of tags in use -system.cpu.l2cache.total_refs 467627 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17661.294741 # Cycle average of tags in use +system.cpu.l2cache.total_refs 467607 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 59275 # number of writebacks system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 165665166 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 468104287 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 188277603 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1202918342 # number of cpu cycles simulated +system.cpu.memDep0.insertedLoads 468104285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 188277600 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1202918235 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 123850375 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers system.cpu.rename.RENAME:IQFullEvents 134234499 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 443701080 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 443701065 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 41034727 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2926118072 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1732032872 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1445195761 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 329589448 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 30410707 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 2924510246 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1732032824 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1445195719 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 329589441 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 30410701 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 217220623 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 200425309 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 57780337 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:UndoneMaps 200425267 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 57780266 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 385268433 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 385268446 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed system.cpu.timesIdled 11396 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 2f00d5679..f550d7f17 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 2 2010 15:11:52 -M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase -M5 started Dec 2 2010 19:10:47 -M5 executing on zizzer +M5 compiled Jan 15 2011 04:38:18 +M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip +M5 started Jan 15 2011 04:38:23 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 18731500 because target called exit() +Exiting @ tick 18656000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index ed5cabb1f..e87194a60 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 90431 # Simulator instruction rate (inst/s) -host_mem_usage 203888 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 117038227 # Simulator tick rate (ticks/s) +host_inst_rate 46971 # Simulator instruction rate (inst/s) +host_mem_usage 216748 # Number of bytes of host memory used +host_seconds 0.31 # Real time elapsed on the host +host_tick_rate 60590117 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18731500 # Number of ticks simulated +sim_ticks 18656000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 2701 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 5096 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2698 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 5085 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 725 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 5196 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5196 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 5172 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5172 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 27718 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.547478 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.185032 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 27579 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.550237 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.187070 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 19937 71.93% 71.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 4515 16.29% 88.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1459 5.26% 93.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 767 2.77% 96.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 374 1.35% 97.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 256 0.92% 98.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 289 1.04% 99.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 19793 71.77% 71.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 4521 16.39% 88.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1461 5.30% 93.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 765 2.77% 96.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 373 1.35% 97.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 256 0.93% 98.51% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.70% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 84 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 27718 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 27579 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 3674 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 725 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5217 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5133 # The number of squashed insts skipped by commit system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.592844 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.592844 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2789 # number of ReadReq accesses(hits+misses) +system.cpu.cpi 2.582393 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.582393 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2777 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2665 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 2653 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.044460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.044653 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022686 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits @@ -75,167 +75,167 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # m system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.376712 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.294521 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4231 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4219 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 35362.781955 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3699 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3687 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 18813000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.125739 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.126096 # miss rate for demand accesses system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 5215500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.034507 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.034605 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.024963 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 102.247340 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 4231 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.024937 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 102.143173 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 4219 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 35362.781955 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3699 # number of overall hits +system.cpu.dcache.overall_hits 3687 # number of overall hits system.cpu.dcache.overall_miss_latency 18813000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.125739 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.126096 # miss rate for overall accesses system.cpu.dcache.overall_misses 532 # number of overall misses system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 5215500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.034507 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.034605 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.247340 # Cycle average of tags in use -system.cpu.dcache.total_refs 3705 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.143173 # Cycle average of tags in use +system.cpu.dcache.total_refs 3693 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 7118 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 23678 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 13190 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 7286 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1191 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 7077 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 23586 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 13112 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 7266 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1178 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 5196 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4112 # Number of cache lines fetched -system.cpu.fetch.Cycles 11672 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched +system.cpu.fetch.Cycles 11611 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 24093 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 837 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.138693 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4112 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2701 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.643097 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 28892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.833899 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.950141 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2698 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.642725 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 28740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.834447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.949360 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21359 73.93% 73.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3597 12.45% 86.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 580 2.01% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 513 1.78% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 668 2.31% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 530 1.83% 94.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 244 0.84% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 197 0.68% 95.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1204 4.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21234 73.88% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3581 12.46% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 587 2.04% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 509 1.77% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 664 2.31% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 529 1.84% 94.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 246 0.86% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 197 0.69% 95.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1193 4.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28892 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4112 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34753.073770 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34880.281690 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3624 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16959500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.118677 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 488 # number of ReadReq misses +system.cpu.fetch.rateDist::total 28740 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 4077 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 34819.301848 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34975.988701 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3590 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16957000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.119451 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 12382500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.086333 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 355 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency 12381500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.086829 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10.237288 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10.141243 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4112 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34753.073770 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34880.281690 # average overall mshr miss latency -system.cpu.icache.demand_hits 3624 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16959500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.118677 # miss rate for demand accesses -system.cpu.icache.demand_misses 488 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 4077 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 34819.301848 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency +system.cpu.icache.demand_hits 3590 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16957000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.119451 # miss rate for demand accesses +system.cpu.icache.demand_misses 487 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12382500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.086333 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 355 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 12381500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.086829 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 354 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.099925 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 204.645792 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4112 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34753.073770 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34880.281690 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.099779 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 204.347725 # Average occupied blocks per context +system.cpu.icache.overall_accesses 4077 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 34819.301848 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3624 # number of overall hits -system.cpu.icache.overall_miss_latency 16959500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.118677 # miss rate for overall accesses -system.cpu.icache.overall_misses 488 # number of overall misses +system.cpu.icache.overall_hits 3590 # number of overall hits +system.cpu.icache.overall_miss_latency 16957000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.119451 # miss rate for overall accesses +system.cpu.icache.overall_misses 487 # number of overall misses system.cpu.icache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12382500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.086333 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 355 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 12381500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.086829 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 354 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 204.645792 # Cycle average of tags in use -system.cpu.icache.total_refs 3624 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 204.347725 # Cycle average of tags in use +system.cpu.icache.total_refs 3590 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8572 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3845 # Number of branches executed -system.cpu.iew.EXEC:nop 1083 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.470131 # Inst execution rate -system.cpu.iew.EXEC:refs 4644 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1769 # Number of stores executed +system.cpu.idleCycles 8573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3856 # Number of branches executed +system.cpu.iew.EXEC:nop 1087 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.470989 # Inst execution rate +system.cpu.iew.EXEC:refs 4619 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1763 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9394 # num instructions consuming a value -system.cpu.iew.WB:count 17150 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.855972 # average fanout of values written-back +system.cpu.iew.WB:consumers 9338 # num instructions consuming a value +system.cpu.iew.WB:count 17128 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.855858 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8041 # num instructions producing a value -system.cpu.iew.WB:rate 0.457773 # insts written-back per cycle -system.cpu.iew.WB:sent 17335 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 821 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 7992 # num instructions producing a value +system.cpu.iew.WB:rate 0.459036 # insts written-back per cycle +system.cpu.iew.WB:sent 17304 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 800 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3080 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 569 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1935 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 20414 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2875 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 481 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 17613 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 566 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1925 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 20324 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2856 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 465 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 17574 # Number of executed instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1191 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1178 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked @@ -245,109 +245,109 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 854 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 487 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 832 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 477 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 582 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 239 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.385677 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.385677 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387238 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387238 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 13329 73.67% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2941 16.25% 89.92% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1824 10.08% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 13302 73.74% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 73.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2921 16.19% 89.93% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1816 10.07% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 18094 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 123 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006798 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 18039 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 125 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006929 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 29 23.58% 44.72% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 68 55.28% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 28 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 29 23.20% 45.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 68 54.40% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 28892 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.626263 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192032 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 28740 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.627662 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192852 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 20022 69.30% 69.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4253 14.72% 84.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1909 6.61% 90.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 1729 5.98% 96.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 432 1.50% 98.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 282 0.98% 99.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 171 0.59% 99.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 19886 69.19% 69.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 4262 14.83% 84.02% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 1894 6.59% 90.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 1722 5.99% 96.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 431 1.50% 98.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 279 0.97% 99.07% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 172 0.60% 99.67% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::7 80 0.28% 99.95% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 28892 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.482970 # Inst issue rate -system.cpu.iq.iqInstsAdded 18762 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 18094 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 569 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4139 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 28740 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.483451 # Inst issue rate +system.cpu.iq.iqInstsAdded 18671 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 18039 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 566 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.385542 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency @@ -357,16 +357,16 @@ system.cpu.l2cache.ReadExReq_misses 83 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 418 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34234.299517 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.454106 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34314.769976 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.324455 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14173000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990431 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 414 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12837500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990431 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 414 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 14172000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks. @@ -375,63 +375,63 @@ system.cpu.l2cache.blocked::no_targets 0 # nu system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 501 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34294.768612 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31082.494970 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 500 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34361.895161 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17044500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992016 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 17043500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 496 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15448000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992016 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 497 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 15447500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 496 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.007292 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 238.958608 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 501 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34294.768612 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31082.494970 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.007282 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 238.619810 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 500 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34361.895161 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17044500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992016 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_miss_latency 17043500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 496 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15448000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992016 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 497 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 15447500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 496 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 238.958608 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 238.619810 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 3080 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1935 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 37464 # number of cpu cycles simulated +system.cpu.memDep0.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1925 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 37313 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 13649 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 13569 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 40984 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21894 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19600 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 7060 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1191 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 422 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5768 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 6316 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 622 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2701 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 587 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:RenameLookups 40450 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21815 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19528 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 7042 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1178 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 421 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 5696 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 6276 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 617 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2691 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 583 # count of temporary serializing insts renamed system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index e5c78e4f6..4f8a47072 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 2 2010 15:11:52 -M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase -M5 started Dec 2 2010 19:11:11 -M5 executing on zizzer +M5 compiled Jan 15 2011 04:38:18 +M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip +M5 started Jan 15 2011 04:38:23 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -36,17 +36,17 @@ Iteration 2 completed Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 Iteration 4 completed [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 @@ -55,33 +55,33 @@ Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 Iteration 7 completed -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 9, Thread 1] Got lock [Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 117665000 because target called exit() +Exiting @ tick 117496500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3f5682abc..3a768d259 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,269 +1,269 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 152094 # Simulator instruction rate (inst/s) -host_mem_usage 214340 # Number of bytes of host memory used -host_seconds 7.59 # Real time elapsed on the host -host_tick_rate 15507555 # Simulator tick rate (ticks/s) +host_inst_rate 82069 # Simulator instruction rate (inst/s) +host_mem_usage 227196 # Number of bytes of host memory used +host_seconds 14.05 # Real time elapsed on the host +host_tick_rate 8360775 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1153987 # Number of instructions simulated -sim_seconds 0.000118 # Number of seconds simulated -sim_ticks 117665000 # Number of ticks simulated +sim_insts 1153323 # Number of instructions simulated +sim_seconds 0.000117 # Number of seconds simulated +sim_ticks 117496500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 89393 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 92028 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 89278 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 91911 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu0.BPredUnit.condIncorrect 1075 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 92481 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 92481 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 92364 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 92364 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 89667 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 218 # number cycles where commit BW limit reached +system.cpu0.commit.COM:branches 89553 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 219 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 215178 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 2.487387 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 2.121699 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 214839 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 2.488128 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 2.121442 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 33843 15.73% 15.73% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 90761 42.18% 57.91% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 2490 1.16% 59.06% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 739 0.34% 59.41% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 743 0.35% 59.75% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 85822 39.88% 99.64% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 487 0.23% 99.86% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 75 0.03% 99.90% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 218 0.10% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 33722 15.70% 15.70% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 90658 42.20% 57.89% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 2488 1.16% 59.05% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 738 0.34% 59.40% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 743 0.35% 59.74% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 85727 39.90% 99.64% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 468 0.22% 99.86% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 76 0.04% 99.90% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 219 0.10% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 215178 # Number of insts commited each cycle -system.cpu0.commit.COM:count 535231 # Number of instructions committed -system.cpu0.commit.COM:loads 174546 # Number of loads committed +system.cpu0.commit.COM:committed_per_cycle::total 214839 # Number of insts commited each cycle +system.cpu0.commit.COM:count 534547 # Number of instructions committed +system.cpu0.commit.COM:loads 174318 # Number of loads committed system.cpu0.commit.COM:membars 84 # Number of memory barriers committed -system.cpu0.commit.COM:refs 262325 # Number of memory references committed +system.cpu0.commit.COM:refs 261983 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.branchMispredicts 1075 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 535231 # The number of committed instructions +system.cpu0.commit.commitCommittedInsts 534547 # The number of committed instructions system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 9532 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 448749 # Number of Instructions Simulated -system.cpu0.committedInsts_total 448749 # Number of Instructions Simulated -system.cpu0.cpi 0.524416 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.524416 # CPI: Total CPI of All Threads -system.cpu0.dcache.ReadReq_accesses 89627 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 27580.808081 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27913.043478 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 89132 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 13652500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.005523 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 495 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 311 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 5136000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002053 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses +system.cpu0.commit.commitSquashedInsts 9542 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 448179 # Number of Instructions Simulated +system.cpu0.committedInsts_total 448179 # Number of Instructions Simulated +system.cpu0.cpi 0.524331 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.524331 # CPI: Total CPI of All Threads +system.cpu0.dcache.ReadReq_accesses 89513 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 27025.458248 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27734.972678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 89022 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 13269500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.005485 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 491 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 308 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 5075500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002044 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 183 # number of ReadReq MSHR misses system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 16596.153846 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13596.153846 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency 16807.692308 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13807.692308 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 431500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency 437000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_mshr_miss_latency 353500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency 359000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 87737 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 46115.711111 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37137.931034 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 87197 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 24902484 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.006155 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_accesses 87623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 46095.340741 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36862.857143 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 87083 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 24891484 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.006163 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 366 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 6462000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001983 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 6451000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001997 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 175 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 640.367816 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 607.620690 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 177364 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 37251.192271 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 32396.648045 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 176329 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 38554984 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.005835 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1035 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 677 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 11598000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.002018 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_accesses 177136 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 37013.563531 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 32196.927374 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 176105 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 38160984 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.005820 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1031 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 673 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 11526500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.002021 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.275981 # Average percentage of cache occupancy -system.cpu0.dcache.occ_%::1 -0.002700 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 141.302499 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.382442 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 177364 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 37251.192271 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 32396.648045 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.275951 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.002548 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 141.286787 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.304354 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 177136 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 37013.563531 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 32196.927374 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 176329 # number of overall hits -system.cpu0.dcache.overall_miss_latency 38554984 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.005835 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1035 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 677 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 11598000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.002018 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_hits 176105 # number of overall hits +system.cpu0.dcache.overall_miss_latency 38160984 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.005820 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1031 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 673 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 11526500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.002021 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 139.920057 # Cycle average of tags in use -system.cpu0.dcache.total_refs 111424 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 139.982434 # Cycle average of tags in use +system.cpu0.dcache.total_refs 105726 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 13620 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:DecodedInsts 549750 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 20029 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 181310 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 2059 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:BlockedCycles 13489 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:DecodedInsts 549068 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 20046 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 181085 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 2062 # Number of cycles decode is squashing system.cpu0.decode.DECODE:UnblockCycles 202 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 92481 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 5258 # Number of cache lines fetched -system.cpu0.fetch.Cycles 187053 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.Branches 92364 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 5264 # Number of cache lines fetched +system.cpu0.fetch.Cycles 186834 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.IcacheSquashes 482 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 550749 # Number of instructions fetch has processed +system.cpu0.fetch.Insts 550067 # Number of instructions fetch has processed system.cpu0.fetch.SquashCycles 1232 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.392983 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 5258 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 89393 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 2.340316 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 217220 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.535443 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.186868 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.393048 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 5264 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 89278 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 2.340770 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 216884 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.536227 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.186778 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35466 16.33% 16.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 90305 41.57% 57.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 487 0.22% 58.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 806 0.37% 58.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 587 0.27% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 86662 39.90% 98.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35355 16.30% 16.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 90192 41.59% 57.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 488 0.23% 58.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 808 0.37% 58.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 588 0.27% 58.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 86546 39.90% 98.66% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 826 0.38% 99.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 210 0.10% 99.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1871 0.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 211 0.10% 99.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 1870 0.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 217220 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses 5258 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 39105.298013 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37007.389163 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 4503 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 29524500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.143591 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 755 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 146 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 22537500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.115824 # mshr miss rate for ReadReq accesses +system.cpu0.fetch.rateDist::total 216884 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses 5264 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 39056.216931 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37012.315271 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 4508 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 29526500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.143617 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 756 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 147 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 22540500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.115691 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 609 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs 11000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 7.406250 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 7.414474 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 22000 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 5258 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 39105.298013 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 37007.389163 # average overall mshr miss latency -system.cpu0.icache.demand_hits 4503 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 29524500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.143591 # miss rate for demand accesses -system.cpu0.icache.demand_misses 755 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 22537500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.115824 # mshr miss rate for demand accesses +system.cpu0.icache.demand_accesses 5264 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 39056.216931 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 37012.315271 # average overall mshr miss latency +system.cpu0.icache.demand_hits 4508 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 29526500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.143617 # miss rate for demand accesses +system.cpu0.icache.demand_misses 756 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 147 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 22540500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.115691 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 609 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.502905 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 257.487512 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 5258 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 39105.298013 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 37007.389163 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.502840 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 257.454218 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 5264 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 39056.216931 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 37012.315271 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 4503 # number of overall hits -system.cpu0.icache.overall_miss_latency 29524500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.143591 # miss rate for overall accesses -system.cpu0.icache.overall_misses 755 # number of overall misses -system.cpu0.icache.overall_mshr_hits 146 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 22537500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.115824 # mshr miss rate for overall accesses +system.cpu0.icache.overall_hits 4508 # number of overall hits +system.cpu0.icache.overall_miss_latency 29526500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.143617 # miss rate for overall accesses +system.cpu0.icache.overall_misses 756 # number of overall misses +system.cpu0.icache.overall_mshr_hits 147 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 22540500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.115691 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 609 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.replacements 307 # number of replacements system.cpu0.icache.sampled_refs 608 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 257.487512 # Cycle average of tags in use -system.cpu0.icache.total_refs 4503 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 257.454218 # Cycle average of tags in use +system.cpu0.icache.total_refs 4508 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 18111 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 90461 # Number of branches executed -system.cpu0.iew.EXEC:nop 86855 # number of nop insts executed -system.cpu0.iew.EXEC:rate 1.931679 # Inst execution rate -system.cpu0.iew.EXEC:refs 263994 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 88313 # Number of stores executed +system.cpu0.idleCycles 18110 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 90363 # Number of branches executed +system.cpu0.iew.EXEC:nop 86742 # number of nop insts executed +system.cpu0.iew.EXEC:rate 1.932130 # Inst execution rate +system.cpu0.iew.EXEC:refs 263654 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 88201 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 271356 # num instructions consuming a value -system.cpu0.iew.WB:count 453956 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.992932 # average fanout of values written-back +system.cpu0.iew.WB:consumers 270968 # num instructions consuming a value +system.cpu0.iew.WB:count 453412 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.992922 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 269438 # num instructions producing a value -system.cpu0.iew.WB:rate 1.929011 # insts written-back per cycle -system.cpu0.iew.WB:sent 454201 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 1256 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 901 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 176230 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 725 # Number of dispatched non-speculative instructions +system.cpu0.iew.WB:producers 269050 # num instructions producing a value +system.cpu0.iew.WB:rate 1.929462 # insts written-back per cycle +system.cpu0.iew.WB:sent 453657 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 1246 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 822 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 176000 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 727 # Number of dispatched non-speculative instructions system.cpu0.iew.iewDispSquashedInsts 482 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 88858 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 544759 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 175681 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 928 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 454584 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewDispStoreInsts 88746 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 544085 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 175453 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 917 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 454039 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 2059 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking +system.cpu0.iew.iewSquashCycles 2062 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 86003 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.forwLoads 85889 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread.0.memOrderViolation 74 # Number of memory ordering violations system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1684 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 1079 # Number of stores squashed +system.cpu0.iew.lsq.thread.0.squashedLoads 1682 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 1081 # Number of stores squashed system.cpu0.iew.memOrderViolationEvents 74 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 831 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 821 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 1.906884 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.906884 # IPC: Total IPC of All Threads +system.cpu0.ipc 1.907193 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.907193 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 191111 41.96% 41.96% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 190895 41.96% 41.96% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 41.96% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.96% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 41.96% # Type of FU issued @@ -292,1210 +292,1211 @@ system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 41.96% system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 41.96% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 41.96% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 41.96% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 175974 38.63% 80.59% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88427 19.41% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 175746 38.63% 80.59% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88315 19.41% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 455512 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 219 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.000481 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 454956 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 227 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.000499 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 29 13.24% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 13.24% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 83 37.90% 51.14% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 107 48.86% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 33 14.54% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 14.54% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 85 37.44% 51.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 109 48.02% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 217220 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.097008 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.057658 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 216884 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.097693 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.057244 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 33500 15.42% 15.42% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 5647 2.60% 18.02% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 88284 40.64% 58.66% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 87260 40.17% 98.84% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 1518 0.70% 99.53% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 727 0.33% 99.87% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 185 0.09% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 92 0.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 33388 15.39% 15.39% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 5635 2.60% 17.99% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 88185 40.66% 58.65% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 87166 40.19% 98.84% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 1498 0.69% 99.53% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 719 0.33% 99.86% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 194 0.09% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 90 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 217220 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 1.935623 # Inst issue rate -system.cpu0.iq.iqInstsAdded 457082 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 455512 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 822 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 8244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.ISSUE:issued_per_cycle::total 216884 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 1.936032 # Inst issue rate +system.cpu0.iq.iqInstsAdded 456518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 454956 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 825 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 8243 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 263 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 6884 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.memDep0.conflictingLoads 86366 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 86212 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 176230 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 88858 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 235331 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 1287 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 361924 # Number of HB maps that are committed +system.cpu0.iq.iqSquashedNonSpecRemoved 266 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 6865 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.memDep0.conflictingLoads 86252 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 86102 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 176000 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 88746 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 234994 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 1211 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 361468 # Number of HB maps that are committed system.cpu0.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 20717 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 290 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:RenameLookups 1091002 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 546581 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 372241 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 180866 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 2059 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 696 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 10317 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 11595 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 810 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 4205 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 813 # count of temporary serializing insts renamed +system.cpu0.rename.RENAME:IdleCycles 20733 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 291 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:RenameLookups 1089130 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 545907 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 371790 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 180641 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 2062 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 697 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 10322 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 11540 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 809 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 4202 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 812 # count of temporary serializing insts renamed system.cpu0.timesIdled 337 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 54164 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 56398 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 41740 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 43967 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 1087 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 56510 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 56510 # Number of BP lookups +system.cpu1.BPredUnit.condIncorrect 1106 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 44023 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 44023 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 53699 # Number of branches committed +system.cpu1.commit.COM:branches 41195 # Number of branches committed system.cpu1.commit.COM:bw_lim_events 485 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 188517 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 1.608476 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.965365 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 187667 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 1.179936 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.750960 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 76809 40.74% 40.74% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 54523 28.92% 69.67% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 7469 3.96% 73.63% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 7247 3.84% 77.47% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 2461 1.31% 78.78% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 38972 20.67% 99.45% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 418 0.22% 99.67% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 133 0.07% 99.74% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 100980 53.81% 53.81% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 41996 22.38% 76.19% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 7478 3.98% 80.17% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 10619 5.66% 85.83% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 2461 1.31% 87.14% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 23116 12.32% 99.46% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 402 0.21% 99.67% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 130 0.07% 99.74% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::8 485 0.26% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 188517 # Number of insts commited each cycle -system.cpu1.commit.COM:count 303225 # Number of instructions committed -system.cpu1.commit.COM:loads 89251 # Number of loads committed -system.cpu1.commit.COM:membars 5705 # Number of memory barriers committed -system.cpu1.commit.COM:refs 131280 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 187667 # Number of insts commited each cycle +system.cpu1.commit.COM:count 221435 # Number of instructions committed +system.cpu1.commit.COM:loads 60856 # Number of loads committed +system.cpu1.commit.COM:membars 9088 # Number of memory barriers committed +system.cpu1.commit.COM:refs 87006 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 1087 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 303225 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 8275 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 253031 # Number of Instructions Simulated -system.cpu1.committedInsts_total 253031 # Number of Instructions Simulated -system.cpu1.cpi 0.791401 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.791401 # CPI: Total CPI of All Threads -system.cpu1.dcache.ReadReq_accesses 51825 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 22044.372294 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13760.869565 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 51363 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 10184500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.008915 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 462 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 2215500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003107 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 161 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 25285.714286 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22285.714286 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 1416000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.823529 # miss rate for SwapReq accesses +system.cpu1.commit.branchMispredicts 1106 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 221435 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 9806 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 8244 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 180366 # Number of Instructions Simulated +system.cpu1.committedInsts_total 180366 # Number of Instructions Simulated +system.cpu1.cpi 1.108479 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.108479 # CPI: Total CPI of All Threads +system.cpu1.dcache.ReadReq_accesses 39263 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 22504.819277 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 14511.904762 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 38848 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9339500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.010570 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 415 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 247 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 2438000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.004279 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 168 # number of ReadReq MSHR misses +system.cpu1.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_avg_miss_latency 25946.428571 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22946.428571 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_hits 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_latency 1453000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_rate 0.777778 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_misses 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_miss_latency 1248000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.823529 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_latency 1285000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.777778 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 41961 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 22944 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14406.542056 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 41836 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 2868000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.002979 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 125 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1541500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002550 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 26078 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 24129.166667 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15810 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 25958 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 2895500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.004602 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 120 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 20 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 1581000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.003835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 100 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 1593.333333 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1063.866667 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 93786 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 22235.945486 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14018.656716 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 93199 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 13052500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.006259 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 587 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 3757000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.002858 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_accesses 65341 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 22869.158879 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14996.268657 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 64806 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 12235000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.008188 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 535 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 4019000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.004102 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 268 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.047197 # Average percentage of cache occupancy -system.cpu1.dcache.occ_%::1 -0.018851 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 24.164747 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -9.651740 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 93786 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 22235.945486 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14018.656716 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.047224 # Average percentage of cache occupancy +system.cpu1.dcache.occ_%::1 -0.015258 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 24.178499 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -7.812139 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 65341 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 22869.158879 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14996.268657 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 93199 # number of overall hits -system.cpu1.dcache.overall_miss_latency 13052500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.006259 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 587 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 3757000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.002858 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_hits 64806 # number of overall hits +system.cpu1.dcache.overall_miss_latency 12235000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.008188 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 535 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 267 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 4019000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.004102 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 268 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 14.513007 # Cycle average of tags in use -system.cpu1.dcache.total_refs 47800 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 16.366360 # Cycle average of tags in use +system.cpu1.dcache.total_refs 31916 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 20785 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:DecodedInsts 315548 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 53596 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 108904 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 1778 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:UnblockCycles 5231 # Number of cycles decode is unblocking -system.cpu1.fetch.Branches 56510 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 20132 # Number of cache lines fetched -system.cpu1.fetch.Cycles 134664 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 220 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 316686 # Number of instructions fetch has processed -system.cpu1.fetch.SquashCycles 1166 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.282199 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 20132 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 54164 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.581461 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 196924 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.608164 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.050823 # Number of instructions fetched each cycle (Total) +system.cpu1.decode.DECODE:BlockedCycles 23978 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:DecodedInsts 233739 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 70922 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 84431 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 1784 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:UnblockCycles 8335 # Number of cycles decode is unblocking +system.cpu1.fetch.Branches 44023 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 27242 # Number of cache lines fetched +system.cpu1.fetch.Cycles 120404 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 234880 # Number of instructions fetch has processed +system.cpu1.fetch.SquashCycles 1183 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.220190 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 27242 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 41740 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 1.174799 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 196087 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.197836 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.836209 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 82414 41.85% 41.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 58905 29.91% 71.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6768 3.44% 75.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2772 1.41% 76.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1900 0.96% 77.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 39920 20.27% 97.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2488 1.26% 99.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 255 0.13% 99.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1502 0.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 102948 52.50% 52.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49979 25.49% 77.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 10332 5.27% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2701 1.38% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1922 0.98% 85.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 23991 12.23% 97.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2480 1.26% 99.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 261 0.13% 99.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1473 0.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 196924 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses 20132 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 15221.991701 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12289.237668 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 19650 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 7337000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.023942 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 482 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 36 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5481000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.022154 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 446 # number of ReadReq MSHR misses +system.cpu1.fetch.rateDist::total 196087 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses 27242 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 15144.329897 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12327.702703 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 26757 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 7345000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.017803 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 485 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 5473500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.016298 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 444 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 44.058296 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 60.263514 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 20132 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 15221.991701 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12289.237668 # average overall mshr miss latency -system.cpu1.icache.demand_hits 19650 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 7337000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.023942 # miss rate for demand accesses -system.cpu1.icache.demand_misses 482 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 36 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5481000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.022154 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_accesses 27242 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 15144.329897 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 12327.702703 # average overall mshr miss latency +system.cpu1.icache.demand_hits 26757 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 7345000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017803 # miss rate for demand accesses +system.cpu1.icache.demand_misses 485 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 5473500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.016298 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 444 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.166450 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 85.222348 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 20132 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 15221.991701 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12289.237668 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.166395 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 85.194355 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 27242 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 15144.329897 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12327.702703 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 19650 # number of overall hits -system.cpu1.icache.overall_miss_latency 7337000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.023942 # miss rate for overall accesses -system.cpu1.icache.overall_misses 482 # number of overall misses -system.cpu1.icache.overall_mshr_hits 36 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5481000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.022154 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 446 # number of overall MSHR misses +system.cpu1.icache.overall_hits 26757 # number of overall hits +system.cpu1.icache.overall_miss_latency 7345000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017803 # miss rate for overall accesses +system.cpu1.icache.overall_misses 485 # number of overall misses +system.cpu1.icache.overall_mshr_hits 41 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 5473500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.016298 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 444 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 334 # number of replacements -system.cpu1.icache.sampled_refs 446 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 332 # number of replacements +system.cpu1.icache.sampled_refs 444 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 85.222348 # Cycle average of tags in use -system.cpu1.icache.total_refs 19650 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 85.194355 # Cycle average of tags in use +system.cpu1.icache.total_refs 26757 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 3325 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 54259 # Number of branches executed -system.cpu1.iew.EXEC:nop 45275 # number of nop insts executed -system.cpu1.iew.EXEC:rate 1.310923 # Inst execution rate -system.cpu1.iew.EXEC:refs 132378 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 42378 # Number of stores executed +system.cpu1.idleCycles 3845 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 41746 # Number of branches executed +system.cpu1.iew.EXEC:nop 32789 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.965868 # Inst execution rate +system.cpu1.iew.EXEC:refs 88018 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 26481 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 152453 # num instructions consuming a value -system.cpu1.iew.WB:count 262146 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.975993 # average fanout of values written-back +system.cpu1.iew.WB:consumers 108078 # num instructions consuming a value +system.cpu1.iew.WB:count 192754 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.966228 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 148793 # num instructions producing a value -system.cpu1.iew.WB:rate 1.309100 # insts written-back per cycle -system.cpu1.iew.WB:sent 262278 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 1189 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 1723 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 90759 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 936 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 579 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 42808 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 311533 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 90000 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 943 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 262511 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 104428 # num instructions producing a value +system.cpu1.iew.WB:rate 0.964098 # insts written-back per cycle +system.cpu1.iew.WB:sent 192883 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 1512 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 62331 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 947 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 594 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 26882 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 229712 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 61537 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 953 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 193108 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 1778 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu1.iew.iewSquashCycles 1784 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 38160 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.forwLoads 22259 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 37 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 35 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 1508 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 779 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 207 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 982 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 1.263582 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.263582 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.squashedLoads 1475 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 732 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 189 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 1010 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.902137 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.902137 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 125153 47.50% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 95890 36.40% 83.90% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42411 16.10% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 96746 49.85% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 49.85% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 70805 36.49% 86.34% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 26510 13.66% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 263454 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 196 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 194061 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 185 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.000953 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 10 5.10% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.06% 33.16% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 131 66.84% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 11 5.95% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.95% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 43 23.24% 29.19% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 131 70.81% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 196924 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 1.337846 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.287201 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 196087 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.989668 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.215562 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 78523 39.87% 39.87% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 26788 13.60% 53.48% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 44704 22.70% 76.18% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 42538 21.60% 97.78% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 2558 1.30% 99.08% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 1568 0.80% 99.88% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 153 0.08% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 99332 50.66% 50.66% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 36909 18.82% 69.48% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 28876 14.73% 84.21% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 26632 13.58% 97.79% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 2531 1.29% 99.08% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 1564 0.80% 99.88% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 151 0.08% 99.95% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 196924 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 1.315632 # Inst issue rate -system.cpu1.iq.iqInstsAdded 259237 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 263454 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 7021 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 6583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 6195 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.memDep0.conflictingLoads 44385 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 38318 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 90759 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 42808 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 200249 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 7062 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 207913 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 85 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 54227 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 50 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:RenameLookups 600696 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 313742 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 216202 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 113632 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 1778 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 643 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 8289 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12952 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 960 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2963 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 1012 # count of temporary serializing insts renamed -system.cpu1.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.iq.ISSUE:issued_per_cycle::total 196087 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.970635 # Inst issue rate +system.cpu1.iq.iqInstsAdded 186439 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 194061 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 10484 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 6548 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 678 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 6090 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.memDep0.conflictingLoads 31889 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 22377 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 62331 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 26882 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 199932 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 9891 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 147748 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 48 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 71551 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 40 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:RenameLookups 422855 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 231943 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 155885 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 92302 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 1784 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 562 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 8137 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 13360 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 970 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2743 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 1022 # count of temporary serializing insts renamed +system.cpu1.timesIdled 297 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.BTBHits 47901 # Number of BTB hits -system.cpu2.BPredUnit.BTBLookups 50093 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 58194 # Number of BTB hits +system.cpu2.BPredUnit.BTBLookups 60389 # Number of BTB lookups system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu2.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect -system.cpu2.BPredUnit.condPredicted 50192 # Number of conditional branches predicted -system.cpu2.BPredUnit.lookups 50192 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 60491 # Number of conditional branches predicted +system.cpu2.BPredUnit.lookups 60491 # Number of BP lookups system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.commit.COM:branches 47506 # Number of branches committed -system.cpu2.commit.COM:bw_lim_events 498 # number cycles where commit BW limit reached +system.cpu2.commit.COM:branches 57782 # Number of branches committed +system.cpu2.commit.COM:bw_lim_events 501 # number cycles where commit BW limit reached system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.commit.COM:committed_per_cycle::samples 185809 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::mean 1.418279 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::stdev 1.887696 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::samples 185916 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::mean 1.779174 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::stdev 2.020750 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::0 86613 46.61% 46.61% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::1 48206 25.94% 72.56% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::2 7461 4.02% 76.57% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::3 8520 4.59% 81.16% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::4 2453 1.32% 82.48% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::5 31433 16.92% 99.40% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::6 495 0.27% 99.66% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::7 130 0.07% 99.73% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::8 498 0.27% 100.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::0 66151 35.58% 35.58% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::1 58504 31.47% 67.05% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::2 7458 4.01% 71.06% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::3 5724 3.08% 74.14% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::4 2452 1.32% 75.46% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::5 44514 23.94% 99.40% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::6 485 0.26% 99.66% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::7 127 0.07% 99.73% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::8 501 0.27% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::total 185809 # Number of insts commited each cycle -system.cpu2.commit.COM:count 263529 # Number of instructions committed -system.cpu2.commit.COM:loads 75595 # Number of loads committed -system.cpu2.commit.COM:membars 6984 # Number of memory barriers committed -system.cpu2.commit.COM:refs 110158 # Number of memory references committed +system.cpu2.commit.COM:committed_per_cycle::total 185916 # Number of insts commited each cycle +system.cpu2.commit.COM:count 330777 # Number of instructions committed +system.cpu2.commit.COM:loads 98945 # Number of loads committed +system.cpu2.commit.COM:membars 4183 # Number of memory barriers committed +system.cpu2.commit.COM:refs 146579 # Number of memory references committed system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu2.commit.branchMispredicts 1085 # The number of times a branch was mispredicted -system.cpu2.commit.commitCommittedInsts 263529 # The number of committed instructions -system.cpu2.commit.commitNonSpecStalls 7697 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.commitSquashedInsts 7885 # The number of squashed insts skipped by commit -system.cpu2.committedInsts 218248 # Number of Instructions Simulated -system.cpu2.committedInsts_total 218248 # Number of Instructions Simulated -system.cpu2.cpi 0.916192 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.916192 # CPI: Total CPI of All Threads -system.cpu2.dcache.ReadReq_accesses 45615 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 22462.882096 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15906.060606 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 45157 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 10288000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.010041 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 458 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_hits 293 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_miss_latency 2624500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003617 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses -system.cpu2.dcache.SwapReq_accesses 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 27057.692308 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 24057.692308 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_hits 15 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 1407000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_rate 0.776119 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_misses 52 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 1251000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.776119 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 34496 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 24833.333333 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16634.615385 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 34373 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 3054500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.003566 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 123 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_miss_latency 1730000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.003015 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses +system.cpu2.commit.commitCommittedInsts 330777 # The number of committed instructions +system.cpu2.commit.commitNonSpecStalls 4895 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.commitSquashedInsts 8092 # The number of squashed insts skipped by commit +system.cpu2.committedInsts 278020 # Number of Instructions Simulated +system.cpu2.committedInsts_total 278020 # Number of Instructions Simulated +system.cpu2.cpi 0.718078 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.718078 # CPI: Total CPI of All Threads +system.cpu2.dcache.ReadReq_accesses 55923 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 22046.336207 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14829.113924 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 55459 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 10229500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.008297 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 464 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_hits 306 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_miss_latency 2343000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002825 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 158 # number of ReadReq MSHR misses +system.cpu2.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_avg_miss_latency 24990.740741 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 21990.740741 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_miss_latency 1349500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_rate 0.818182 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_misses 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_mshr_miss_latency 1187500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.818182 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses +system.cpu2.dcache.WriteReq_accesses 47568 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 23770.161290 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 15316.037736 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 47444 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 2947500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.002607 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_miss_latency 1623500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002228 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 1343.133333 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1779.400000 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 80111 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 22964.716007 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 79530 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 13342500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.007252 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 581 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 312 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 4354500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.003358 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_accesses 103491 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 22409.863946 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 15024.621212 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 102903 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 13177000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.005682 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 588 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 324 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 3966500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.002551 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.052845 # Average percentage of cache occupancy -system.cpu2.dcache.occ_%::1 -0.017028 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 27.056623 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -8.718285 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 80111 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 22964.716007 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.052851 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.017878 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 27.059534 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -9.153554 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 103491 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 22409.863946 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 15024.621212 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 79530 # number of overall hits -system.cpu2.dcache.overall_miss_latency 13342500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.007252 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 581 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 312 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 4354500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.003358 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 269 # number of overall MSHR misses +system.cpu2.dcache.overall_hits 102903 # number of overall hits +system.cpu2.dcache.overall_miss_latency 13177000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.005682 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 588 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 324 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 3966500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.002551 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 18.338338 # Cycle average of tags in use -system.cpu2.dcache.total_refs 40294 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 17.905980 # Cycle average of tags in use +system.cpu2.dcache.total_refs 53382 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.decode.DECODE:BlockedCycles 22122 # Number of cycles decode is blocked -system.cpu2.decode.DECODE:DecodedInsts 275316 # Number of instructions handled by decode -system.cpu2.decode.DECODE:IdleCycles 60659 # Number of cycles decode is idle -system.cpu2.decode.DECODE:RunCycles 96539 # Number of cycles decode is running -system.cpu2.decode.DECODE:SquashCycles 1720 # Number of cycles decode is squashing -system.cpu2.decode.DECODE:UnblockCycles 6488 # Number of cycles decode is unblocking -system.cpu2.fetch.Branches 50192 # Number of branches that fetch encountered -system.cpu2.fetch.CacheLines 22953 # Number of cache lines fetched -system.cpu2.fetch.Cycles 126374 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.IcacheSquashes 220 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.Insts 276443 # Number of instructions fetch has processed -system.cpu2.fetch.SquashCycles 1163 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.251014 # Number of branch fetches per cycle -system.cpu2.fetch.icacheStallCycles 22953 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.predictedBranches 47901 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.382512 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 194140 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.423936 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.970541 # Number of instructions fetched each cycle (Total) +system.cpu2.decode.DECODE:BlockedCycles 19187 # Number of cycles decode is blocked +system.cpu2.decode.DECODE:DecodedInsts 342711 # Number of instructions handled by decode +system.cpu2.decode.DECODE:IdleCycles 46061 # Number of cycles decode is idle +system.cpu2.decode.DECODE:RunCycles 116769 # Number of cycles decode is running +system.cpu2.decode.DECODE:SquashCycles 1740 # Number of cycles decode is squashing +system.cpu2.decode.DECODE:UnblockCycles 3898 # Number of cycles decode is unblocking +system.cpu2.fetch.Branches 60491 # Number of branches that fetch encountered +system.cpu2.fetch.CacheLines 17027 # Number of cache lines fetched +system.cpu2.fetch.Cycles 138086 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.IcacheSquashes 224 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.Insts 343825 # Number of instructions fetch has processed +system.cpu2.fetch.SquashCycles 1162 # Number of cycles fetch has spent squashing +system.cpu2.fetch.branchRate 0.303000 # Number of branch fetches per cycle +system.cpu2.fetch.icacheStallCycles 17027 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.predictedBranches 58194 # Number of branches that fetch has predicted taken +system.cpu2.fetch.rate 1.722225 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::samples 194280 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.769740 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.108066 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 90749 46.74% 46.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 54056 27.84% 74.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8214 4.23% 78.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 2581 1.33% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1900 0.98% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 32436 16.71% 97.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 2464 1.27% 99.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 268 0.14% 99.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1472 0.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 73252 37.70% 37.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 61385 31.60% 69.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5275 2.72% 72.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 2733 1.41% 73.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1902 0.98% 74.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 45539 23.44% 97.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 2450 1.26% 99.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 264 0.14% 99.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1480 0.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 194140 # Number of instructions fetched each cycle (Total) -system.cpu2.icache.ReadReq_accesses 22953 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 21650 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18383.484163 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 22463 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 10608500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.021348 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 490 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_miss_latency 8125500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.019257 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses +system.cpu2.fetch.rateDist::total 194280 # Number of instructions fetched each cycle (Total) +system.cpu2.icache.ReadReq_accesses 17027 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 21608.921162 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18272.935780 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 16545 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 10415500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.028308 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 482 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_miss_latency 7967000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.025606 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_misses 436 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs 18250 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 50.821267 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 37.947248 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 36500 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 22953 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 21650 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18383.484163 # average overall mshr miss latency -system.cpu2.icache.demand_hits 22463 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 10608500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.021348 # miss rate for demand accesses -system.cpu2.icache.demand_misses 490 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 8125500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.019257 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_accesses 17027 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 21608.921162 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 18272.935780 # average overall mshr miss latency +system.cpu2.icache.demand_hits 16545 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 10415500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.028308 # miss rate for demand accesses +system.cpu2.icache.demand_misses 482 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 7967000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.025606 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 436 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.176697 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 90.468971 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 22953 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 21650 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18383.484163 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.176617 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 90.427890 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 17027 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 21608.921162 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 18272.935780 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 22463 # number of overall hits -system.cpu2.icache.overall_miss_latency 10608500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.021348 # miss rate for overall accesses -system.cpu2.icache.overall_misses 490 # number of overall misses -system.cpu2.icache.overall_mshr_hits 48 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 8125500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.019257 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 442 # number of overall MSHR misses +system.cpu2.icache.overall_hits 16545 # number of overall hits +system.cpu2.icache.overall_miss_latency 10415500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.028308 # miss rate for overall accesses +system.cpu2.icache.overall_misses 482 # number of overall misses +system.cpu2.icache.overall_mshr_hits 46 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 7967000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.025606 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 436 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 332 # number of replacements -system.cpu2.icache.sampled_refs 442 # Sample count of references to valid blocks. +system.cpu2.icache.replacements 326 # number of replacements +system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 90.468971 # Cycle average of tags in use -system.cpu2.icache.total_refs 22463 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 90.427890 # Cycle average of tags in use +system.cpu2.icache.total_refs 16545 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idleCycles 5817 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.iew.EXEC:branches 48053 # Number of branches executed -system.cpu2.iew.EXEC:nop 38997 # number of nop insts executed -system.cpu2.iew.EXEC:rate 1.144831 # Inst execution rate -system.cpu2.iew.EXEC:refs 111212 # number of memory reference insts executed -system.cpu2.iew.EXEC:stores 34898 # Number of stores executed +system.cpu2.idleCycles 5360 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.iew.EXEC:branches 58330 # Number of branches executed +system.cpu2.iew.EXEC:nop 49308 # number of nop insts executed +system.cpu2.iew.EXEC:rate 1.432328 # Inst execution rate +system.cpu2.iew.EXEC:refs 147694 # number of memory reference insts executed +system.cpu2.iew.EXEC:stores 47984 # Number of stores executed system.cpu2.iew.EXEC:swp 0 # number of swp insts executed -system.cpu2.iew.WB:consumers 131272 # num instructions consuming a value -system.cpu2.iew.WB:count 228549 # cumulative count of insts written-back -system.cpu2.iew.WB:fanout 0.972149 # average fanout of values written-back +system.cpu2.iew.WB:consumers 167735 # num instructions consuming a value +system.cpu2.iew.WB:count 285574 # cumulative count of insts written-back +system.cpu2.iew.WB:fanout 0.978186 # average fanout of values written-back system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.iew.WB:producers 127616 # num instructions producing a value -system.cpu2.iew.WB:rate 1.142991 # insts written-back per cycle -system.cpu2.iew.WB:sent 228678 # cumulative count of insts sent to commit +system.cpu2.iew.WB:producers 164076 # num instructions producing a value +system.cpu2.iew.WB:rate 1.430445 # insts written-back per cycle +system.cpu2.iew.WB:sent 285706 # cumulative count of insts sent to commit system.cpu2.iew.branchMispredicts 1190 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewBlockCycles 1615 # Number of cycles IEW is blocking -system.cpu2.iew.iewDispLoadInsts 77014 # Number of dispatched load instructions -system.cpu2.iew.iewDispNonSpecInsts 921 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispStoreInsts 35289 # Number of dispatched store instructions -system.cpu2.iew.iewDispatchedInsts 271445 # Number of instructions dispatched to IQ -system.cpu2.iew.iewExecLoadInsts 76314 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 958 # Number of squashed instructions skipped in execute -system.cpu2.iew.iewExecutedInsts 228917 # Number of executed instructions -system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewBlockCycles 1666 # Number of cycles IEW is blocking +system.cpu2.iew.iewDispLoadInsts 100435 # Number of dispatched load instructions +system.cpu2.iew.iewDispNonSpecInsts 918 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewDispSquashedInsts 521 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispStoreInsts 48400 # Number of dispatched store instructions +system.cpu2.iew.iewDispatchedInsts 338900 # Number of instructions dispatched to IQ +system.cpu2.iew.iewExecLoadInsts 99710 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 966 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecutedInsts 285950 # Number of executed instructions +system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.iewSquashCycles 1720 # Number of cycles IEW is squashing -system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu2.iew.iewSquashCycles 1740 # Number of cycles IEW is squashing +system.cpu2.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 30681 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread.0.forwLoads 43769 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 36 # Number of memory ordering violations +system.cpu2.iew.lsq.thread.0.memOrderViolation 35 # Number of memory ordering violations system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 1419 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 726 # Number of stores squashed -system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu2.iew.predictedNotTakenIncorrect 197 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.predictedTakenIncorrect 993 # Number of branches that were predicted taken incorrectly -system.cpu2.ipc 1.091475 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.091475 # IPC: Total IPC of All Threads +system.cpu2.iew.lsq.thread.0.squashedLoads 1490 # Number of loads squashed +system.cpu2.iew.lsq.thread.0.squashedStores 766 # Number of stores squashed +system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu2.iew.predictedNotTakenIncorrect 199 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.predictedTakenIncorrect 991 # Number of branches that were predicted taken incorrectly +system.cpu2.ipc 1.392607 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.392607 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntAlu 111470 48.49% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.49% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemRead 83479 36.31% 84.81% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34926 15.19% 100.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntAlu 134825 46.99% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 46.99% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemRead 104076 36.27% 83.27% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemWrite 48015 16.73% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::total 229875 # Type of FU issued -system.cpu2.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested -system.cpu2.iq.ISSUE:fu_busy_rate 0.000827 # FU busy rate (busy events/executed inst) +system.cpu2.iq.ISSUE:FU_type_0::total 286916 # Type of FU issued +system.cpu2.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested +system.cpu2.iq.ISSUE:fu_busy_rate 0.000690 # FU busy rate (busy events/executed inst) system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntAlu 11 5.79% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.26% 31.05% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full::MemWrite 131 68.95% 100.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemRead 55 27.78% 33.84% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemWrite 131 66.16% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:issued_per_cycle::samples 194140 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.184068 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.270828 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::samples 194280 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.476817 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.291045 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::0 86894 44.76% 44.76% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::1 30647 15.79% 60.54% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::2 37182 19.15% 79.70% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::3 34986 18.02% 97.72% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::4 2607 1.34% 99.06% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::5 1569 0.81% 99.87% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::6 161 0.08% 99.95% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0 69262 35.65% 35.65% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1 22249 11.45% 47.10% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2 50270 25.88% 72.98% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3 48052 24.73% 97.71% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::4 2627 1.35% 99.06% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::5 1560 0.80% 99.87% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::6 166 0.09% 99.95% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::7 85 0.04% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::total 194140 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:rate 1.149622 # Inst issue rate -system.cpu2.iq.iqInstsAdded 224210 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqInstsIssued 229875 # Number of instructions issued -system.cpu2.iq.iqNonSpecInstsAdded 8238 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqSquashedInstsExamined 6319 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedNonSpecRemoved 541 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.iqSquashedOperandsExamined 5841 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.memDep0.conflictingLoads 38126 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 30815 # Number of conflicting stores. -system.cpu2.memDep0.insertedLoads 77014 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 35289 # Number of stores inserted to the mem dependence unit. -system.cpu2.numCycles 199957 # number of cpu cycles simulated -system.cpu2.rename.RENAME:BlockCycles 8148 # Number of cycles rename is blocking -system.cpu2.rename.RENAME:CommittedMaps 179320 # Number of HB maps that are committed -system.cpu2.rename.RENAME:IQFullEvents 31 # Number of times rename has blocked due to IQ full -system.cpu2.rename.RENAME:IdleCycles 61271 # Number of cycles rename is idle -system.cpu2.rename.RENAME:LSQFullEvents 56 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RENAME:RenameLookups 515611 # Number of register rename lookups that rename has made -system.cpu2.rename.RENAME:RenamedInsts 273634 # Number of instructions processed by rename -system.cpu2.rename.RENAME:RenamedOperands 187411 # Number of destination operands rename has renamed -system.cpu2.rename.RENAME:RunCycles 102588 # Number of cycles rename is running -system.cpu2.rename.RENAME:SquashCycles 1720 # Number of cycles rename is squashing -system.cpu2.rename.RENAME:UnblockCycles 553 # Number of cycles rename is unblocking -system.cpu2.rename.RENAME:UndoneMaps 8091 # Number of HB maps that are undone due to squashing -system.cpu2.rename.RENAME:serializeStallCycles 13248 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RENAME:serializingInsts 943 # count of serializing insts renamed -system.cpu2.rename.RENAME:skidInsts 2678 # count of insts added to the skid buffer -system.cpu2.rename.RENAME:tempSerializingInsts 998 # count of temporary serializing insts renamed -system.cpu2.timesIdled 306 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.iq.ISSUE:issued_per_cycle::total 194280 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:rate 1.437167 # Inst issue rate +system.cpu2.iq.iqInstsAdded 284164 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqInstsIssued 286916 # Number of instructions issued +system.cpu2.iq.iqNonSpecInstsAdded 5428 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqSquashedInstsExamined 6474 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedNonSpecRemoved 533 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.iqSquashedOperandsExamined 6110 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.memDep0.conflictingLoads 48437 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 43927 # Number of conflicting stores. +system.cpu2.memDep0.insertedLoads 100435 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 48400 # Number of stores inserted to the mem dependence unit. +system.cpu2.numCycles 199640 # number of cpu cycles simulated +system.cpu2.rename.RENAME:BlockCycles 5634 # Number of cycles rename is blocking +system.cpu2.rename.RENAME:CommittedMaps 228819 # Number of HB maps that are committed +system.cpu2.rename.RENAME:IQFullEvents 67 # Number of times rename has blocked due to IQ full +system.cpu2.rename.RENAME:IdleCycles 46667 # Number of cycles rename is idle +system.cpu2.rename.RENAME:LSQFullEvents 60 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RENAME:RenameLookups 661216 # Number of register rename lookups that rename has made +system.cpu2.rename.RENAME:RenamedInsts 341037 # Number of instructions processed by rename +system.cpu2.rename.RENAME:RenamedOperands 237006 # Number of destination operands rename has renamed +system.cpu2.rename.RENAME:RunCycles 120203 # Number of cycles rename is running +system.cpu2.rename.RENAME:SquashCycles 1740 # Number of cycles rename is squashing +system.cpu2.rename.RENAME:UnblockCycles 620 # Number of cycles rename is unblocking +system.cpu2.rename.RENAME:UndoneMaps 8187 # Number of HB maps that are undone due to squashing +system.cpu2.rename.RENAME:serializeStallCycles 12791 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RENAME:serializingInsts 940 # count of serializing insts renamed +system.cpu2.rename.RENAME:skidInsts 2775 # count of insts added to the skid buffer +system.cpu2.rename.RENAME:tempSerializingInsts 995 # count of temporary serializing insts renamed +system.cpu2.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.BTBHits 51008 # Number of BTB hits -system.cpu3.BPredUnit.BTBLookups 53230 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 53101 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 55313 # Number of BTB lookups system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu3.BPredUnit.condIncorrect 1107 # Number of conditional branches incorrect -system.cpu3.BPredUnit.condPredicted 53290 # Number of conditional branches predicted -system.cpu3.BPredUnit.lookups 53290 # Number of BP lookups +system.cpu3.BPredUnit.condIncorrect 1094 # Number of conditional branches incorrect +system.cpu3.BPredUnit.condPredicted 55399 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 55399 # Number of BP lookups system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu3.commit.COM:branches 50385 # Number of branches committed +system.cpu3.commit.COM:branches 52563 # Number of branches committed system.cpu3.commit.COM:bw_lim_events 486 # number cycles where commit BW limit reached system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.commit.COM:committed_per_cycle::samples 188101 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::mean 1.497398 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::stdev 1.921379 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::samples 187872 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::mean 1.575583 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::stdev 1.953160 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::0 83023 44.14% 44.14% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::1 51203 27.22% 71.36% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::2 7476 3.97% 75.33% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::3 8063 4.29% 79.62% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::4 2451 1.30% 80.92% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::5 34897 18.55% 99.47% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::6 373 0.20% 99.67% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::0 78438 41.75% 41.75% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::1 53385 28.42% 70.17% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::2 7469 3.98% 74.14% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::3 7434 3.96% 78.10% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::4 2454 1.31% 79.41% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::5 37686 20.06% 99.46% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::6 391 0.21% 99.67% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::total 188101 # Number of insts commited each cycle -system.cpu3.commit.COM:count 281662 # Number of instructions committed -system.cpu3.commit.COM:loads 81780 # Number of loads committed -system.cpu3.commit.COM:membars 6533 # Number of memory barriers committed -system.cpu3.commit.COM:refs 119669 # Number of memory references committed +system.cpu3.commit.COM:committed_per_cycle::total 187872 # Number of insts commited each cycle +system.cpu3.commit.COM:count 296008 # Number of instructions committed +system.cpu3.commit.COM:loads 86777 # Number of loads committed +system.cpu3.commit.COM:membars 5899 # Number of memory barriers committed +system.cpu3.commit.COM:refs 127476 # Number of memory references committed system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.branchMispredicts 1107 # The number of times a branch was mispredicted -system.cpu3.commit.commitCommittedInsts 281662 # The number of committed instructions -system.cpu3.commit.commitNonSpecStalls 7252 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.commitSquashedInsts 8589 # The number of squashed insts skipped by commit -system.cpu3.committedInsts 233959 # Number of Instructions Simulated -system.cpu3.committedInsts_total 233959 # Number of Instructions Simulated -system.cpu3.cpi 0.853513 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.853513 # CPI: Total CPI of All Threads -system.cpu3.dcache.ReadReq_accesses 48481 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 22746.495327 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 48053 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 9735500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.008828 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 428 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_miss_latency 2268000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003342 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 25166.666667 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22166.666667 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 1510000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.821918 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 60 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_miss_latency 1330000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.821918 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_misses 60 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 37816 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 24138.655462 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15764.705882 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 37697 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 2872500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.003147 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 119 # number of WriteReq misses +system.cpu3.commit.branchMispredicts 1094 # The number of times a branch was mispredicted +system.cpu3.commit.commitCommittedInsts 296008 # The number of committed instructions +system.cpu3.commit.commitNonSpecStalls 6615 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.commitSquashedInsts 8397 # The number of squashed insts skipped by commit +system.cpu3.committedInsts 246758 # Number of Instructions Simulated +system.cpu3.committedInsts_total 246758 # Number of Instructions Simulated +system.cpu3.cpi 0.807958 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.807958 # CPI: Total CPI of All Threads +system.cpu3.dcache.ReadReq_accesses 50677 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 21660.356347 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13875 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 50228 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 9725500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.008860 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 449 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_hits 289 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_miss_latency 2220000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003157 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 160 # number of ReadReq MSHR misses +system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_avg_miss_latency 26068.965517 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 23068.965517 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_latency 1512000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_rate 0.828571 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_mshr_miss_latency 1338000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.828571 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 40629 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 23540.650407 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15301.886792 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 40506 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 2895500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.003027 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 123 # number of WriteReq misses system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_miss_latency 1608000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002697 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_miss_latency 1622000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002609 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 1503.551724 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1601.034483 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 86297 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 23049.360146 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14681.818182 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 85750 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 12608000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.006339 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 547 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 3876000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.003059 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_accesses 91306 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 22064.685315 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14443.609023 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 90734 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 12621000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.006265 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 572 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 306 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 3842000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.002913 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.049235 # Average percentage of cache occupancy -system.cpu3.dcache.occ_%::1 -0.015412 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 25.208240 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -7.890970 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 86297 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 23049.360146 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14681.818182 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.048988 # Average percentage of cache occupancy +system.cpu3.dcache.occ_%::1 -0.020365 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 25.081960 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -10.426668 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 91306 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 22064.685315 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14443.609023 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 85750 # number of overall hits -system.cpu3.dcache.overall_miss_latency 12608000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.006339 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 547 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 283 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 3876000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.003059 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 264 # number of overall MSHR misses +system.cpu3.dcache.overall_hits 90734 # number of overall hits +system.cpu3.dcache.overall_miss_latency 12621000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.006265 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 572 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 306 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 3842000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.002913 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 17.317269 # Cycle average of tags in use -system.cpu3.dcache.total_refs 43603 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 14.655292 # Cycle average of tags in use +system.cpu3.dcache.total_refs 46430 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.decode.DECODE:BlockedCycles 21721 # Number of cycles decode is blocked -system.cpu3.decode.DECODE:DecodedInsts 294320 # Number of instructions handled by decode -system.cpu3.decode.DECODE:IdleCycles 57795 # Number of cycles decode is idle -system.cpu3.decode.DECODE:RunCycles 102536 # Number of cycles decode is running -system.cpu3.decode.DECODE:SquashCycles 1822 # Number of cycles decode is squashing -system.cpu3.decode.DECODE:UnblockCycles 6048 # Number of cycles decode is unblocking -system.cpu3.fetch.Branches 53290 # Number of branches that fetch encountered -system.cpu3.fetch.CacheLines 21878 # Number of cache lines fetched -system.cpu3.fetch.Cycles 130861 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.IcacheSquashes 222 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.Insts 295471 # Number of instructions fetch has processed -system.cpu3.fetch.SquashCycles 1182 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.266868 # Number of branch fetches per cycle -system.cpu3.fetch.icacheStallCycles 21878 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.predictedBranches 51008 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.479671 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 196540 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.503363 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.005027 # Number of instructions fetched each cycle (Total) +system.cpu3.decode.DECODE:BlockedCycles 21089 # Number of cycles decode is blocked +system.cpu3.decode.DECODE:DecodedInsts 308413 # Number of instructions handled by decode +system.cpu3.decode.DECODE:IdleCycles 54614 # Number of cycles decode is idle +system.cpu3.decode.DECODE:RunCycles 106676 # Number of cycles decode is running +system.cpu3.decode.DECODE:SquashCycles 1792 # Number of cycles decode is squashing +system.cpu3.decode.DECODE:UnblockCycles 5492 # Number of cycles decode is unblocking +system.cpu3.fetch.Branches 55399 # Number of branches that fetch encountered +system.cpu3.fetch.CacheLines 20572 # Number of cache lines fetched +system.cpu3.fetch.Cycles 133138 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.IcacheSquashes 221 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.Insts 309543 # Number of instructions fetch has processed +system.cpu3.fetch.SquashCycles 1170 # Number of cycles fetch has spent squashing +system.cpu3.fetch.branchRate 0.277870 # Number of branch fetches per cycle +system.cpu3.fetch.icacheStallCycles 20572 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.predictedBranches 53101 # Number of branches that fetch has predicted taken +system.cpu3.fetch.rate 1.552606 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::samples 196296 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.576920 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.037630 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 87581 44.56% 44.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 56529 28.76% 73.32% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7663 3.90% 77.22% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 2862 1.46% 78.68% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1914 0.97% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 35780 18.20% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2478 1.26% 99.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 258 0.13% 99.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 1475 0.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 83755 42.67% 42.67% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 58002 29.55% 72.22% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7019 3.58% 75.79% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 2809 1.43% 77.22% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1911 0.97% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 38598 19.66% 97.86% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2463 1.25% 99.11% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 248 0.13% 99.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 1491 0.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 196540 # Number of instructions fetched each cycle (Total) -system.cpu3.icache.ReadReq_accesses 21878 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 14319.791667 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11656.884876 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 21398 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 6873500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.021940 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 480 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_miss_latency 5164000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.020249 # mshr miss rate for ReadReq accesses +system.cpu3.fetch.rateDist::total 196296 # Number of instructions fetched each cycle (Total) +system.cpu3.icache.ReadReq_accesses 20572 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 14541.928721 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11822.799097 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 20095 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 6936500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.023187 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 477 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_miss_latency 5237500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.021534 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_misses 443 # number of ReadReq MSHR misses system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 48.302483 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 45.361174 # Average number of references to valid blocks. system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 21878 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 14319.791667 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11656.884876 # average overall mshr miss latency -system.cpu3.icache.demand_hits 21398 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 6873500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.021940 # miss rate for demand accesses -system.cpu3.icache.demand_misses 480 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 37 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 5164000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.020249 # mshr miss rate for demand accesses +system.cpu3.icache.demand_accesses 20572 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 14541.928721 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11822.799097 # average overall mshr miss latency +system.cpu3.icache.demand_hits 20095 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 6936500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.023187 # miss rate for demand accesses +system.cpu3.icache.demand_misses 477 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 5237500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.021534 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.172972 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 88.561786 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 21878 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 14319.791667 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11656.884876 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.172973 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 88.562021 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 20572 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 14541.928721 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11822.799097 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 21398 # number of overall hits -system.cpu3.icache.overall_miss_latency 6873500 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.021940 # miss rate for overall accesses -system.cpu3.icache.overall_misses 480 # number of overall misses -system.cpu3.icache.overall_mshr_hits 37 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 5164000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.020249 # mshr miss rate for overall accesses +system.cpu3.icache.overall_hits 20095 # number of overall hits +system.cpu3.icache.overall_miss_latency 6936500 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.023187 # miss rate for overall accesses +system.cpu3.icache.overall_misses 477 # number of overall misses +system.cpu3.icache.overall_mshr_hits 34 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 5237500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.021534 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_misses 443 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.icache.replacements 331 # number of replacements system.cpu3.icache.sampled_refs 443 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 88.561786 # Cycle average of tags in use -system.cpu3.icache.total_refs 21398 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 88.562021 # Cycle average of tags in use +system.cpu3.icache.total_refs 20095 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idleCycles 3147 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.iew.EXEC:branches 50939 # Number of branches executed -system.cpu3.iew.EXEC:nop 42047 # number of nop insts executed -system.cpu3.iew.EXEC:rate 1.222869 # Inst execution rate -system.cpu3.iew.EXEC:refs 120748 # number of memory reference insts executed -system.cpu3.iew.EXEC:stores 38237 # Number of stores executed +system.cpu3.idleCycles 3074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.iew.EXEC:branches 53119 # Number of branches executed +system.cpu3.iew.EXEC:nop 44175 # number of nop insts executed +system.cpu3.iew.EXEC:rate 1.285981 # Inst execution rate +system.cpu3.iew.EXEC:refs 128575 # number of memory reference insts executed +system.cpu3.iew.EXEC:stores 41051 # Number of stores executed system.cpu3.iew.EXEC:swp 0 # number of swp insts executed -system.cpu3.iew.WB:consumers 140792 # num instructions consuming a value -system.cpu3.iew.WB:count 243825 # cumulative count of insts written-back -system.cpu3.iew.WB:fanout 0.974075 # average fanout of values written-back +system.cpu3.iew.WB:consumers 148618 # num instructions consuming a value +system.cpu3.iew.WB:count 256019 # cumulative count of insts written-back +system.cpu3.iew.WB:fanout 0.975407 # average fanout of values written-back system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.iew.WB:producers 137142 # num instructions producing a value -system.cpu3.iew.WB:rate 1.221036 # insts written-back per cycle -system.cpu3.iew.WB:sent 243958 # cumulative count of insts sent to commit -system.cpu3.iew.branchMispredicts 1214 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewBlockCycles 1672 # Number of cycles IEW is blocking -system.cpu3.iew.iewDispLoadInsts 83367 # Number of dispatched load instructions -system.cpu3.iew.iewDispNonSpecInsts 943 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispStoreInsts 38663 # Number of dispatched store instructions -system.cpu3.iew.iewDispatchedInsts 290280 # Number of instructions dispatched to IQ -system.cpu3.iew.iewExecLoadInsts 82511 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 965 # Number of squashed instructions skipped in execute -system.cpu3.iew.iewExecutedInsts 244191 # Number of executed instructions +system.cpu3.iew.WB:producers 144963 # num instructions producing a value +system.cpu3.iew.WB:rate 1.284140 # insts written-back per cycle +system.cpu3.iew.WB:sent 256153 # cumulative count of insts sent to commit +system.cpu3.iew.branchMispredicts 1196 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewBlockCycles 1671 # Number of cycles IEW is blocking +system.cpu3.iew.iewDispLoadInsts 88323 # Number of dispatched load instructions +system.cpu3.iew.iewDispNonSpecInsts 935 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispSquashedInsts 564 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispStoreInsts 41481 # Number of dispatched store instructions +system.cpu3.iew.iewDispatchedInsts 304435 # Number of instructions dispatched to IQ +system.cpu3.iew.iewExecLoadInsts 87524 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 961 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 256386 # Number of executed instructions system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.iewSquashCycles 1822 # Number of cycles IEW is squashing -system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu3.iew.iewSquashCycles 1792 # Number of cycles IEW is squashing +system.cpu3.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 34012 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread.0.forwLoads 36829 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 33 # Number of memory ordering violations +system.cpu3.iew.lsq.thread.0.memOrderViolation 34 # Number of memory ordering violations system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 1587 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 774 # Number of stores squashed -system.cpu3.iew.memOrderViolationEvents 33 # Number of memory order violations -system.cpu3.iew.predictedNotTakenIncorrect 191 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.predictedTakenIncorrect 1023 # Number of branches that were predicted taken incorrectly -system.cpu3.ipc 1.171629 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.171629 # IPC: Total IPC of All Threads +system.cpu3.iew.lsq.thread.0.squashedLoads 1546 # Number of loads squashed +system.cpu3.iew.lsq.thread.0.squashedStores 782 # Number of stores squashed +system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations +system.cpu3.iew.predictedNotTakenIncorrect 194 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.predictedTakenIncorrect 1002 # Number of branches that were predicted taken incorrectly +system.cpu3.ipc 1.237689 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.237689 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntAlu 117660 47.99% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemRead 89228 36.40% 84.39% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemWrite 38268 15.61% 100.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntAlu 122656 47.66% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.66% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemRead 93608 36.37% 84.04% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemWrite 41083 15.96% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::total 245156 # Type of FU issued -system.cpu3.iq.ISSUE:fu_busy_cnt 195 # FU busy when requested -system.cpu3.iq.ISSUE:fu_busy_rate 0.000795 # FU busy rate (busy events/executed inst) +system.cpu3.iq.ISSUE:FU_type_0::total 257347 # Type of FU issued +system.cpu3.iq.ISSUE:fu_busy_cnt 199 # FU busy when requested +system.cpu3.iq.ISSUE:fu_busy_rate 0.000773 # FU busy rate (busy events/executed inst) system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntAlu 10 5.13% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.13% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemRead 54 27.69% 32.82% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemWrite 131 67.18% 100.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntAlu 11 5.53% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.53% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemRead 57 28.64% 34.17% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemWrite 131 65.83% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:issued_per_cycle::samples 196540 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::mean 1.247359 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 1.278033 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::samples 196296 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 1.311015 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 1.285531 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::0 83952 42.71% 42.71% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::1 29215 14.86% 57.58% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::2 40646 20.68% 78.26% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::3 38400 19.54% 97.80% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::4 2533 1.29% 99.09% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::5 1549 0.79% 99.88% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::6 153 0.08% 99.95% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0 79991 40.75% 40.75% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1 27327 13.92% 54.67% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2 43412 22.12% 76.79% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3 41220 21.00% 97.79% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::4 2543 1.30% 99.08% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::5 1556 0.79% 99.87% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::6 155 0.08% 99.95% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::total 196540 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:rate 1.227701 # Inst issue rate -system.cpu3.iq.iqInstsAdded 240287 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqInstsIssued 245156 # Number of instructions issued -system.cpu3.iq.iqNonSpecInstsAdded 7946 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqSquashedInstsExamined 6812 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.iqSquashedOperandsExamined 6560 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.memDep0.conflictingLoads 41143 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 34165 # Number of conflicting stores. -system.cpu3.memDep0.insertedLoads 83367 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 38663 # Number of stores inserted to the mem dependence unit. -system.cpu3.numCycles 199687 # number of cpu cycles simulated -system.cpu3.rename.RENAME:BlockCycles 7785 # Number of cycles rename is blocking -system.cpu3.rename.RENAME:CommittedMaps 192153 # Number of HB maps that are committed -system.cpu3.rename.RENAME:IQFullEvents 59 # Number of times rename has blocked due to IQ full -system.cpu3.rename.RENAME:IdleCycles 58421 # Number of cycles rename is idle -system.cpu3.rename.RENAME:LSQFullEvents 39 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RENAME:RenameLookups 554540 # Number of register rename lookups that rename has made -system.cpu3.rename.RENAME:RenamedInsts 292537 # Number of instructions processed by rename -system.cpu3.rename.RENAME:RenamedOperands 200475 # Number of destination operands rename has renamed -system.cpu3.rename.RENAME:RunCycles 108103 # Number of cycles rename is running -system.cpu3.rename.RENAME:SquashCycles 1822 # Number of cycles rename is squashing -system.cpu3.rename.RENAME:UnblockCycles 588 # Number of cycles rename is unblocking -system.cpu3.rename.RENAME:UndoneMaps 8322 # Number of HB maps that are undone due to squashing -system.cpu3.rename.RENAME:serializeStallCycles 13203 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RENAME:serializingInsts 964 # count of serializing insts renamed -system.cpu3.rename.RENAME:skidInsts 2784 # count of insts added to the skid buffer -system.cpu3.rename.RENAME:tempSerializingInsts 1016 # count of temporary serializing insts renamed -system.cpu3.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.iq.ISSUE:issued_per_cycle::total 196296 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:rate 1.290801 # Inst issue rate +system.cpu3.iq.iqInstsAdded 253019 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqInstsIssued 257347 # Number of instructions issued +system.cpu3.iq.iqNonSpecInstsAdded 7241 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqSquashedInstsExamined 6661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedNonSpecRemoved 626 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.iqSquashedOperandsExamined 6379 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.memDep0.conflictingLoads 43278 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 36990 # Number of conflicting stores. +system.cpu3.memDep0.insertedLoads 88323 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 41481 # Number of stores inserted to the mem dependence unit. +system.cpu3.numCycles 199370 # number of cpu cycles simulated +system.cpu3.rename.RENAME:BlockCycles 7226 # Number of cycles rename is blocking +system.cpu3.rename.RENAME:CommittedMaps 202775 # Number of HB maps that are committed +system.cpu3.rename.RENAME:IQFullEvents 58 # Number of times rename has blocked due to IQ full +system.cpu3.rename.RENAME:IdleCycles 55235 # Number of cycles rename is idle +system.cpu3.rename.RENAME:LSQFullEvents 44 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RENAME:RenameLookups 585183 # Number of register rename lookups that rename has made +system.cpu3.rename.RENAME:RenamedInsts 306652 # Number of instructions processed by rename +system.cpu3.rename.RENAME:RenamedOperands 211061 # Number of destination operands rename has renamed +system.cpu3.rename.RENAME:RunCycles 111693 # Number of cycles rename is running +system.cpu3.rename.RENAME:SquashCycles 1792 # Number of cycles rename is squashing +system.cpu3.rename.RENAME:UnblockCycles 593 # Number of cycles rename is unblocking +system.cpu3.rename.RENAME:UndoneMaps 8286 # Number of HB maps that are undone due to squashing +system.cpu3.rename.RENAME:serializeStallCycles 13124 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RENAME:serializingInsts 957 # count of serializing insts renamed +system.cpu3.rename.RENAME:skidInsts 2808 # count of insts added to the skid buffer +system.cpu3.rename.RENAME:tempSerializingInsts 1009 # count of temporary serializing insts renamed +system.cpu3.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) @@ -1526,50 +1527,50 @@ system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # ms system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses system.l2c.ReadReq_accesses::0 689 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 459 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 456 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 457 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 450 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::3 456 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2060 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 63648.106904 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2381500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 340214.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 5715600 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 8500962.392619 # average ReadReq miss latency +system.l2c.ReadReq_accesses::total 2052 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 63653.674833 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 2381708.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 348542.682927 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 4082928.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 6876833.262522 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40001.841621 # average ReadReq mshr miss latency system.l2c.ReadReq_hits::0 240 # number of ReadReq hits -system.l2c.ReadReq_hits::1 447 # number of ReadReq hits -system.l2c.ReadReq_hits::2 372 # number of ReadReq hits -system.l2c.ReadReq_hits::3 451 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1510 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 28578000 # number of ReadReq miss cycles +system.l2c.ReadReq_hits::1 445 # number of ReadReq hits +system.l2c.ReadReq_hits::2 368 # number of ReadReq hits +system.l2c.ReadReq_hits::3 449 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1502 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 28580500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_rate::0 0.651669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026144 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.184211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.010965 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.872988 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026258 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.182222 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.015351 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.875500 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 449 # number of ReadReq misses system.l2c.ReadReq_misses::1 12 # number of ReadReq misses -system.l2c.ReadReq_misses::2 84 # number of ReadReq misses -system.l2c.ReadReq_misses::3 5 # number of ReadReq misses +system.l2c.ReadReq_misses::2 82 # number of ReadReq misses +system.l2c.ReadReq_misses::3 7 # number of ReadReq misses system.l2c.ReadReq_misses::total 550 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 21721000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::0 0.788099 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.183007 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.190789 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.188184 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.206667 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::3 1.190789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.352684 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.373739 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 543 # number of ReadReq MSHR misses system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 98 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 23 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 97 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 7428.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 6240 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 6782.608696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 26451.180124 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 6782.608696 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 6500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 26711.180124 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits @@ -1581,119 +1582,119 @@ system.l2c.UpgradeReq_miss_rate::3 1 # mi system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 25 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 95 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3800000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 3.275862 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.523810 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 3.800000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 4.130435 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 15.730106 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 95 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::2 23 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 24 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 94 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 3760000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 3.241379 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.476190 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 4.086957 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 3.916667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 15.721193 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 94 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.765138 # Average number of references to valid blocks. +system.l2c.avg_refs 2.750459 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses::0 783 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 471 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 469 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 469 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 463 # number of demand (read+write) accesses system.l2c.demand_accesses::3 468 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2191 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 65294.659300 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1477291.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 365515.463918 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 2085588.235294 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3993690.025178 # average overall miss latency +system.l2c.demand_accesses::total 2183 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 65299.263352 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1477395.833333 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 373236.842105 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1866184.210526 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3782116.149317 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency system.l2c.demand_hits::0 240 # number of demand (read+write) hits -system.l2c.demand_hits::1 447 # number of demand (read+write) hits -system.l2c.demand_hits::2 372 # number of demand (read+write) hits -system.l2c.demand_hits::3 451 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510 # number of demand (read+write) hits -system.l2c.demand_miss_latency 35455000 # number of demand (read+write) miss cycles +system.l2c.demand_hits::1 445 # number of demand (read+write) hits +system.l2c.demand_hits::2 368 # number of demand (read+write) hits +system.l2c.demand_hits::3 449 # number of demand (read+write) hits +system.l2c.demand_hits::total 1502 # number of demand (read+write) hits +system.l2c.demand_miss_latency 35457500 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate::0 0.693487 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.050955 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.206823 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.036325 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.987590 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.051173 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.205184 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.040598 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.990441 # miss rate for demand accesses system.l2c.demand_misses::0 543 # number of demand (read+write) misses system.l2c.demand_misses::1 24 # number of demand (read+write) misses -system.l2c.demand_misses::2 97 # number of demand (read+write) misses -system.l2c.demand_misses::3 17 # number of demand (read+write) misses +system.l2c.demand_misses::2 95 # number of demand (read+write) misses +system.l2c.demand_misses::3 19 # number of demand (read+write) misses system.l2c.demand_misses::total 681 # number of demand (read+write) misses system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 26999000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0.860792 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.430998 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.437100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.437100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.455724 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::3 1.440171 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.169061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.193787 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 674 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.005562 # Average percentage of cache occupancy +system.l2c.occ_%::0 0.005561 # Average percentage of cache occupancy system.l2c.occ_%::1 0.000141 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.000962 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.000050 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000078 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 364.482094 # Average occupied blocks per context -system.l2c.occ_blocks::1 9.273148 # Average occupied blocks per context -system.l2c.occ_blocks::2 63.060647 # Average occupied blocks per context -system.l2c.occ_blocks::3 3.262767 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.106132 # Average occupied blocks per context +system.l2c.occ_%::2 0.000959 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000053 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000079 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 364.466495 # Average occupied blocks per context +system.l2c.occ_blocks::1 9.271638 # Average occupied blocks per context +system.l2c.occ_blocks::2 62.868915 # Average occupied blocks per context +system.l2c.occ_blocks::3 3.440920 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.201108 # Average occupied blocks per context system.l2c.overall_accesses::0 783 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 471 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 469 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 469 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 463 # number of overall (read+write) accesses system.l2c.overall_accesses::3 468 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2191 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 65294.659300 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1477291.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 365515.463918 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 2085588.235294 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3993690.025178 # average overall miss latency +system.l2c.overall_accesses::total 2183 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 65299.263352 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1477395.833333 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 373236.842105 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1866184.210526 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3782116.149317 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits::0 240 # number of overall hits -system.l2c.overall_hits::1 447 # number of overall hits -system.l2c.overall_hits::2 372 # number of overall hits -system.l2c.overall_hits::3 451 # number of overall hits -system.l2c.overall_hits::total 1510 # number of overall hits -system.l2c.overall_miss_latency 35455000 # number of overall miss cycles +system.l2c.overall_hits::1 445 # number of overall hits +system.l2c.overall_hits::2 368 # number of overall hits +system.l2c.overall_hits::3 449 # number of overall hits +system.l2c.overall_hits::total 1502 # number of overall hits +system.l2c.overall_miss_latency 35457500 # number of overall miss cycles system.l2c.overall_miss_rate::0 0.693487 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.050955 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.206823 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.036325 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.987590 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.051173 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.205184 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.040598 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.990441 # miss rate for overall accesses system.l2c.overall_misses::0 543 # number of overall misses system.l2c.overall_misses::1 24 # number of overall misses -system.l2c.overall_misses::2 97 # number of overall misses -system.l2c.overall_misses::3 17 # number of overall misses +system.l2c.overall_misses::2 95 # number of overall misses +system.l2c.overall_misses::3 19 # number of overall misses system.l2c.overall_misses::total 681 # number of overall misses system.l2c.overall_mshr_hits 7 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 26999000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0.860792 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.430998 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.437100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.437100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.455724 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::3 1.440171 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.169061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.193787 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 674 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements system.l2c.sampled_refs 545 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 445.184788 # Cycle average of tags in use -system.l2c.total_refs 1507 # Total number of references to valid blocks. +system.l2c.tagsinuse 445.249076 # Cycle average of tags in use +system.l2c.total_refs 1499 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks |