diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
| commit | da2a4acc26ba264c3c4a12495776fd6a1c4fb133 (patch) | |
| tree | f142100388b9d1403492c97b0d323728ce18ef8a /tests | |
| parent | 241cc0c8402f1b9f2ec20d1cc152d96930959b2a (diff) | |
| parent | a7394ad6807bd5e85f680184bf308673ca00534a (diff) | |
| download | gem5-da2a4acc26ba264c3c4a12495776fd6a1c4fb133.tar.xz | |
Merge yet again with the main repository.
Diffstat (limited to 'tests')
110 files changed, 4195 insertions, 4156 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index a12b8078f..c626036a3 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index ffb5e6ddd..d3f649818 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index db687aea5..9655899ee 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -3,26 +3,26 @@ sim_seconds 0.586294 # Number of seconds simulated sim_ticks 586294224000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112274 # Simulator instruction rate (inst/s) -host_tick_rate 40595683 # Simulator tick rate (ticks/s) -host_mem_usage 244844 # Number of bytes of host memory used -host_seconds 14442.28 # Real time elapsed on the host +host_inst_rate 115446 # Simulator instruction rate (inst/s) +host_tick_rate 41742717 # Simulator tick rate (ticks/s) +host_mem_usage 244900 # Number of bytes of host memory used +host_seconds 14045.43 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1172588449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 142448983 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142448983 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 142448982 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142448982 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 134509889 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 134509888 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1143761055 # Number of instructions fetch has processed -system.cpu.fetch.Branches 142448983 # Number of branches that fetch encountered +system.cpu.fetch.Insts 1143761054 # Number of instructions fetch has processed +system.cpu.fetch.Branches 142448982 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing @@ -66,32 +66,32 @@ system.cpu.rename.RenamedInsts 2043122328 # Nu system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2031527324 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4954653616 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4954649396 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 2031527322 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4954653611 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4954649391 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 413532674 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 413532672 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 91 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 148937435 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1986583518 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1781630005 # Number of instructions issued +system.cpu.memDep0.conflictingStores 148937436 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1986583516 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 218 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1781630004 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 670712331 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 670712329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 168 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271921708 23.19% 23.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 416937500 35.56% 58.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271921709 23.19% 23.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 416937499 35.56% 58.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle @@ -138,7 +138,7 @@ system.cpu.iq.fu_full::MemWrite 148998 5.73% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1102052870 61.86% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1102052869 61.86% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued @@ -171,17 +171,17 @@ system.cpu.iq.FU_type_0::MemRead 457985397 25.71% 89.07% # Ty system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1781630005 # Type of FU issued +system.cpu.iq.FU_type_0::total 1781630004 # Type of FU issued system.cpu.iq.rate 1.519399 # Inst issue rate system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4738479065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4738479063 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1760053766 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 1760053765 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1757334382 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1757334381 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -208,7 +208,7 @@ system.cpu.iew.memOrderViolationEvents 216417 # Nu system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1768232809 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 1768232808 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed @@ -217,8 +217,8 @@ system.cpu.iew.exec_refs 645919458 # nu system.cpu.iew.exec_branches 112169596 # Number of branches executed system.cpu.iew.exec_stores 193872240 # Number of stores executed system.cpu.iew.exec_rate 1.507974 # Inst execution rate -system.cpu.iew.wb_sent 1766226830 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1760053778 # cumulative count of insts written-back +system.cpu.iew.wb_sent 1766226829 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1760053777 # cumulative count of insts written-back system.cpu.iew.wb_producers 1336567337 # num instructions producing a value system.cpu.iew.wb_consumers 2003494286 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ @@ -268,9 +268,9 @@ system.cpu.cpi_total 0.723153 # CP system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads -system.cpu.int_regfile_writes 1756091293 # number of integer regfile writes +system.cpu.int_regfile_writes 1756091292 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 908871446 # number of misc regfile reads +system.cpu.misc_regfile_reads 908871445 # number of misc regfile reads system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.tagsinuse 810.394392 # Cycle average of tags in use system.cpu.icache.total_refs 137025977 # Total number of references to valid blocks. diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6c9d60230..dd4d7f0aa 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,12 +62,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index b229bc589..510b69206 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:22:36 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index f6fa9ef1e..a5e9437b0 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3280168 # Simulator instruction rate (inst/s) -host_mem_usage 202508 # Number of bytes of host memory used -host_seconds 494.33 # Real time elapsed on the host -host_tick_rate 1950088412 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated sim_ticks 963992704000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1220339 # Simulator instruction rate (inst/s) +host_tick_rate 725502264 # Simulator tick rate (ticks/s) +host_mem_usage 234168 # Number of bytes of host memory used +host_seconds 1328.72 # Real time elapsed on the host +sim_insts 1621493983 # Number of instructions simulated +system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1927985409 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1927985409 # Number of busy cycles -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written -system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions -system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1927985409 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index fa700a969..129642a98 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,12 +165,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index eb8442791..613f79639 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:23:09 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 1cc5290ea..5aedfb687 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2023797 # Simulator instruction rate (inst/s) -host_mem_usage 210248 # Number of bytes of host memory used -host_seconds 801.21 # Real time elapsed on the host -host_tick_rate 2250658484 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated sim_ticks 1803258587000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 760773 # Simulator instruction rate (inst/s) +host_tick_rate 846053445 # Simulator tick rate (ticks/s) +host_mem_usage 242892 # Number of bytes of host memory used +host_seconds 2131.38 # Real time elapsed on the host +sim_insts 1621493983 # Number of instructions simulated +system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.numCycles 3606517174 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1621493983 # Number of instructions executed +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_store_insts 188186057 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 3606517174 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use +system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits +system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1186516018 # number of overall hits +system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses +system.cpu.icache.demand_misses 722 # number of demand (read+write) misses +system.cpu.icache.overall_misses 722 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 437952 # number of replacements +system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits +system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 606786134 # number of overall hits +system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses +system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 442048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses -system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses +system.cpu.dcache.writebacks 396372 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606786134 # number of overall hits -system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses -system.cpu.dcache.overall_misses 442048 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 396372 # number of writebacks -system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 722 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1186516018 # number of overall hits -system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 722 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use -system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 71208 # number of replacements +system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 353302 # number of overall hits +system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits +system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 89468 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353302 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 89468 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 71208 # number of replacements -system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58007 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3606517174 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 3606517174 # Number of busy cycles -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses -system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read -system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written -system.cpu.num_load_insts 419042125 # Number of load instructions -system.cpu.num_mem_refs 607228182 # number of memory refs -system.cpu.num_store_insts 188186057 # Number of store instructions -system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index fb7470780..e6a0de845 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -9,18 +9,19 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.nvmem system.physmem midr_regval=890224640 +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1495,6 +1496,7 @@ port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side [system.vncserver] type=VncServer +frame_capture=false number=0 port=5900 diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index caf37a67b..13d4b63f2 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout +Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:32:34 -gem5 started Nov 22 2011 02:00:14 -gem5 executing on u200540-lin +gem5 compiled Jan 8 2012 22:12:58 +gem5 started Jan 9 2012 03:33:38 +gem5 executing on zizzer command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2582494395500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index fc137bfb1..3163bcf32 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -3,10 +3,10 @@ sim_seconds 2.582494 # Number of seconds simulated sim_ticks 2582494395500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86259 # Simulator instruction rate (inst/s) -host_tick_rate 2789337609 # Simulator tick rate (ticks/s) -host_mem_usage 380504 # Number of bytes of host memory used -host_seconds 925.85 # Real time elapsed on the host +host_inst_rate 65512 # Simulator instruction rate (inst/s) +host_tick_rate 2118472138 # Simulator tick rate (ticks/s) +host_mem_usage 384260 # Number of bytes of host memory used +host_seconds 1219.04 # Real time elapsed on the host sim_insts 79862069 # Number of instructions simulated system.l2c.replacements 132200 # number of replacements system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use @@ -312,12 +312,12 @@ system.cpu0.rename.ROBFullEvents 1483 # Nu system.cpu0.rename.IQFullEvents 580883 # Number of times rename has blocked due to IQ full system.cpu0.rename.LSQFullEvents 3149232 # Number of times rename has blocked due to LSQ full system.cpu0.rename.FullRegisterEvents 205 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54779836 # Number of destination operands rename has renamed +system.cpu0.rename.RenamedOperands 54779837 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 247536349 # Number of register rename lookups that rename has made system.cpu0.rename.int_rename_lookups 247487579 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 48770 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 41441157 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13338678 # Number of HB maps that are undone due to squashing +system.cpu0.rename.UndoneMaps 13338679 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 828868 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 763855 # count of temporary serializing insts renamed system.cpu0.rename.skidInsts 8500592 # count of insts added to the skid buffer @@ -325,13 +325,13 @@ system.cpu0.memDep0.insertedLoads 11770384 # Nu system.cpu0.memDep0.insertedStores 7686805 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 1443183 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 1570137 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50961906 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1297751 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 80276175 # Number of instructions issued +system.cpu0.iq.iqInstsAdded 50961905 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1297752 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 80276174 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 137636 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 9888896 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedOperandsExamined 22816025 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 253323 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedNonSpecRemoved 253324 # Number of squashed non-spec instructions that were removed system.cpu0.iq.issued_per_cycle::samples 109741052 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::mean 0.731505 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::stdev 1.440076 # Number of insts issued each cycle @@ -340,8 +340,8 @@ system.cpu0.iq.issued_per_cycle::0 80125799 73.01% 73.01% # Nu system.cpu0.iq.issued_per_cycle::1 10111373 9.21% 82.23% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 4133530 3.77% 85.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 3177611 2.90% 88.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9954077 9.07% 97.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1265280 1.15% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 9954078 9.07% 97.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1265279 1.15% 99.11% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 670333 0.61% 99.72% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 224189 0.20% 99.93% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 78860 0.07% 100.00% # Number of insts issued each cycle @@ -384,7 +384,7 @@ system.cpu0.iq.fu_full::MemWrite 285533 3.56% 100.00% # at system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29731482 37.04% 37.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29731481 37.04% 37.15% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 62351 0.08% 37.22% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.22% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.22% # Type of FU issued @@ -417,17 +417,17 @@ system.cpu0.iq.FU_type_0::MemRead 43135014 53.73% 90.96% # Ty system.cpu0.iq.FU_type_0::MemWrite 7257159 9.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 80276175 # Type of FU issued +system.cpu0.iq.FU_type_0::total 80276174 # Type of FU issued system.cpu0.iq.rate 0.227757 # Inst issue rate system.cpu0.iq.fu_busy_cnt 8028360 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.100009 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 278513866 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_reads 278513864 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 62161443 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 46668616 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_wakeup_accesses 46668615 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 11568 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 6980 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 5172 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 88210043 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 88210042 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 6031 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 399886 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -447,14 +447,14 @@ system.cpu0.iew.iewDispatchedInsts 52433539 # Nu system.cpu0.iew.iewDispSquashedInsts 243567 # Number of squashed instructions skipped by dispatch system.cpu0.iew.iewDispLoadInsts 11770384 # Number of dispatched load instructions system.cpu0.iew.iewDispStoreInsts 7686805 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 865739 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispNonSpecInsts 865740 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 62160 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 5553 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 20554 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 507509 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 136100 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 643609 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 79551296 # Number of executed instructions +system.cpu0.iew.iewExecutedInsts 79551295 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 42843907 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 724879 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed @@ -463,8 +463,8 @@ system.cpu0.iew.exec_refs 50011427 # nu system.cpu0.iew.exec_branches 6433542 # Number of branches executed system.cpu0.iew.exec_stores 7167520 # Number of stores executed system.cpu0.iew.exec_rate 0.225700 # Inst execution rate -system.cpu0.iew.wb_sent 79133798 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 46673788 # cumulative count of insts written-back +system.cpu0.iew.wb_sent 79133797 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 46673787 # cumulative count of insts written-back system.cpu0.iew.wb_producers 24793926 # num instructions producing a value system.cpu0.iew.wb_consumers 46078393 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ @@ -514,8 +514,8 @@ system.cpu0.cpi 8.431852 # CP system.cpu0.cpi_total 8.431852 # CPI: Total CPI of All Threads system.cpu0.ipc 0.118598 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.118598 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 354175082 # number of integer regfile reads -system.cpu0.int_regfile_writes 46137252 # number of integer regfile writes +system.cpu0.int_regfile_reads 354175079 # number of integer regfile reads +system.cpu0.int_regfile_writes 46137251 # number of integer regfile writes system.cpu0.fp_regfile_reads 4205 # number of floating regfile reads system.cpu0.fp_regfile_writes 1348 # number of floating regfile writes system.cpu0.misc_regfile_reads 65629786 # number of misc regfile reads diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal Binary files differindex b680faba9..0453fa273 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index b9ffca20c..0e78591b5 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -9,18 +9,19 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.nvmem system.physmem midr_regval=890224640 +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -1041,6 +1042,7 @@ port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side s [system.vncserver] type=VncServer +frame_capture=false number=0 port=5900 diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 61a472c55..9d4c8ae86 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout +Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:32:34 -gem5 started Nov 22 2011 02:00:08 -gem5 executing on u200540-lin +gem5 compiled Jan 8 2012 22:12:58 +gem5 started Jan 9 2012 03:32:35 +gem5 executing on zizzer command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2503566110500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b782cd5c8..768983a75 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -3,10 +3,10 @@ sim_seconds 2.503566 # Number of seconds simulated sim_ticks 2503566110500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84156 # Simulator instruction rate (inst/s) -host_tick_rate 2743719152 # Simulator tick rate (ticks/s) -host_mem_usage 380536 # Number of bytes of host memory used -host_seconds 912.47 # Real time elapsed on the host +host_inst_rate 72389 # Simulator instruction rate (inst/s) +host_tick_rate 2360079964 # Simulator tick rate (ticks/s) +host_mem_usage 384076 # Number of bytes of host memory used +host_seconds 1060.80 # Real time elapsed on the host sim_insts 76790007 # Number of instructions simulated system.l2c.replacements 119509 # number of replacements system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use @@ -270,12 +270,12 @@ system.cpu.rename.ROBFullEvents 4400 # Nu system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118358542 # Number of destination operands rename has renamed +system.cpu.rename.RenamedOperands 118358543 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40865823 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 40865824 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer @@ -283,13 +283,13 @@ system.cpu.memDep0.insertedLoads 21982315 # Nu system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102860212 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1874615 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126873317 # Number of instructions issued +system.cpu.iq.iqInstsAdded 102860211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1874616 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126873316 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 374922 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedNonSpecRemoved 374923 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle @@ -298,8 +298,8 @@ system.cpu.iq.issued_per_cycle::0 108919716 70.03% 70.03% # Nu system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12766128 8.21% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2735747 1.76% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12766129 8.21% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2735746 1.76% 98.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle @@ -342,7 +342,7 @@ system.cpu.iq.fu_full::MemWrite 436630 4.91% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60069483 47.35% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60069482 47.35% 47.43% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued @@ -375,17 +375,17 @@ system.cpu.iq.FU_type_0::MemRead 53942685 42.52% 90.02% # Ty system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126873317 # Type of FU issued +system.cpu.iq.FU_type_0::total 126873316 # Type of FU issued system.cpu.iq.rate 0.305048 # Inst issue rate system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 418533130 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 418533128 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87292109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 87292108 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135654306 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 135654305 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -405,14 +405,14 @@ system.cpu.iew.iewDispatchedInsts 104949442 # Nu system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1228030 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispNonSpecInsts 1228031 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123429780 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 123429779 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed @@ -421,8 +421,8 @@ system.cpu.iew.exec_refs 65401525 # nu system.cpu.iew.exec_branches 11705842 # Number of branches executed system.cpu.iew.exec_stores 12487221 # Number of stores executed system.cpu.iew.exec_rate 0.296769 # Inst execution rate -system.cpu.iew.wb_sent 121771134 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87302555 # cumulative count of insts written-back +system.cpu.iew.wb_sent 121771133 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87302554 # cumulative count of insts written-back system.cpu.iew.wb_producers 47043389 # num instructions producing a value system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ @@ -472,8 +472,8 @@ system.cpu.cpi 5.416227 # CP system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 559625789 # number of integer regfile reads -system.cpu.int_regfile_writes 89694790 # number of integer regfile writes +system.cpu.int_regfile_reads 559625786 # number of integer regfile reads +system.cpu.int_regfile_writes 89694789 # number of integer regfile writes system.cpu.fp_regfile_reads 8322 # number of floating regfile reads system.cpu.fp_regfile_writes 2832 # number of floating regfile writes system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 720c151c8..1dbe30c5e 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 5371c92be..9ef75afe6 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,10 +15,11 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table @@ -1301,7 +1302,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1321,7 +1322,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 795bcf9d9..18f42b689 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:24:08 -gem5 started Nov 21 2011 23:30:30 -gem5 executing on u200540-lin -command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Jan 9 2012 20:47:38 +gem5 started Jan 9 2012 21:13:16 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5145286546500 because m5_exit instruction encountered +Exiting @ tick 5161177988500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f0652d752..e687ea7eb 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.145287 # Number of seconds simulated -sim_ticks 5145286546500 # Number of ticks simulated +sim_seconds 5.161178 # Number of seconds simulated +sim_ticks 5161177988500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333179 # Simulator instruction rate (inst/s) -host_tick_rate 2041066369 # Simulator tick rate (ticks/s) -host_mem_usage 358476 # Number of bytes of host memory used -host_seconds 2520.88 # Real time elapsed on the host -sim_insts 839904894 # Number of instructions simulated -system.l2c.replacements 171120 # number of replacements -system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use -system.l2c.total_refs 3818646 # Total number of references to valid blocks. -system.l2c.sampled_refs 206013 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.535947 # Average number of references to valid blocks. +host_inst_rate 384526 # Simulator instruction rate (inst/s) +host_tick_rate 2360358751 # Simulator tick rate (ticks/s) +host_mem_usage 386468 # Number of bytes of host memory used +host_seconds 2186.61 # Real time elapsed on the host +sim_insts 840808469 # Number of instructions simulated +system.l2c.replacements 169467 # number of replacements +system.l2c.tagsinuse 38339.786444 # Cycle average of tags in use +system.l2c.total_refs 3812924 # Total number of references to valid blocks. +system.l2c.sampled_refs 204660 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.630529 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11983.527500 # Average occupied blocks per context -system.l2c.occ_blocks::1 26428.399366 # Average occupied blocks per context -system.l2c.occ_percent::0 0.182854 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403265 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2330328 # number of ReadReq hits -system.l2c.ReadReq_hits::1 145914 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2476242 # number of ReadReq hits -system.l2c.Writeback_hits::0 1599020 # number of Writeback hits -system.l2c.Writeback_hits::total 1599020 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 343 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 150210 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 150210 # number of ReadExReq hits -system.l2c.demand_hits::0 2480538 # number of demand (read+write) hits -system.l2c.demand_hits::1 145914 # number of demand (read+write) hits -system.l2c.demand_hits::total 2626452 # number of demand (read+write) hits -system.l2c.overall_hits::0 2480538 # number of overall hits -system.l2c.overall_hits::1 145914 # number of overall hits -system.l2c.overall_hits::total 2626452 # number of overall hits -system.l2c.ReadReq_misses::0 68080 # number of ReadReq misses -system.l2c.ReadReq_misses::1 84 # number of ReadReq misses -system.l2c.ReadReq_misses::total 68164 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3905 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3905 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142426 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142426 # number of ReadExReq misses -system.l2c.demand_misses::0 210506 # number of demand (read+write) misses -system.l2c.demand_misses::1 84 # number of demand (read+write) misses -system.l2c.demand_misses::total 210590 # number of demand (read+write) misses -system.l2c.overall_misses::0 210506 # number of overall misses -system.l2c.overall_misses::1 84 # number of overall misses -system.l2c.overall_misses::total 210590 # number of overall misses -system.l2c.ReadReq_miss_latency 3574844000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 37228000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7453066500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 11027910500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 11027910500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2398408 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 145998 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2544406 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1599020 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1599020 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4248 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4248 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292636 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2691044 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 145998 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2837042 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2691044 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 145998 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2837042 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.028385 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000575 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028961 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.919256 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.486700 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.078225 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000575 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.078800 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.078225 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000575 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.078800 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52509.459459 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 42557666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42610176.126126 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 9533.418694 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11950.408174 # Average occupied blocks per context +system.l2c.occ_blocks::1 26389.378270 # Average occupied blocks per context +system.l2c.occ_percent::0 0.182349 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.402670 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2335607 # number of ReadReq hits +system.l2c.ReadReq_hits::1 145488 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2481095 # number of ReadReq hits +system.l2c.Writeback_hits::0 1594493 # number of Writeback hits +system.l2c.Writeback_hits::total 1594493 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 327 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 327 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 150672 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 150672 # number of ReadExReq hits +system.l2c.demand_hits::0 2486279 # number of demand (read+write) hits +system.l2c.demand_hits::1 145488 # number of demand (read+write) hits +system.l2c.demand_hits::total 2631767 # number of demand (read+write) hits +system.l2c.overall_hits::0 2486279 # number of overall hits +system.l2c.overall_hits::1 145488 # number of overall hits +system.l2c.overall_hits::total 2631767 # number of overall hits +system.l2c.ReadReq_misses::0 66850 # number of ReadReq misses +system.l2c.ReadReq_misses::1 109 # number of ReadReq misses +system.l2c.ReadReq_misses::total 66959 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3932 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3932 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142221 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142221 # number of ReadExReq misses +system.l2c.demand_misses::0 209071 # number of demand (read+write) misses +system.l2c.demand_misses::1 109 # number of demand (read+write) misses +system.l2c.demand_misses::total 209180 # number of demand (read+write) misses +system.l2c.overall_misses::0 209071 # number of overall misses +system.l2c.overall_misses::1 109 # number of overall misses +system.l2c.overall_misses::total 209180 # number of overall misses +system.l2c.ReadReq_miss_latency 3511861000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 38996000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7442399000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 10954260000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 10954260000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2402457 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 145597 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2548054 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1594493 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1594493 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4259 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4259 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292893 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292893 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2695350 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 145597 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2840947 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2695350 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 145597 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2840947 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027826 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000749 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028574 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.923221 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.485573 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.077567 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000749 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.078316 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.077567 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000749 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.078316 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52533.448018 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 32218908.256881 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 32271441.704899 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 9917.599186 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52329.395616 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52329.817678 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52387.630281 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 131284648.809524 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 131337036.439805 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52387.630281 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 131284648.809524 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 131337036.439805 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52394.928039 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 100497798.165138 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 100550193.093176 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52394.928039 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 100497798.165138 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 100550193.093176 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,58 +100,58 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142550 # number of writebacks +system.l2c.writebacks 142631 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 68162 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3905 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142426 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 210588 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 210588 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 66957 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3932 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142221 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 209178 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 209178 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2743592500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 156565000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5717024500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8460617000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8460617000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61532546500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222452000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62754998500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028420 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.466869 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.495289 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.919256 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2695362500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 157637000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5708607000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8403969500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8403969500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 59978490000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1230737500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 61209227500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027870 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.459879 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.487749 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.923221 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.486700 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.485573 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.078255 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.442403 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.520658 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.078255 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.442403 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.520658 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40251.056307 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.469910 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40140.314971 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.077607 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.436692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.514299 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.077607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.436692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.514299 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40255.126424 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40090.793489 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40138.987913 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47572 # number of replacements -system.iocache.tagsinuse 0.146650 # Cycle average of tags in use +system.iocache.replacements 47573 # number of replacements +system.iocache.tagsinuse 0.195398 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994510051000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.146650 # Average occupied blocks per context -system.iocache.occ_percent::1 0.009166 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994542788000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.195398 # Average occupied blocks per context +system.iocache.occ_percent::1 0.012212 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -168,10 +168,10 @@ system.iocache.demand_misses::total 47627 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 47627 # number of overall misses system.iocache.overall_misses::total 47627 # number of overall misses -system.iocache.ReadReq_miss_latency 113785932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6369912160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6483698092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6483698092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 113669932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6372391160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6486061092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6486061092 # number of overall miss cycles system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) @@ -191,26 +191,26 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125453.067255 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125325.173098 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136342.297945 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136395.358733 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136134.925399 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136184.540114 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136134.925399 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136184.540114 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68669502 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68679532 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6098.534813 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6104.304684 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks +system.iocache.writebacks 46668 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses @@ -218,10 +218,10 @@ system.iocache.WriteReq_mshr_misses 46720 # nu system.iocache.demand_mshr_misses 47627 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 47627 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66598982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3940155856 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4006754838 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4006754838 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66482982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3942637876 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4009120858 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4009120858 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,10 +235,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73427.764057 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84335.527740 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73299.869901 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84388.653168 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -255,140 +255,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449021643 # number of cpu cycles simulated +system.cpu.numCycles 449878562 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91138491 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91138491 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1248082 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89857544 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83686998 # Number of BTB hits +system.cpu.BPredUnit.lookups 91189820 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91189820 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1250253 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 90006318 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83822675 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28288670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 450771327 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91138491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83686998 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171087914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6045536 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 191873 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82674920 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 54951 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9822160 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 542562 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4016 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 287044907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.085924 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28390554 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 451032028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91189820 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83822675 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171638033 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6092005 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 127923 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 86885537 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36685 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 38090 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9866979 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 541048 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3553 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 291873782 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.039474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.398963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116472661 40.58% 40.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1490084 0.52% 41.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72800190 25.36% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1427390 0.50% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1806479 0.63% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3992507 1.39% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1571582 0.55% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2063795 0.72% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85420219 29.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 120818032 41.39% 41.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1855546 0.64% 42.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72826244 24.95% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1422491 0.49% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1829890 0.63% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4020066 1.38% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1590838 0.55% 70.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1683069 0.58% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85827606 29.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 287044907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.202971 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.003897 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33370892 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79040686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165533455 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4389968 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4709906 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 881886507 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 578 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4709906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37547254 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52554502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10077381 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165462513 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16693351 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 877383155 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14371 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11668719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2142745 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 879650717 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1723132927 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1723132383 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 544 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843287047 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36363663 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 486686 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 487762 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43318784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19666821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10717044 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1121000 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1013044 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 870450598 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 900193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866206507 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178001 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 30597956 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 44655599 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 144106 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 287044907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.017669 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.373774 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 291873782 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.202699 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.002564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33589176 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83124342 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 166020087 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4383500 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4756677 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 883216023 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4756677 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37852860 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55892656 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9911063 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165583689 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 17876837 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 878703692 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12652 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12602978 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2126989 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 880098416 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1724229495 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1724229039 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843418783 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36679626 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 488930 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 489908 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44000804 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19727758 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10753359 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1338256 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1089668 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870922009 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1727938 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 867227375 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177419 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 30993538 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 45221667 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207753 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 291873782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.971241 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.381572 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82633676 28.79% 28.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22379993 7.80% 36.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14042555 4.89% 41.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9676323 3.37% 44.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79535811 27.71% 72.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5032653 1.75% 74.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72954170 25.42% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 636902 0.22% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152824 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 86148709 29.52% 29.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 24105973 8.26% 37.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 13574297 4.65% 42.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9676822 3.32% 45.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79595279 27.27% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5022101 1.72% 74.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72958833 25.00% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 636421 0.22% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 155347 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 287044907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 291873782 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 195893 8.77% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1841396 82.43% 91.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 196729 8.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202428 8.97% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1851752 82.02% 90.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 203495 9.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 302784 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 830728417 95.90% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 306567 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 831752185 95.91% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.94% # Type of FU issued @@ -417,253 +418,253 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.94% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25630184 2.96% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9545122 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25621043 2.95% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9547580 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866206507 # Type of FU issued -system.cpu.iq.rate 1.929097 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2234018 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002579 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2022023513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 901959019 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855369267 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868137651 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1362479 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 867227375 # Type of FU issued +system.cpu.iq.rate 1.927692 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2257675 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002603 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2028918942 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 903653765 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 856397776 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 869178395 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1343949 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4321864 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17926 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2286443 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4393917 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17180 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11337 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2321478 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7817280 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 160300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817249 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 160526 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4709906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33528904 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6021560 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871350791 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 302780 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19666821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10717077 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 894230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5567968 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 900317 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 526461 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1426778 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864071451 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25139822 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2135055 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4756677 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34884624 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6122535 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 872649947 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 301193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19727758 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10753386 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 894363 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5389997 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11337 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 906001 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524480 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1430481 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 865094857 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25131798 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2132517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34444060 # number of memory reference insts executed -system.cpu.iew.exec_branches 86704764 # Number of branches executed -system.cpu.iew.exec_stores 9304238 # Number of stores executed -system.cpu.iew.exec_rate 1.924343 # Inst execution rate -system.cpu.iew.wb_sent 863434483 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855369319 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671433691 # num instructions producing a value -system.cpu.iew.wb_consumers 1171953644 # num instructions consuming a value +system.cpu.iew.exec_refs 34436194 # number of memory reference insts executed +system.cpu.iew.exec_branches 86723634 # Number of branches executed +system.cpu.iew.exec_stores 9304396 # Number of stores executed +system.cpu.iew.exec_rate 1.922952 # Inst execution rate +system.cpu.iew.wb_sent 864455877 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 856397826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671292665 # num instructions producing a value +system.cpu.iew.wb_consumers 1171999804 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904962 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572918 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903620 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572775 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839904894 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 31338704 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 756085 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1254700 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282350978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.974684 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863709 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 840808469 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 31735206 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1520183 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1254406 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 287133088 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.928288 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.869814 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102836465 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12523164 4.44% 40.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4697520 1.66% 42.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76975529 27.26% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4042949 1.43% 71.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1857352 0.66% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1067382 0.38% 72.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71607681 25.36% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6742936 2.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 107529680 37.45% 37.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13316862 4.64% 42.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3946452 1.37% 43.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76651474 26.70% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4051645 1.41% 71.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1852261 0.65% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1054561 0.37% 72.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71992194 25.07% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6737959 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282350978 # Number of insts commited each cycle -system.cpu.commit.count 839904894 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 287133088 # Number of insts commited each cycle +system.cpu.commit.count 840808469 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23775588 # Number of memory references committed -system.cpu.commit.loads 15344954 # Number of loads committed -system.cpu.commit.membars 3541 # Number of memory barriers committed -system.cpu.commit.branches 85526796 # Number of branches committed +system.cpu.commit.refs 23765746 # Number of memory references committed +system.cpu.commit.loads 15333838 # Number of loads committed +system.cpu.commit.membars 781579 # Number of memory barriers committed +system.cpu.commit.branches 85539454 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768518485 # Number of committed integer instructions. +system.cpu.commit.int_insts 768627958 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6742936 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6737959 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1146769000 # The number of ROB reads -system.cpu.rob.rob_writes 1747209492 # The number of ROB writes -system.cpu.timesIdled 3079387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 161976736 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9841548887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 839904894 # Number of Instructions Simulated -system.cpu.committedInsts_total 839904894 # Number of Instructions Simulated -system.cpu.cpi 0.534610 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534610 # CPI: Total CPI of All Threads -system.cpu.ipc 1.870522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.870522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1407118516 # number of integer regfile reads -system.cpu.int_regfile_writes 857404874 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 282285829 # number of misc regfile reads -system.cpu.misc_regfile_writes 410057 # number of misc regfile writes -system.cpu.icache.replacements 1028866 # number of replacements -system.cpu.icache.tagsinuse 510.467349 # Cycle average of tags in use -system.cpu.icache.total_refs 8724446 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1029378 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.475454 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54553290000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.467349 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8724446 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8724446 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8724446 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1152856114 # The number of ROB reads +system.cpu.rob.rob_writes 1749856645 # The number of ROB writes +system.cpu.timesIdled 3066243 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 158004780 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9872474852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 840808469 # Number of Instructions Simulated +system.cpu.committedInsts_total 840808469 # Number of Instructions Simulated +system.cpu.cpi 0.535055 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.535055 # CPI: Total CPI of All Threads +system.cpu.ipc 1.868968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.868968 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1407444841 # number of integer regfile reads +system.cpu.int_regfile_writes 857665866 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.misc_regfile_reads 282350765 # number of misc regfile reads +system.cpu.misc_regfile_writes 410137 # number of misc regfile writes +system.cpu.icache.replacements 1031767 # number of replacements +system.cpu.icache.tagsinuse 510.488308 # Cycle average of tags in use +system.cpu.icache.total_refs 8766017 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1032279 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.491907 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54591118000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.488308 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997047 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8766017 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8766017 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8766017 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8724446 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8724446 # number of overall hits +system.cpu.icache.demand_hits::total 8766017 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8766017 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8724446 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1097711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1097711 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1097711 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8766017 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1100959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1100959 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1100959 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1097711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1097711 # number of overall misses +system.cpu.icache.demand_misses::total 1100959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1100959 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1097711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16447038991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16447038991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16447038991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9822157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9822157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9822157 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1100959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16475831488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16475831488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16475831488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9866976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9866976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9866976 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9822157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9822157 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9866976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9866976 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9822157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.111759 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.111759 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9866976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111580 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111580 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.111759 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111580 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14983.031956 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14964.981882 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14983.031956 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14964.981882 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14983.031956 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14964.981882 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2545992 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2787490 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 258 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 276 # 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number of overall MSHR misses +system.cpu.icache.writebacks 1565 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 66134 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 66134 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 66134 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1034825 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1034825 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1034825 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12476028992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12476028992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12476028992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12496503490 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12496503490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12496503490 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105061 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104878 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.105061 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.104878 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.105061 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.104878 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12090.065734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12075.958244 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12075.958244 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12075.958244 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # 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number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 9699 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9699 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 15025 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15025 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 9699 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9699 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 15025 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15025 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 189764500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 189764500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 189764500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 41598 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41598 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 9699 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9699 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 124296000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 124296000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 124296000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 36333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 41601 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41601 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 36336 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36336 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 41601 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41601 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.361195 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 36336 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36336 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.266947 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.361169 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.266925 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.361169 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.266925 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12629.916805 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.341788 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12629.916805 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.341788 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12629.916805 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.341788 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -673,83 +674,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2705 # number of writebacks +system.cpu.itb_walker_cache.writebacks 1368 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 15025 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 15025 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 15025 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 9699 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 9699 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 9699 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 144320000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 144320000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 144320000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 94849000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 94849000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 94849000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.361195 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.266947 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.361169 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.266925 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.361169 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.266925 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9605.324459 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9779.255593 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9779.255593 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9779.255593 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 144708 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.855241 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 146935 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 144723 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.015284 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5098934458000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.855241 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.865953 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 147187 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 147187 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 145081 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.868389 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 150553 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 145096 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.037610 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5102657828000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.868389 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.866774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 150554 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 150554 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 147187 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 147187 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 150554 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 150554 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 147187 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 147187 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 145638 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 145638 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 150554 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 150554 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 146024 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 146024 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 145638 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 145638 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 146024 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 146024 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 145638 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 145638 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 2011660500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 2011660500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 2011660500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 292825 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 292825 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 146024 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 146024 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 2047200500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 2047200500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 2047200500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 296578 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 296578 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 292825 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 292825 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 296578 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 296578 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 292825 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 292825 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.497355 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 296578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 296578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492363 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.497355 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492363 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.497355 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492363 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13812.744613 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14019.616638 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13812.744613 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14019.616638 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13812.744613 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14019.616638 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -759,136 +760,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 46772 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 42577 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 145638 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 145638 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 145638 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 146024 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 146024 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 146024 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1570780000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1570780000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1570780000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1605163000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1605163000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1605163000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.497355 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492363 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.497355 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492363 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.497355 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492363 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10785.509276 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10992.460144 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10992.460144 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10992.460144 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1661747 # number of replacements -system.cpu.dcache.tagsinuse 511.998367 # Cycle average of tags in use -system.cpu.dcache.total_refs 17960054 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1662259 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.804606 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1663087 # number of replacements +system.cpu.dcache.tagsinuse 511.997625 # Cycle average of tags in use +system.cpu.dcache.total_refs 17982371 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1663599 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.809318 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998367 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11390626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11390626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6547450 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6547450 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 17938076 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.997625 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 11413167 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11413167 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6547162 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6547162 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 17960329 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 17938076 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 17938076 # number of overall hits +system.cpu.dcache.demand_hits::total 17960329 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 17960329 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 17938076 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2490346 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2490346 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1873884 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1873884 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4364230 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 17960329 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2492340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2492340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1875398 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1875398 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4367738 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4364230 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4364230 # number of overall misses +system.cpu.dcache.demand_misses::total 4367738 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4367738 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4364230 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 37598789500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63471421475 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 101070210975 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 101070210975 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13880972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13880972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8421334 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8421334 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22302306 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4367738 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37542071500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63453033216 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 100995104716 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 100995104716 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13905507 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13905507 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8422560 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8422560 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22328067 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22302306 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22302306 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22328067 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22328067 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22302306 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.179407 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222516 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.195685 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22328067 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.179234 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222664 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.195616 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.195685 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.195616 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15097.817532 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15062.981576 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33871.585154 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33834.435792 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23158.772790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23122.976863 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23158.772790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23122.976863 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1083244649 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6672500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73213 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1083233153 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6672000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73547 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14795.796498 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17065.217391 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14728.447836 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17063.938619 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1547981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1120147 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1577106 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2697253 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2697253 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1370199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 296778 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1666977 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1666977 # number of overall MSHR misses +system.cpu.dcache.writebacks 1548983 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1121085 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1578340 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2699425 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2699425 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1371255 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 297058 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1668313 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1668313 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18186929000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9757421649 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27944350649 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27944350649 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947016500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1386048000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88333064500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098711 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18154950000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9754920653 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27909870653 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27909870653 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85210888500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1394917000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 86605805500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098612 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035241 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074745 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074718 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074745 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074718 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13273.202652 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32877.846906 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13239.660019 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32838.437790 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 85136ebe7..6570dc326 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -23,7 +23,7 @@ Built 1 zonelists. Total pages: 30458 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.004 MHz processor.
+time.c: Detected 2000.000 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812511
+result 7812497
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index df2fb6f73..103b3f085 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index f9ce22b4b..5b6f3a1bd 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 011648483..6fc7a3666 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.070313 # Number of seconds simulated sim_ticks 70312944500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125815 # Simulator instruction rate (inst/s) -host_tick_rate 31799589 # Simulator tick rate (ticks/s) -host_mem_usage 378944 # Number of bytes of host memory used -host_seconds 2211.13 # Real time elapsed on the host +host_inst_rate 109444 # Simulator instruction rate (inst/s) +host_tick_rate 27661822 # Simulator tick rate (ticks/s) +host_mem_usage 378996 # Number of bytes of host memory used +host_seconds 2541.88 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 140625890 # number of cpu cycles simulated diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index f21f47f4d..aaa5a7780 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,14 +62,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 0d61b002c..c929e4789 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:39:34 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index ed3183ec3..0cce68f38 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3107267 # Simulator instruction rate (inst/s) -host_mem_usage 337076 # Number of bytes of host memory used -host_seconds 89.53 # Real time elapsed on the host -host_tick_rate 1887081425 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated sim_ticks 168950072000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1147935 # Simulator instruction rate (inst/s) +host_tick_rate 697156581 # Simulator tick rate (ticks/s) +host_mem_usage 368676 # Number of bytes of host memory used +host_seconds 242.34 # Real time elapsed on the host +sim_insts 278192520 # Number of instructions simulated +system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 337900145 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 337900145 # Number of busy cycles -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written -system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 337900145 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 2184f1531..2ff958baf 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,14 +165,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 1d6e35c6c..07f15598f 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:41:14 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index e994cf670..35887f197 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1776708 # Simulator instruction rate (inst/s) -host_mem_usage 344820 # Number of bytes of host memory used -host_seconds 156.58 # Real time elapsed on the host -host_tick_rate 2363113199 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated sim_ticks 370010840000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 588786 # Simulator instruction rate (inst/s) +host_tick_rate 783116445 # Simulator tick rate (ticks/s) +host_mem_usage 377276 # Number of bytes of host memory used +host_seconds 472.49 # Real time elapsed on the host +sim_insts 278192520 # Number of instructions simulated +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 740021680 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 278192520 # Number of instructions executed +system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls +system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read +system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_store_insts 31439751 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 740021680 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use +system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits +system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits +system.cpu.icache.overall_hits 217695401 # number of overall hits +system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses +system.cpu.icache.demand_misses 808 # number of demand (read+write) misses +system.cpu.icache.overall_misses 808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2062733 # number of replacements +system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use +system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits +system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 120152372 # number of overall hits +system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency -system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses +system.cpu.dcache.writebacks 1437080 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 120152372 # number of overall hits -system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2066829 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1437080 # number of writebacks -system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 808 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 217695401 # number of overall hits -system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 808 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use -system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 49212 # number of replacements +system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1991062 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits +system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76575 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 29460 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1991062 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 76575 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 49212 # number of replacements -system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 29460 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 740021680 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 740021680 # Number of busy cycles -system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 278192520 # Number of instructions executed -system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses -system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read -system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written -system.cpu.num_load_insts 90779388 # Number of load instructions -system.cpu.num_mem_refs 122219139 # number of memory refs -system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 79e59f3f1..bdd61e6fb 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -500,9 +501,9 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index dde98e297..a9de996c2 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:28:02 -gem5 started Nov 22 2011 17:44:50 -gem5 executing on u200540-lin +gem5 compiled Jan 8 2012 22:11:51 +gem5 started Jan 9 2012 02:13:40 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index 5b64b7083..01bc0f829 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.274199 # Number of seconds simulated sim_ticks 274198757500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124379 # Simulator instruction rate (inst/s) -host_tick_rate 59483814 # Simulator tick rate (ticks/s) -host_mem_usage 219308 # Number of bytes of host memory used -host_seconds 4609.64 # Real time elapsed on the host +host_inst_rate 102660 # Simulator instruction rate (inst/s) +host_tick_rate 49096980 # Simulator tick rate (ticks/s) +host_mem_usage 223104 # Number of bytes of host memory used +host_seconds 5584.84 # Real time elapsed on the host sim_insts 573341162 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -456,10 +456,10 @@ system.cpu.l2cache.total_refs 1567440 # To system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7517.825600 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13543.290586 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.229426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.413308 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits @@ -471,11 +471,11 @@ system.cpu.l2cache.UpgradeReq_misses 33 # nu system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 238282 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 4448633000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 8155007500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8155007500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses) @@ -487,11 +487,11 @@ system.cpu.l2cache.UpgradeReq_miss_rate 0.221477 # mi system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34205.519161 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34224.186048 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34224.186048 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,22 +510,22 @@ system.cpu.l2cache.ReadExReq_mshr_misses 108226 # nu system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4037687500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7393309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7393309500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.297223 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.036137 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.036137 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 71df37b56..b2ef015f3 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 7acfed5bd..f37768727 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -82,4 +81,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 494093841000 because target called exit() +Exiting @ tick 493912286000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index 548cdcdb0..556f62c4f 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.494094 # Number of seconds simulated -sim_ticks 494093841000 # Number of ticks simulated +sim_seconds 0.493912 # Number of seconds simulated +sim_ticks 493912286000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111156 # Simulator instruction rate (inst/s) -host_tick_rate 35920075 # Simulator tick rate (ticks/s) -host_mem_usage 281020 # Number of bytes of host memory used -host_seconds 13755.37 # Real time elapsed on the host +host_inst_rate 108889 # Simulator instruction rate (inst/s) +host_tick_rate 35174673 # Simulator tick rate (ticks/s) +host_mem_usage 280548 # Number of bytes of host memory used +host_seconds 14041.70 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 988187683 # number of cpu cycles simulated +system.cpu.numCycles 987824573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits +system.cpu.BPredUnit.lookups 245766486 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245766486 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16576996 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 236474058 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218464201 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed -system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 205503020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1343384866 # Number of instructions fetch has processed +system.cpu.fetch.Branches 245766486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 218464201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436676837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 119986236 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 218554807 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 341323 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 194710374 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4099618 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.599701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317490 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 531629837 55.13% 55.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32377332 3.36% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38827894 4.03% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32536894 3.37% 65.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21844251 2.27% 68.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36448993 3.78% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49128972 5.10% 77.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36937786 3.83% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184520504 19.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248796 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.359943 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 264509435 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 174554141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 373011587 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49033211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 103144089 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2445932072 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 103144089 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 301738657 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40282868 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12225 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 383467875 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135606749 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2393375507 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2559 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25131978 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 92224846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2227188673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5629907069 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5629667957 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 239112 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 799889646 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1309 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1288 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 318947403 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 577879232 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226530900 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 227222440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65937432 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2286709085 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12489 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1922370305 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1306641 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 755226802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1190125426 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11936 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964252463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.993638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.811521 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282911384 29.34% 29.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 160280603 16.62% 45.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162550496 16.86% 62.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148847741 15.44% 78.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109081156 11.31% 89.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60080329 6.23% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30822605 3.20% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8641604 0.90% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1036545 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964252463 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2246339 14.60% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10026447 65.19% 79.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3108042 20.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2420122 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1274712167 66.31% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued @@ -169,85 +169,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 463703127 24.12% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181534884 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued -system.cpu.iq.rate 1.945459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1922370305 # Type of FU issued +system.cpu.iq.rate 1.946064 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15380828 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4825675637 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3042139517 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1874661917 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4905 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 81824 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 136 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1935329448 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1563 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 158391521 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 193777072 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372742 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283642 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77371112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2379 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 103144089 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9045659 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1404502 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286721574 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1118432 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 577879232 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226531297 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6081 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1006586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29974 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283642 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15693422 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2344063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18037485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1889150749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454748002 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33219556 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed -system.cpu.iew.exec_branches 176731992 # Number of branches executed -system.cpu.iew.exec_stores 174531259 # Number of stores executed -system.cpu.iew.exec_rate 1.911862 # Inst execution rate -system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1440755706 # num instructions producing a value -system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value +system.cpu.iew.exec_refs 629271939 # number of memory reference insts executed +system.cpu.iew.exec_branches 176719729 # Number of branches executed +system.cpu.iew.exec_stores 174523937 # Number of stores executed +system.cpu.iew.exec_rate 1.912435 # Inst execution rate +system.cpu.iew.wb_sent 1882531239 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1874662053 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1440606287 # num instructions producing a value +system.cpu.iew.wb_consumers 2134778201 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back +system.cpu.iew.wb_rate 1.897768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674827 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 757743569 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16604349 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 861108374 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.775605 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.288022 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 338327816 39.29% 39.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 210551706 24.45% 63.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 75360819 8.75% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92562974 10.75% 83.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34054041 3.95% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27955182 3.25% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16032820 1.86% 92.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12266632 1.42% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53996384 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 861108374 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 53996384 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3094435758 # The number of ROB reads -system.cpu.rob.rob_writes 4677260376 # The number of ROB writes -system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3093844315 # The number of ROB reads +system.cpu.rob.rob_writes 4676786954 # The number of ROB writes +system.cpu.timesIdled 606516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23572110 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads -system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads -system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes -system.cpu.fp_regfile_reads 109 # number of floating regfile reads -system.cpu.fp_regfile_writes 3 # number of floating regfile writes -system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads -system.cpu.icache.replacements 9996 # number of replacements -system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use -system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks. +system.cpu.cpi 0.646064 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.646064 # CPI: Total CPI of All Threads +system.cpu.ipc 1.547834 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.547834 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3179044858 # number of integer regfile reads +system.cpu.int_regfile_writes 1744829680 # number of integer regfile writes +system.cpu.fp_regfile_reads 145 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.misc_regfile_reads 1039286160 # number of misc regfile reads +system.cpu.icache.replacements 10045 # number of replacements +system.cpu.icache.tagsinuse 976.337758 # Cycle average of tags in use +system.cpu.icache.total_refs 194480398 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11548 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16841.045895 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits -system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits -system.cpu.icache.overall_hits 194495909 # number of overall hits -system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses -system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses -system.cpu.icache.overall_misses 223856 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency +system.cpu.icache.occ_blocks::0 976.337758 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.476727 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 194486608 # number of ReadReq hits +system.cpu.icache.demand_hits 194486608 # number of demand (read+write) hits +system.cpu.icache.overall_hits 194486608 # number of overall hits +system.cpu.icache.ReadReq_misses 223766 # number of ReadReq misses +system.cpu.icache.demand_misses 223766 # number of demand (read+write) misses +system.cpu.icache.overall_misses 223766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1539723000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1539723000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1539723000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 194710374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 194710374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 194710374 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001149 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001149 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001149 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6880.951530 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6880.951530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6880.951530 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,136 +309,136 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 6 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 2071 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2071 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2071 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 221695 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 221695 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 221695 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 824417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 824417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 824417000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3718.699114 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527207 # number of replacements -system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use -system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2527930 # number of replacements +system.cpu.dcache.tagsinuse 4087.566272 # Cycle average of tags in use +system.cpu.dcache.total_refs 440586260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2532026 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 174.005425 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits -system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 439652157 # number of overall hits -system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses -system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4698243 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4087.566272 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997941 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 291836002 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147579227 # number of WriteReq hits +system.cpu.dcache.demand_hits 439415229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 439415229 # number of overall hits +system.cpu.dcache.ReadReq_misses 3119681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1580974 # number of WriteReq misses +system.cpu.dcache.demand_misses 4700655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4700655 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 52079313500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 37355392500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 89434706000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89434706000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 294955683 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency +system.cpu.dcache.demand_accesses 444115884 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 444115884 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010577 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010599 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010584 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16693.794494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23628.087812 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19026.009354 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19026.009354 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229595 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1359154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 607660 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1966814 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1966814 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1760527 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 973314 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2733841 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2733841 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14908482500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17169522000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32078004500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32078004500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005969 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.006156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8468.193047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17640.270252 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574699 # number of replacements -system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1957169 # number of overall hits -system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 585504 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency +system.cpu.l2cache.replacements 574945 # number of replacements +system.cpu.l2cache.tagsinuse 21597.257673 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3194359 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594122 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.376604 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 271429089000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7797.131828 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13800.125845 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.237950 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421146 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1433279 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229601 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1240 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524400 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957679 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957679 # number of overall hits +system.cpu.l2cache.ReadReq_misses 338611 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 208876 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247152 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 585763 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 585763 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11564612500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9756500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8478074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20042687000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20042687000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1771890 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229601 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 210116 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771552 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2543442 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2543442 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191102 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994098 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320331 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230303 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230303 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.091601 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 46.709531 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34303.078672 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34216.375906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34216.375906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411193 # number of writebacks +system.cpu.l2cache.writebacks 411265 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 338611 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 208876 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247152 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 585763 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 585763 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10503665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6475353000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666739500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18170405000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18170405000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994098 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320331 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230303 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230303 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index fdc891c59..da3b012b0 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,14 +62,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 190029619..d3e847fa3 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:30:34 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 3cf669902..c9073b3b2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3416660 # Simulator instruction rate (inst/s) -host_mem_usage 206360 # Number of bytes of host memory used -host_seconds 447.51 # Real time elapsed on the host -host_tick_rate 1978121798 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated sim_ticks 885229360000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1063398 # Simulator instruction rate (inst/s) +host_tick_rate 615669149 # Simulator tick rate (ticks/s) +host_mem_usage 237896 # Number of bytes of host memory used +host_seconds 1437.83 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458721 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1770458721 # Number of busy cycles -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1770458721 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 330cf56d3..e63456bf2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,14 +165,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index b7abf2775..268de88f4 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:27:05 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 9224e99d3..a96327ae0 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2070048 # Simulator instruction rate (inst/s) -host_mem_usage 214112 # Number of bytes of host memory used -host_seconds 738.62 # Real time elapsed on the host -host_tick_rate 2245699490 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated sim_ticks 1658729604000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 746220 # Simulator instruction rate (inst/s) +host_tick_rate 809539282 # Simulator tick rate (ticks/s) +host_mem_usage 246668 # Number of bytes of host memory used +host_seconds 2048.98 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 3317459208 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1528988757 # Number of instructions executed +system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read +system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_store_insts 149160185 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 3317459208 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 1253 # number of replacements +system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits +system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1068344296 # number of overall hits +system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses +system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses +system.cpu.icache.overall_misses 2814 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2514362 # number of replacements +system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits +system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 530743932 # number of overall hits +system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses +system.cpu.dcache.writebacks 2223170 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530743932 # number of overall hits -system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2518458 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2223170 # number of writebacks -system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1068344296 # number of overall hits -system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 2814 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 568906 # number of replacements +system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1941663 # number of overall hits +system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits +system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 579609 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 411709 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1941663 # number of overall hits -system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 579609 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 568906 # number of replacements -system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 411709 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3317459208 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 3317459208 # Number of busy cycles -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1528988757 # Number of instructions executed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses -system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read -system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written -system.cpu.num_load_insts 384102160 # Number of load instructions -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 89aae9c00..862679185 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,12 +62,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index fd345ce8f..bad0385b9 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:22:46 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 3863ba265..9b17b524e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2952357 # Simulator instruction rate (inst/s) -host_mem_usage 202444 # Number of bytes of host memory used -host_seconds 1587.50 # Real time elapsed on the host -host_tick_rate 1792761763 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated sim_ticks 2846007259500 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1508697 # Simulator instruction rate (inst/s) +host_tick_rate 916127309 # Simulator tick rate (ticks/s) +host_mem_usage 234076 # Number of bytes of host memory used +host_seconds 3106.56 # Real time elapsed on the host +sim_insts 4686862651 # Number of instructions simulated +system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014520 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 5692014520 # Number of busy cycles -system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written -system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5692014520 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index c75881c3f..90d473af2 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,12 +165,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 60300fa55..bfa3c0689 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:36:40 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index e9ae83f48..75fcf4f7a 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1878760 # Simulator instruction rate (inst/s) -host_mem_usage 210192 # Number of bytes of host memory used -host_seconds 2494.66 # Real time elapsed on the host -host_tick_rate 2374493636 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated sim_ticks 5923548078000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 871353 # Simulator instruction rate (inst/s) +host_tick_rate 1101269643 # Simulator tick rate (ticks/s) +host_mem_usage 242804 # Number of bytes of host memory used +host_seconds 5378.84 # Real time elapsed on the host +sim_insts 4686862651 # Number of instructions simulated +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 11847096156 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 4686862651 # Number of instructions executed +system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls +system.cpu.num_int_insts 4686862580 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read +system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1677713086 # number of memory refs +system.cpu.num_load_insts 1239184749 # Number of load instructions +system.cpu.num_store_insts 438528337 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 11847096156 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 10 # number of replacements +system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits +system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits +system.cpu.icache.overall_hits 4013232252 # number of overall hits +system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses +system.cpu.icache.demand_misses 675 # number of demand (read+write) misses +system.cpu.icache.overall_misses 675 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9108581 # number of replacements +system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits +system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1668600409 # number of overall hits +system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses +system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9112677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses +system.cpu.dcache.writebacks 3053391 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1668600409 # number of overall hits -system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9112677 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3053391 # number of writebacks -system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_misses 675 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4013232252 # number of overall hits -system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_misses 675 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use -system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 2706631 # number of replacements +system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6396007 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits +system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2717345 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 1174631 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6396007 # number of overall hits -system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2717345 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2706631 # number of replacements -system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1174631 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11847096156 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 11847096156 # Number of busy cycles -system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 4686862651 # Number of instructions executed -system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses -system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read -system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written -system.cpu.num_load_insts 1239184749 # Number of load instructions -system.cpu.num_mem_refs 1677713086 # number of memory refs -system.cpu.num_store_insts 438528337 # Number of store instructions -system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 8802a5811..d20296793 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index ac0a4779d..a8f7791d3 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,11 +3,12 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -tests +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 7b2ddaff9..f73117896 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -3,10 +3,10 @@ sim_seconds 0.096690 # Number of seconds simulated sim_ticks 96689893000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89575 # Simulator instruction rate (inst/s) -host_tick_rate 39125952 # Simulator tick rate (ticks/s) -host_mem_usage 253168 # Number of bytes of host memory used -host_seconds 2471.25 # Real time elapsed on the host +host_inst_rate 71082 # Simulator instruction rate (inst/s) +host_tick_rate 31048201 # Simulator tick rate (ticks/s) +host_mem_usage 253148 # Number of bytes of host memory used +host_seconds 3114.19 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 193379787 # number of cpu cycles simulated diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini index adbeb371c..22a2b62b1 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,12 +62,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 6d11a44d3..d0fe2b96b 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,16 +1,14 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:38:23 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 80e0c67c1..727d7b7f0 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3098099 # Simulator instruction rate (inst/s) -host_mem_usage 209904 # Number of bytes of host memory used -host_seconds 71.45 # Real time elapsed on the host -host_tick_rate 1838915708 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated sim_ticks 131393100000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 733183 # Simulator instruction rate (inst/s) +host_tick_rate 435191133 # Simulator tick rate (ticks/s) +host_mem_usage 241232 # Number of bytes of host memory used +host_seconds 301.92 # Real time elapsed on the host +sim_insts 221363018 # Number of instructions simulated +system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 262786201 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 262786201 # Number of busy cycles -system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written -system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 262786201 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 040454ea4..2acc29c81 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,12 +165,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index ac8ab44c7..a9cb69d9f 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,16 +1,14 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:30:33 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index b2588e568..d8ed7223d 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1944621 # Simulator instruction rate (inst/s) -host_mem_usage 217656 # Number of bytes of host memory used -host_seconds 113.83 # Real time elapsed on the host -host_tick_rate 2204625935 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated sim_ticks 250960631000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 461238 # Simulator instruction rate (inst/s) +host_tick_rate 522908265 # Simulator tick rate (ticks/s) +host_mem_usage 250008 # Number of bytes of host memory used +host_seconds 479.93 # Real time elapsed on the host +sim_insts 221363018 # Number of instructions simulated +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 501921262 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls +system.cpu.num_int_insts 220339607 # number of integer instructions +system.cpu.num_fp_insts 2162459 # number of float instructions +system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read +system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_mem_refs 77165306 # number of memory refs +system.cpu.num_load_insts 56649590 # Number of load instructions +system.cpu.num_store_insts 20515716 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 501921262 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 2836 # number of replacements +system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use +system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits +system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits +system.cpu.icache.overall_hits 173489718 # number of overall hits +system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses +system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 41 # number of replacements +system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use +system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits +system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 77195833 # number of overall hits +system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses +system.cpu.dcache.writebacks 7 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1905 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 7 # number of writebacks -system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 173489718 # number of overall hits -system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_misses 4694 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use -system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1864 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits +system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 4735 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1864 # number of overall hits -system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4735 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 501921262 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 501921262 # Number of busy cycles -system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 221363018 # Number of instructions executed -system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses -system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read -system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written -system.cpu.num_load_insts 56649590 # Number of load instructions -system.cpu.num_mem_refs 77165306 # number of memory refs -system.cpu.num_store_insts 20515716 # Number of store instructions -system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 31dc2c5f8..3c544cad1 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -41,8 +43,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.cpu_ruby_ports.port[1] -icache_port=system.ruby.cpu_ruby_ports.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -63,7 +65,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -87,6 +89,7 @@ number_of_TBEs=256 probeFilter=system.dir_cntrl0.probeFilter probe_filter_enabled=false recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 @@ -122,6 +125,7 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 +is_icache=false latency=1 replacement_policy=PSEUDO_LRU size=1024 @@ -129,9 +133,9 @@ start_index_bit=6 [system.l1_cntrl0] type=L1Cache_Controller -children=L2cacheMemory -L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache -L1IcacheMemory=system.ruby.cpu_ruby_ports.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 cache_response_latency=10 @@ -141,18 +145,53 @@ l2_cache_hit_latency=10 no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.cpu_ruby_ports +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=true +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 start_index_bit=6 +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + [system.physmem] type=PhysicalMemory file= @@ -161,52 +200,18 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.cpu_ruby_ports.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem -children=cpu_ruby_ports network profiler tracer +children=network profiler tracer block_size_bytes=64 clock=1 mem_size=134217728 -network=system.ruby.network no_mem_vec=false -profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports] -type=RubySequencer -children=dcache icache -access_phys_mem=true -dcache=system.ruby.cpu_ruby_ports.dcache -deadlock_threshold=500000 -icache=system.ruby.cpu_ruby_ports.icache -max_outstanding_requests=16 -physmem=system.physmem -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.cpu_ruby_ports.dcache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.ruby.cpu_ruby_ports.icache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 [system.ruby.network] type=SimpleNetwork @@ -216,6 +221,7 @@ buffer_size=0 control_msg_size=8 endpoint_bandwidth=1000 number_of_virtual_networks=10 +ruby_system=system.ruby topology=system.ruby.network.topology [system.ruby.network.topology] @@ -280,8 +286,10 @@ type=RubyProfiler all_instructions=false hot_lines=false num_of_sequencers=1 +ruby_system=system.ruby [system.ruby.tracer] type=RubyTracer +ruby_system=system.ruby warmup_length=100000 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index 026d71a83..c8eb7f5d6 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Apr/28/2011 15:12:18 +Real time: Jan/10/2012 12:41:50 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.46 -Virtual_time_in_minutes: 0.00766667 -Virtual_time_in_hours: 0.000127778 -Virtual_time_in_days: 5.32407e-06 +Virtual_time_in_seconds: 0.28 +Virtual_time_in_minutes: 0.00466667 +Virtual_time_in_hours: 7.77778e-05 +Virtual_time_in_days: 3.24074e-06 Ruby_current_time: 208400 Ruby_start_time: 0 Ruby_cycles: 208400 -mbytes_resident: 39.1133 -mbytes_total: 221.852 -resident_ratio: 0.176357 +mbytes_resident: 39.0547 +mbytes_total: 234.742 +resident_ratio: 0.166439 ruby_cycles_executed: [ 208401 ] @@ -126,8 +126,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11228 -page_faults: 0 +page_reclaims: 10898 +page_faults: 53 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -181,28 +181,28 @@ links_utilized_percent_switch_2: 2.15187 outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.cpu_ruby_ports.icache - system.ruby.cpu_ruby_ports.icache_total_misses: 646 - system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646 - system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 646 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 646 100% -Cache Stats: system.ruby.cpu_ruby_ports.dcache - system.ruby.cpu_ruby_ports.dcache_total_misses: 716 - system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716 - system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 716 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 716 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 73.324% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 26.676% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 73.324% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 26.676% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 716 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 716 100% Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_total_misses: 1362 @@ -289,9 +289,9 @@ O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 O Flush_line [0 ] 0 -M Load [368 ] 368 -M Ifetch [5833 ] 5833 -M Store [66 ] 66 +M Load [306 ] 306 +M Ifetch [5768 ] 5768 +M Store [60 ] 60 M L2_Replacement [923 ] 923 M L1_to_L2 [1061 ] 1061 M Trigger_L2_to_L1D [68 ] 68 @@ -304,9 +304,9 @@ M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 M Flush_line [0 ] 0 -MM Load [397 ] 397 +MM Load [354 ] 354 MM Ifetch [0 ] 0 -MM Store [641 ] 641 +MM Store [614 ] 614 MM L2_Replacement [220 ] 220 MM L1_to_L2 [293 ] 293 MM Trigger_L2_to_L1D [70 ] 70 @@ -319,6 +319,36 @@ MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 MM Flush_line [0 ] 0 +IR Load [0 ] 0 +IR Ifetch [0 ] 0 +IR Store [0 ] 0 +IR L1_to_L2 [0 ] 0 +IR Flush_line [0 ] 0 + +SR Load [0 ] 0 +SR Ifetch [0 ] 0 +SR Store [0 ] 0 +SR L1_to_L2 [0 ] 0 +SR Flush_line [0 ] 0 + +OR Load [0 ] 0 +OR Ifetch [0 ] 0 +OR Store [0 ] 0 +OR L1_to_L2 [0 ] 0 +OR Flush_line [0 ] 0 + +MR Load [62 ] 62 +MR Ifetch [65 ] 65 +MR Store [6 ] 6 +MR L1_to_L2 [0 ] 0 +MR Flush_line [0 ] 0 + +MMR Load [43 ] 43 +MMR Ifetch [0 ] 0 +MMR Store [27 ] 27 +MMR L1_to_L2 [0 ] 0 +MMR Flush_line [0 ] 0 + IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 @@ -468,13 +498,6 @@ IT Store [0 ] 0 IT L2_Replacement [0 ] 0 IT L1_to_L2 [0 ] 0 IT Complete_L2_to_L1 [0 ] 0 -IT Other_GETX [0 ] 0 -IT Other_GETS [0 ] 0 -IT Merged_GETS [0 ] 0 -IT Other_GETS_No_Mig [0 ] 0 -IT NC_DMA_GETS [0 ] 0 -IT Invalidate [0 ] 0 -IT Flush_line [0 ] 0 ST Load [0 ] 0 ST Ifetch [0 ] 0 @@ -482,13 +505,6 @@ ST Store [0 ] 0 ST L2_Replacement [0 ] 0 ST L1_to_L2 [0 ] 0 ST Complete_L2_to_L1 [0 ] 0 -ST Other_GETX [0 ] 0 -ST Other_GETS [0 ] 0 -ST Merged_GETS [0 ] 0 -ST Other_GETS_No_Mig [0 ] 0 -ST NC_DMA_GETS [0 ] 0 -ST Invalidate [0 ] 0 -ST Flush_line [0 ] 0 OT Load [0 ] 0 OT Ifetch [0 ] 0 @@ -496,13 +512,6 @@ OT Store [0 ] 0 OT L2_Replacement [0 ] 0 OT L1_to_L2 [0 ] 0 OT Complete_L2_to_L1 [0 ] 0 -OT Other_GETX [0 ] 0 -OT Other_GETS [0 ] 0 -OT Merged_GETS [0 ] 0 -OT Other_GETS_No_Mig [0 ] 0 -OT NC_DMA_GETS [0 ] 0 -OT Invalidate [0 ] 0 -OT Flush_line [0 ] 0 MT Load [0 ] 0 MT Ifetch [0 ] 0 @@ -510,13 +519,6 @@ MT Store [0 ] 0 MT L2_Replacement [0 ] 0 MT L1_to_L2 [0 ] 0 MT Complete_L2_to_L1 [133 ] 133 -MT Other_GETX [0 ] 0 -MT Other_GETS [0 ] 0 -MT Merged_GETS [0 ] 0 -MT Other_GETS_No_Mig [0 ] 0 -MT NC_DMA_GETS [0 ] 0 -MT Invalidate [0 ] 0 -MT Flush_line [0 ] 0 MMT Load [0 ] 0 MMT Ifetch [0 ] 0 @@ -524,13 +526,6 @@ MMT Store [0 ] 0 MMT L2_Replacement [0 ] 0 MMT L1_to_L2 [0 ] 0 MMT Complete_L2_to_L1 [70 ] 70 -MMT Other_GETX [0 ] 0 -MMT Other_GETS [0 ] 0 -MMT Merged_GETS [0 ] 0 -MMT Other_GETS_No_Mig [0 ] 0 -MMT NC_DMA_GETS [0 ] 0 -MMT Invalidate [0 ] 0 -MMT Flush_line [0 ] 0 MI_F Load [0 ] 0 MI_F Ifetch [0 ] 0 @@ -974,4 +969,5 @@ NO_F_W Pf_Replacement [0 ] 0 NO_F_W DMA_READ [0 ] 0 NO_F_W DMA_WRITE [0 ] 0 NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF
\ No newline at end of file +NO_F_W GETF [0 ] 0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 496de905d..88e64f8c5 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 28 2011 15:11:39 -M5 started Apr 28 2011 15:12:18 -M5 executing on SC2B0617 -command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +gem5 compiled Jan 10 2012 12:41:45 +gem5 started Jan 10 2012 12:41:49 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index d6d7f383d..76c45d699 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 38626 # Simulator instruction rate (inst/s) -host_mem_usage 227180 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 1255686 # Simulator tick rate (ticks/s) -sim_freq 1000000000 # Frequency of simulated ticks -sim_insts 6404 # Number of instructions simulated sim_seconds 0.000208 # Number of seconds simulated sim_ticks 208400 # Number of ticks simulated -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 9071 # Simulator instruction rate (inst/s) +host_tick_rate 295192 # Simulator tick rate (ticks/s) +host_mem_usage 240380 # Number of bytes of host memory used +host_seconds 0.71 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 6432 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.itb.fetch_hits 6415 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls system.cpu.numCycles 208400 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 208400 # Number of busy cycles -system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions system.cpu.num_int_register_reads 8304 # number of times the integer registers were read system.cpu.num_int_register_writes 4581 # number of times the integer registers were written -system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 208400 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 2277de057..c04240cb3 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -41,8 +43,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.cpu_ruby_ports.port[1] -icache_port=system.ruby.cpu_ruby_ports.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -63,7 +65,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -87,6 +89,7 @@ number_of_TBEs=256 probeFilter=system.dir_cntrl0.probeFilter probe_filter_enabled=false recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 @@ -122,6 +125,7 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 +is_icache=false latency=1 replacement_policy=PSEUDO_LRU size=1024 @@ -129,9 +133,9 @@ start_index_bit=6 [system.l1_cntrl0] type=L1Cache_Controller -children=L2cacheMemory -L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache -L1IcacheMemory=system.ruby.cpu_ruby_ports.icache +children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 cache_response_latency=10 @@ -141,18 +145,53 @@ l2_cache_hit_latency=10 no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.cpu_ruby_ports +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=true +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 start_index_bit=6 +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + [system.physmem] type=PhysicalMemory file= @@ -161,52 +200,18 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.cpu_ruby_ports.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem -children=cpu_ruby_ports network profiler tracer +children=network profiler tracer block_size_bytes=64 clock=1 mem_size=134217728 -network=system.ruby.network no_mem_vec=false -profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports] -type=RubySequencer -children=dcache icache -access_phys_mem=true -dcache=system.ruby.cpu_ruby_ports.dcache -deadlock_threshold=500000 -icache=system.ruby.cpu_ruby_ports.icache -max_outstanding_requests=16 -physmem=system.physmem -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.cpu_ruby_ports.dcache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.ruby.cpu_ruby_ports.icache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 [system.ruby.network] type=SimpleNetwork @@ -216,6 +221,7 @@ buffer_size=0 control_msg_size=8 endpoint_bandwidth=1000 number_of_virtual_networks=10 +ruby_system=system.ruby topology=system.ruby.network.topology [system.ruby.network.topology] @@ -280,8 +286,10 @@ type=RubyProfiler all_instructions=false hot_lines=false num_of_sequencers=1 +ruby_system=system.ruby [system.ruby.tracer] type=RubyTracer +ruby_system=system.ruby warmup_length=100000 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 2bf189137..b81839414 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Apr/28/2011 15:12:18 +Real time: Jan/10/2012 12:42:00 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.36 -Virtual_time_in_minutes: 0.006 -Virtual_time_in_hours: 0.0001 -Virtual_time_in_days: 4.16667e-06 +Virtual_time_in_seconds: 0.21 +Virtual_time_in_minutes: 0.0035 +Virtual_time_in_hours: 5.83333e-05 +Virtual_time_in_days: 2.43056e-06 Ruby_current_time: 78448 Ruby_start_time: 0 Ruby_cycles: 78448 -mbytes_resident: 37.8359 -mbytes_total: 220.914 -resident_ratio: 0.171323 +mbytes_resident: 37.832 +mbytes_total: 233.867 +resident_ratio: 0.161817 ruby_cycles_executed: [ 78449 ] @@ -126,7 +126,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10907 +page_reclaims: 10644 page_faults: 0 swaps: 0 block_inputs: 0 @@ -181,28 +181,28 @@ links_utilized_percent_switch_2: 2.15844 outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.cpu_ruby_ports.icache - system.ruby.cpu_ruby_ports.icache_total_misses: 270 - system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270 - system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 270 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100% -Cache Stats: system.ruby.cpu_ruby_ports.dcache - system.ruby.cpu_ruby_ports.dcache_total_misses: 240 - system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240 - system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 240 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 240 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75.8333% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 24.1667% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 240 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 240 100% Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_total_misses: 510 @@ -289,9 +289,9 @@ O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 O Flush_line [0 ] 0 -M Load [131 ] 131 -M Ifetch [2337 ] 2337 -M Store [36 ] 36 +M Load [109 ] 109 +M Ifetch [2315 ] 2315 +M Store [35 ] 35 M L2_Replacement [344 ] 344 M L1_to_L2 [397 ] 397 M Trigger_L2_to_L1D [23 ] 23 @@ -304,9 +304,9 @@ M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 M Flush_line [0 ] 0 -MM Load [138 ] 138 +MM Load [124 ] 124 MM Ifetch [0 ] 0 -MM Store [211 ] 211 +MM Store [201 ] 201 MM L2_Replacement [81 ] 81 MM L1_to_L2 [105 ] 105 MM Trigger_L2_to_L1D [24 ] 24 @@ -319,6 +319,36 @@ MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 MM Flush_line [0 ] 0 +IR Load [0 ] 0 +IR Ifetch [0 ] 0 +IR Store [0 ] 0 +IR L1_to_L2 [0 ] 0 +IR Flush_line [0 ] 0 + +SR Load [0 ] 0 +SR Ifetch [0 ] 0 +SR Store [0 ] 0 +SR L1_to_L2 [0 ] 0 +SR Flush_line [0 ] 0 + +OR Load [0 ] 0 +OR Ifetch [0 ] 0 +OR Store [0 ] 0 +OR L1_to_L2 [0 ] 0 +OR Flush_line [0 ] 0 + +MR Load [22 ] 22 +MR Ifetch [22 ] 22 +MR Store [1 ] 1 +MR L1_to_L2 [0 ] 0 +MR Flush_line [0 ] 0 + +MMR Load [14 ] 14 +MMR Ifetch [0 ] 0 +MMR Store [10 ] 10 +MMR L1_to_L2 [0 ] 0 +MMR Flush_line [0 ] 0 + IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 @@ -468,13 +498,6 @@ IT Store [0 ] 0 IT L2_Replacement [0 ] 0 IT L1_to_L2 [0 ] 0 IT Complete_L2_to_L1 [0 ] 0 -IT Other_GETX [0 ] 0 -IT Other_GETS [0 ] 0 -IT Merged_GETS [0 ] 0 -IT Other_GETS_No_Mig [0 ] 0 -IT NC_DMA_GETS [0 ] 0 -IT Invalidate [0 ] 0 -IT Flush_line [0 ] 0 ST Load [0 ] 0 ST Ifetch [0 ] 0 @@ -482,13 +505,6 @@ ST Store [0 ] 0 ST L2_Replacement [0 ] 0 ST L1_to_L2 [0 ] 0 ST Complete_L2_to_L1 [0 ] 0 -ST Other_GETX [0 ] 0 -ST Other_GETS [0 ] 0 -ST Merged_GETS [0 ] 0 -ST Other_GETS_No_Mig [0 ] 0 -ST NC_DMA_GETS [0 ] 0 -ST Invalidate [0 ] 0 -ST Flush_line [0 ] 0 OT Load [0 ] 0 OT Ifetch [0 ] 0 @@ -496,13 +512,6 @@ OT Store [0 ] 0 OT L2_Replacement [0 ] 0 OT L1_to_L2 [0 ] 0 OT Complete_L2_to_L1 [0 ] 0 -OT Other_GETX [0 ] 0 -OT Other_GETS [0 ] 0 -OT Merged_GETS [0 ] 0 -OT Other_GETS_No_Mig [0 ] 0 -OT NC_DMA_GETS [0 ] 0 -OT Invalidate [0 ] 0 -OT Flush_line [0 ] 0 MT Load [0 ] 0 MT Ifetch [0 ] 0 @@ -510,13 +519,6 @@ MT Store [0 ] 0 MT L2_Replacement [0 ] 0 MT L1_to_L2 [0 ] 0 MT Complete_L2_to_L1 [45 ] 45 -MT Other_GETX [0 ] 0 -MT Other_GETS [0 ] 0 -MT Merged_GETS [0 ] 0 -MT Other_GETS_No_Mig [0 ] 0 -MT NC_DMA_GETS [0 ] 0 -MT Invalidate [0 ] 0 -MT Flush_line [0 ] 0 MMT Load [0 ] 0 MMT Ifetch [0 ] 0 @@ -524,13 +526,6 @@ MMT Store [0 ] 0 MMT L2_Replacement [0 ] 0 MMT L1_to_L2 [0 ] 0 MMT Complete_L2_to_L1 [24 ] 24 -MMT Other_GETX [0 ] 0 -MMT Other_GETS [0 ] 0 -MMT Merged_GETS [0 ] 0 -MMT Other_GETS_No_Mig [0 ] 0 -MMT NC_DMA_GETS [0 ] 0 -MMT Invalidate [0 ] 0 -MMT Flush_line [0 ] 0 MI_F Load [0 ] 0 MI_F Ifetch [0 ] 0 @@ -974,4 +969,5 @@ NO_F_W Pf_Replacement [0 ] 0 NO_F_W DMA_READ [0 ] 0 NO_F_W DMA_WRITE [0 ] 0 NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF
\ No newline at end of file +NO_F_W GETF [0 ] 0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr index 67f69f09d..31ae36f2e 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index f72ee5223..01a9c1b54 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 28 2011 15:11:39 -M5 started Apr 28 2011 15:12:18 -M5 executing on SC2B0617 -command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer +gem5 compiled Jan 10 2012 12:41:45 +gem5 started Jan 10 2012 12:42:00 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index d43409114..3836f9bae 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 38360 # Simulator instruction rate (inst/s) -host_mem_usage 226220 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 1164850 # Simulator tick rate (ticks/s) -sim_freq 1000000000 # Frequency of simulated ticks -sim_insts 2577 # Number of instructions simulated sim_seconds 0.000078 # Number of seconds simulated sim_ticks 78448 # Number of ticks simulated -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 54765 # Simulator instruction rate (inst/s) +host_tick_rate 1666412 # Simulator tick rate (ticks/s) +host_mem_usage 239484 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 2577 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 415 # DTB read hits system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses system.cpu.dtb.write_hits 294 # DTB write hits system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.itb.fetch_hits 2586 # ITB hits system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls system.cpu.numCycles 78448 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 78448 # Number of busy cycles -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions system.cpu.num_int_register_reads 2998 # number of times the integer registers were read system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 78448 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index 43fbd9cf3..9ae1576ae 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 1cc0d7d05..e8531dc26 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:28:31 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 1b6fe9e6f..e3bb4b417 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -3,26 +3,26 @@ sim_seconds 0.000011 # Number of seconds simulated sim_ticks 11087000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51481 # Simulator instruction rate (inst/s) -host_tick_rate 58182623 # Simulator tick rate (ticks/s) -host_mem_usage 209228 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 74834 # Simulator instruction rate (inst/s) +host_tick_rate 84571612 # Simulator tick rate (ticks/s) +host_mem_usage 239776 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 22175 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3057 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3057 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 3056 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3056 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2732 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 2731 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 5895 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14000 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3057 # Number of branches that fetch encountered +system.cpu.fetch.Insts 13997 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3056 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2221 # Number of cycles fetch has spent squashing @@ -48,8 +48,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137858 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.631342 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.137813 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.631206 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3565 # Number of cycles decode is running @@ -66,34 +66,34 @@ system.cpu.rename.RenamedInsts 22712 # Nu system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 272 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21252 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47663 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47647 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 21246 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 47645 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 47629 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11884 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 11878 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 1613 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2239 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1783 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1782 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20542 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16960 # Number of instructions issued +system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20539 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 16958 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12997 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 12992 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.295844 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003369 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.295691 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.003315 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1107 8.46% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1108 8.47% 69.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 1006 7.69% 77.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 734 5.61% 82.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle @@ -138,7 +138,7 @@ system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13642 80.44% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued @@ -167,28 +167,28 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.46% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1844 10.87% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1843 10.87% 91.33% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16960 # Type of FU issued -system.cpu.iq.rate 0.764825 # Inst issue rate +system.cpu.iq.FU_type_0::total 16958 # Type of FU issued +system.cpu.iq.rate 0.764735 # Inst issue rate system.cpu.iq.fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008314 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 47204 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.008315 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 47200 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 30804 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 15755 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17093 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17091 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1183 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 848 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -199,9 +199,9 @@ system.cpu.iew.iewBlockCycles 144 # Nu system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2239 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1783 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 2238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1782 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations @@ -210,7 +210,7 @@ system.cpu.iew.predictedNotTakenIncorrect 523 # N system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 16100 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 858 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3105 # number of memory reference insts executed diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index ee37f754f..b1b2b6764 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -66,7 +67,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index abc865e69..65af79972 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:22:35 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:28:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 26beb56a5..2f19e2e68 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 918185 # Simulator instruction rate (inst/s) -host_mem_usage 200072 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 520394424 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated sim_ticks 5651000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 855797 # Simulator instruction rate (inst/s) +host_tick_rate 492033087 # Simulator tick rate (ticks/s) +host_mem_usage 229652 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 9810 # Number of instructions simulated +system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 11303 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 11303 # Number of busy cycles -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written -system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions -system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 11303 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index f9c7081f4..752669beb 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -41,8 +42,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.cpu_ruby_ports.port[1] -icache_port=system.ruby.cpu_ruby_ports.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=X86TLB @@ -63,7 +64,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -78,11 +79,13 @@ uid=100 type=Directory_Controller children=directory memBuffer buffer_size=0 +cntrl_id=1 directory=system.dir_cntrl0.directory directory_latency=12 memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 +ruby_system=system.ruby transitions_per_cycle=32 version=0 @@ -117,16 +120,43 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller +children=cacheMemory sequencer buffer_size=0 -cacheMemory=system.ruby.cpu_ruby_ports.dcache +cacheMemory=system.l1_cntrl0.cacheMemory cache_response_latency=12 +cntrl_id=0 issue_latency=2 number_of_TBEs=256 recycle_latency=10 -sequencer=system.ruby.cpu_ruby_ports +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 +[system.l1_cntrl0.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + [system.physmem] type=PhysicalMemory file= @@ -135,44 +165,18 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.ruby.cpu_ruby_ports.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem -children=cpu_ruby_ports network profiler tracer +children=network profiler tracer block_size_bytes=64 clock=1 mem_size=134217728 -network=system.ruby.network no_mem_vec=false -profiler=system.ruby.profiler random_seed=1234 randomization=false stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.cpu_ruby_ports] -type=RubySequencer -children=dcache -access_phys_mem=true -dcache=system.ruby.cpu_ruby_ports.dcache -deadlock_threshold=500000 -icache=system.ruby.cpu_ruby_ports.dcache -max_outstanding_requests=16 -physmem=system.physmem -using_network_tester=false -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.cpu_ruby_ports.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 [system.ruby.network] type=SimpleNetwork @@ -180,59 +184,77 @@ children=topology adaptive_routing=false buffer_size=0 control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 +endpoint_bandwidth=1000 number_of_virtual_networks=10 +ruby_system=system.ruby topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -num_int_nodes=3 print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 [system.ruby.network.topology.ext_links0] -type=ExtLink -bw_multiplier=64 +type=SimpleExtLink +bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=0 +int_node=system.ruby.network.topology.routers0 latency=1 +link_id=0 weight=1 [system.ruby.network.topology.ext_links1] -type=ExtLink -bw_multiplier=64 +type=SimpleExtLink +bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=1 +int_node=system.ruby.network.topology.routers1 latency=1 +link_id=1 weight=1 [system.ruby.network.topology.int_links0] -type=IntLink -bw_multiplier=16 +type=SimpleIntLink +bandwidth_factor=16 latency=1 -node_a=0 -node_b=2 +link_id=2 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 weight=1 [system.ruby.network.topology.int_links1] -type=IntLink -bw_multiplier=16 +type=SimpleIntLink +bandwidth_factor=16 latency=1 -node_a=1 -node_b=2 +link_id=3 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + [system.ruby.profiler] type=RubyProfiler all_instructions=false hot_lines=false num_of_sequencers=1 +ruby_system=system.ruby [system.ruby.tracer] type=RubyTracer +ruby_system=system.ruby warmup_length=100000 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index 5b362fa1f..b05082262 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Apr/19/2011 12:26:55 +Real time: Jan/09/2012 14:28:32 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.17 -Virtual_time_in_minutes: 0.00283333 -Virtual_time_in_hours: 4.72222e-05 -Virtual_time_in_days: 1.96759e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 39.5938 -mbytes_total: 212.965 -resident_ratio: 0.185935 +mbytes_resident: 40.0625 +mbytes_total: 241.918 +resident_ratio: 0.165652 ruby_cycles_executed: [ 276485 ] @@ -125,11 +125,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10428 -page_faults: 0 +page_reclaims: 11175 +page_faults: 4 swaps: 0 block_inputs: 0 -block_outputs: 64 +block_outputs: 0 Network Stats ------------- @@ -142,9 +142,9 @@ total_msgs: 16500 total_bytes: 660000 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.155303 - links_utilized_percent_switch_0_link_0: 0.0622369 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.248369 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 2.48658 + links_utilized_percent_switch_0_link_0: 2.48947 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.48369 bw: 16000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1 @@ -153,9 +153,9 @@ links_utilized_percent_switch_0: 0.155303 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.15552 - links_utilized_percent_switch_1_link_0: 0.0620922 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.248947 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 2.48658 + links_utilized_percent_switch_1_link_0: 2.48369 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 2.48947 bw: 16000 base_latency: 1 outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1 @@ -164,27 +164,27 @@ links_utilized_percent_switch_1: 0.15552 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.248658 - links_utilized_percent_switch_2_link_0: 0.248947 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.248369 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 2.48658 + links_utilized_percent_switch_2_link_0: 2.48947 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.48369 bw: 16000 base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.cpu_ruby_ports.dcache - system.ruby.cpu_ruby_ports.dcache_total_misses: 1377 - system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1377 - system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.cacheMemory + system.l1_cntrl0.cacheMemory_total_misses: 1377 + system.l1_cntrl0.cacheMemory_total_demand_misses: 1377 + system.l1_cntrl0.cacheMemory_total_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185% - system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433% + system.l1_cntrl0.cacheMemory_request_type_LD: 36.2382% + system.l1_cntrl0.cacheMemory_request_type_ST: 18.5185% + system.l1_cntrl0.cacheMemory_request_type_IFETCH: 45.2433% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 1377 100% + system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1377 100% --- L1Cache --- - Event Counts - @@ -230,9 +230,9 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_reads: 1377 memory_writes: 1373 memory_refreshes: 576 - memory_total_request_delays: 3664 - memory_delays_per_request: 1.33236 - memory_delays_in_input_queue: 1372 + memory_total_request_delays: 3035 + memory_delays_per_request: 1.10364 + memory_delays_in_input_queue: 743 memory_delays_behind_head_of_bank_queue: 6 memory_delays_stalled_at_head_of_bank_queue: 2286 memory_stalls_for_bank_busy: 791 @@ -310,4 +310,5 @@ ID_W PUTX [0 ] 0 ID_W PUTX_NotOwner [0 ] 0 ID_W DMA_READ [0 ] 0 ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack
\ No newline at end of file +ID_W Memory_Ack [0 ] 0 + diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 91b45434a..52f9aeb2f 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:26:55 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:28:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index fddfe7f1a..58cff044f 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 147176 # Simulator instruction rate (inst/s) -host_mem_usage 218080 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 4140017 # Simulator tick rate (ticks/s) -sim_freq 1000000000 # Frequency of simulated ticks -sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated sim_ticks 276484 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 73084 # Simulator instruction rate (inst/s) +host_tick_rate 2059440 # Simulator tick rate (ticks/s) +host_mem_usage 247728 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +sim_insts 9810 # Number of instructions simulated +system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 276484 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 276484 # Number of busy cycles -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written -system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions -system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 276484 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index 673c6e4e6..acea7ec29 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -169,7 +170,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 894d72125..045ceeef4 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:39:44 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:28:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index b1998f7b5..eb8aa1f61 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 743049 # Simulator instruction rate (inst/s) -host_mem_usage 207784 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2149305775 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated sim_ticks 28768000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 524711 # Simulator instruction rate (inst/s) +host_tick_rate 1537080573 # Simulator tick rate (ticks/s) +host_mem_usage 238628 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 9810 # Number of instructions simulated +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 57536 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 9810 # Number of instructions executed +system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls +system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read +system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1990 # number of memory refs +system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_store_insts 934 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 57536 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use +system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits +system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits +system.cpu.icache.overall_hits 6683 # number of overall hits +system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses +system.cpu.icache.demand_misses 228 # number of demand (read+write) misses +system.cpu.icache.overall_misses 228 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use +system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits +system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1856 # number of overall hits +system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses +system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses -system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses +system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1856 # number of overall hits -system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses -system.cpu.dcache.overall_misses 134 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use -system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses -system.cpu.icache.demand_misses 228 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6683 # number of overall hits -system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses -system.cpu.icache.overall_misses 228 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use -system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 361 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 361 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 57536 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 57536 # Number of busy cycles -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 9810 # Number of instructions executed -system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses -system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 21313 # number of times the integer registers were read -system.cpu.num_int_register_writes 9368 # number of times the integer registers were written -system.cpu.num_load_insts 1056 # Number of load instructions -system.cpu.num_mem_refs 1990 # number of memory refs -system.cpu.num_store_insts 934 # Number of store instructions -system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 1f83b404b..bea7090e9 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -15,9 +15,11 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table @@ -707,6 +709,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -729,6 +732,7 @@ system=system [system.pc.behind_pci] type=IsaFake +fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 @@ -745,15 +749,31 @@ pio=system.iobus.port[12] [system.pc.com_1] type=Uart8250 +children=terminal pio_addr=9223372036854776824 pio_latency=1000 platform=system.pc system=system -terminal=system.pc.terminal +terminal=system.pc.com_1.terminal pio=system.iobus.port[13] +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.pc.fake_com_2] type=IsaFake +fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 @@ -770,6 +790,7 @@ pio=system.iobus.port[14] [system.pc.fake_com_3] type=IsaFake +fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 @@ -786,6 +807,7 @@ pio=system.iobus.port[15] [system.pc.fake_com_4] type=IsaFake +fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 @@ -802,6 +824,7 @@ pio=system.iobus.port[16] [system.pc.fake_floppy] type=IsaFake +fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 @@ -818,6 +841,7 @@ pio=system.iobus.port[17] [system.pc.i_dont_exist] type=IsaFake +fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 @@ -846,7 +870,6 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 -int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -858,7 +881,8 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos -int_pin=system.pc.south_bridge.int_lines2.source +children=int_pin +int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 platform=system.pc @@ -866,6 +890,9 @@ system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[1] +[system.pc.south_bridge.cmos.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.dma1] type=I8237 pio_addr=9223372036854775808 @@ -948,7 +975,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -968,70 +995,58 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines0.sink -source=system.pc.south_bridge.int_lines0.source +source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=0 -[system.pc.south_bridge.int_lines0.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines1] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines1.sink -source=system.pc.south_bridge.int_lines1.source +source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=2 -[system.pc.south_bridge.int_lines1.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines2] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines2.sink -source=system.pc.south_bridge.int_lines2.source +source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 number=0 -[system.pc.south_bridge.int_lines2.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines3] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines3.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=0 -[system.pc.south_bridge.int_lines3.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines4.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin @@ -1040,32 +1055,26 @@ number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines5.sink -source=system.pc.south_bridge.int_lines5.source +source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=1 -[system.pc.south_bridge.int_lines5.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines6] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines6.sink -source=system.pc.south_bridge.int_lines6.source +source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=12 -[system.pc.south_bridge.int_lines6.source] -type=X86IntSourcePin - [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 @@ -1080,20 +1089,28 @@ pio=system.iobus.port[9] [system.pc.south_bridge.keyboard] type=I8042 +children=keyboard_int_pin mouse_int_pin command_port=9223372036854775908 data_port=9223372036854775904 -keyboard_int_pin=system.pc.south_bridge.int_lines5.source -mouse_int_pin=system.pc.south_bridge.int_lines6.source +keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin +mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[4] +[system.pc.south_bridge.keyboard.keyboard_int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.keyboard.mouse_int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.pic1] type=I8259 +children=output mode=I8259Master -output=system.pc.south_bridge.int_lines0.source +output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 platform=system.pc @@ -1101,10 +1118,14 @@ slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[5] +[system.pc.south_bridge.pic1.output] +type=X86IntSourcePin + [system.pc.south_bridge.pic2] type=I8259 +children=output mode=I8259Slave -output=system.pc.south_bridge.int_lines1.source +output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 platform=system.pc @@ -1112,15 +1133,22 @@ slave=Null system=system pio=system.iobus.port[6] +[system.pc.south_bridge.pic2.output] +type=X86IntSourcePin + [system.pc.south_bridge.pit] type=I8254 -int_pin=system.pc.south_bridge.int_lines3.source +children=int_pin +int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[7] +[system.pc.south_bridge.pit.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.speaker] type=PcSpeaker i8254=system.pc.south_bridge.pit @@ -1130,13 +1158,6 @@ platform=system.pc system=system pio=system.iobus.port[8] -[system.pc.terminal] -type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - [system.physmem] type=PhysicalMemory file= diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr index 99f9676e9..fd09f1faf 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -1,17 +1,9 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Reading current count from inactive timer. -For more information see: http://www.m5sim.org/warn/1ea2be46 warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: Don't know what interrupt to clear for console. -For more information see: http://www.m5sim.org/warn/7fe1004f warn: instruction 'fxsave' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: Tried to clear PCI interrupt 14 -For more information see: http://www.m5sim.org/warn/77378d57 warn: Unknown mouse command 0xe1. -For more information see: http://www.m5sim.org/warn/2447512a warn: instruction 'wbinvd' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index b12d01305..bd3613cfe 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,15 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:44:38 -M5 started Apr 19 2011 12:44:44 -M5 executing on maize -command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic +gem5 compiled Jan 9 2012 20:47:38 +gem5 started Jan 9 2012 21:03:15 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic +warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112051446000 because m5_exit instruction encountered +Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index eef6427c6..dc005fb66 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112037 # Number of seconds simulated -sim_ticks 5112036996000 # Number of ticks simulated +sim_seconds 5.112043 # Number of seconds simulated +sim_ticks 5112043255000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2883648 # Simulator instruction rate (inst/s) -host_tick_rate 36256565088 # Simulator tick rate (ticks/s) -host_mem_usage 375496 # Number of bytes of host memory used -host_seconds 141.00 # Real time elapsed on the host -sim_insts 406583262 # Number of instructions simulated -system.l2c.replacements 163860 # number of replacements -system.l2c.tagsinuse 36838.766351 # Cycle average of tags in use -system.l2c.total_refs 3334365 # Total number of references to valid blocks. -system.l2c.sampled_refs 195829 # Sample count of references to valid blocks. -system.l2c.avg_refs 17.026921 # Average number of references to valid blocks. +host_inst_rate 2860366 # Simulator instruction rate (inst/s) +host_tick_rate 35739722021 # Simulator tick rate (ticks/s) +host_mem_usage 375540 # Number of bytes of host memory used +host_seconds 143.04 # Real time elapsed on the host +sim_insts 409133277 # Number of instructions simulated +system.l2c.replacements 164044 # number of replacements +system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use +system.l2c.total_refs 3332458 # Total number of references to valid blocks. +system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. +system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 9696.304444 # Average occupied blocks per context -system.l2c.occ_blocks::1 27142.461907 # Average occupied blocks per context -system.l2c.occ_percent::0 0.147954 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.414161 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2042982 # number of ReadReq hits -system.l2c.ReadReq_hits::1 10263 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2053245 # number of ReadReq hits -system.l2c.Writeback_hits::0 1528802 # number of Writeback hits -system.l2c.Writeback_hits::total 1528802 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 168885 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168885 # number of ReadExReq hits -system.l2c.demand_hits::0 2211867 # number of demand (read+write) hits -system.l2c.demand_hits::1 10263 # number of demand (read+write) hits -system.l2c.demand_hits::total 2222130 # number of demand (read+write) hits -system.l2c.overall_hits::0 2211867 # number of overall hits -system.l2c.overall_hits::1 10263 # number of overall hits -system.l2c.overall_hits::total 2222130 # number of overall hits -system.l2c.ReadReq_misses::0 56047 # number of ReadReq misses -system.l2c.ReadReq_misses::1 29 # number of ReadReq misses -system.l2c.ReadReq_misses::total 56076 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1784 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1784 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 144391 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 144391 # number of ReadExReq misses -system.l2c.demand_misses::0 200438 # number of demand (read+write) misses -system.l2c.demand_misses::1 29 # number of demand (read+write) misses -system.l2c.demand_misses::total 200467 # number of demand (read+write) misses -system.l2c.overall_misses::0 200438 # number of overall misses -system.l2c.overall_misses::1 29 # number of overall misses -system.l2c.overall_misses::total 200467 # number of overall misses +system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context +system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context +system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits +system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits +system.l2c.Writeback_hits::0 1529403 # number of Writeback hits +system.l2c.Writeback_hits::total 1529403 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits +system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits +system.l2c.demand_hits::1 9538 # number of demand (read+write) hits +system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits +system.l2c.overall_hits::0 2211865 # number of overall hits +system.l2c.overall_hits::1 9538 # number of overall hits +system.l2c.overall_hits::total 2221403 # number of overall hits +system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses +system.l2c.ReadReq_misses::1 27 # number of ReadReq misses +system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses +system.l2c.demand_misses::0 200611 # number of demand (read+write) misses +system.l2c.demand_misses::1 27 # number of demand (read+write) misses +system.l2c.demand_misses::total 200638 # number of demand (read+write) misses +system.l2c.overall_misses::0 200611 # number of overall misses +system.l2c.overall_misses::1 27 # number of overall misses +system.l2c.overall_misses::total 200638 # number of overall misses system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2099029 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 10292 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109321 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1528802 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1528802 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1812 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1812 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 313276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313276 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2412305 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 10292 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2422597 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2412305 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 10292 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2422597 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026701 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.029519 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.984547 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.460907 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.083090 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002818 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.085908 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.083090 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002818 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.085908 # miss rate for overall accesses +system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency @@ -88,7 +88,7 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 144360 # number of writebacks +system.l2c.writebacks 144472 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -109,42 +109,42 @@ system.l2c.overall_avg_mshr_uncacheable_latency no_value system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47572 # number of replacements -system.iocache.tagsinuse 0.042404 # Cycle average of tags in use +system.iocache.replacements 47570 # number of replacements +system.iocache.tagsinuse 0.042409 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994772178509 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.042404 # Average occupied blocks per context -system.iocache.occ_percent::1 0.002650 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context +system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.ReadReq_misses::1 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47627 # number of demand (read+write) misses -system.iocache.demand_misses::total 47627 # number of demand (read+write) misses +system.iocache.demand_misses::1 47625 # number of demand (read+write) misses +system.iocache.demand_misses::total 47625 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47627 # number of overall misses -system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.overall_misses::1 47625 # number of overall misses +system.iocache.overall_misses::total 47625 # number of overall misses system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -200,68 +200,68 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224074013 # number of cpu cycles simulated +system.cpu.numCycles 10224086531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 406583262 # Number of instructions executed -system.cpu.num_int_alu_accesses 391790000 # Number of integer alu accesses +system.cpu.num_insts 409133277 # Number of instructions executed +system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 42454615 # number of instructions that are conditional controls -system.cpu.num_int_insts 391790000 # number of integer instructions +system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls +system.cpu.num_int_insts 374297244 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 836247135 # number of times the integer registers were read -system.cpu.num_int_register_writes 419118732 # number of times the integer registers were written +system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read +system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 38123075 # number of memory refs -system.cpu.num_load_insts 29716799 # Number of load instructions -system.cpu.num_store_insts 8406276 # Number of store instructions -system.cpu.num_idle_cycles 9770647500.086761 # Number of idle cycles -system.cpu.num_busy_cycles 453426512.913238 # Number of busy cycles -system.cpu.not_idle_fraction 0.044349 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955651 # Percentage of idle cycles +system.cpu.num_mem_refs 35626519 # number of memory refs +system.cpu.num_load_insts 27217784 # Number of load instructions +system.cpu.num_store_insts 8408735 # Number of store instructions +system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles +system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles +system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955646 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790768 # number of replacements -system.cpu.icache.tagsinuse 510.627880 # Cycle average of tags in use -system.cpu.icache.total_refs 253353258 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791280 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 320.181551 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148756117000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.627880 # Average occupied blocks per context +system.cpu.icache.replacements 790795 # number of replacements +system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use +system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 253353258 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 253353258 # number of ReadReq hits -system.cpu.icache.demand_hits::0 253353258 # number of demand (read+write) hits +system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits +system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 253353258 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 253353258 # number of overall hits +system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 243365777 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 253353258 # number of overall hits -system.cpu.icache.ReadReq_misses::0 791287 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791287 # number of ReadReq misses -system.cpu.icache.demand_misses::0 791287 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 243365777 # number of overall hits +system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses +system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791287 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 791287 # number of overall misses +system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 791314 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 791287 # number of overall misses +system.cpu.icache.overall_misses::total 791314 # number of overall misses system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 254144545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 254144545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 254144545 # number of demand (read+write) accesses +system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 254144545 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 254144545 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 254144545 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.003114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.003114 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.003114 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency @@ -278,7 +278,7 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 806 # number of writebacks +system.cpu.icache.writebacks 809 # number of writebacks system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -299,50 +299,50 @@ system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3656 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.021422 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7713 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3666 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.103928 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5105310674000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 3.021422 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.188839 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 7719 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7719 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3435 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 3.021701 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.188856 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 7947 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 7721 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7721 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 7949 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 7721 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7721 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 4507 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4507 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 7949 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 4278 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 4507 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4507 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 4278 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 4507 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4507 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::1 4278 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 12226 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::1 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 12228 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 12227 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 12228 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.368641 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.349939 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.368580 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.349881 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.368580 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency @@ -358,7 +358,7 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 405 # number of writebacks +system.cpu.itb_walker_cache.writebacks 518 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -379,46 +379,46 @@ system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8177 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.011395 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12378 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8191 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.511171 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101233676500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 5.011395 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.313212 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 12392 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12392 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 7755 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 12392 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12392 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 12392 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12392 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 9345 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9345 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 9345 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9345 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 9345 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9345 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 21737 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21737 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 21737 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21737 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 21737 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21737 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.429912 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.429912 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.429912 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency @@ -434,7 +434,7 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 2332 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -455,52 +455,52 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621118 # number of replacements +system.cpu.dcache.replacements 1621277 # number of replacements system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use -system.cpu.dcache.total_refs 20138941 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621630 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.418949 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 12055886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12055886 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 8080806 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8080806 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 20136692 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20136692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 20136692 # number of overall hits +system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 20139962 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 20136692 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1308365 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308365 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 315530 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315530 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 1623895 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 20139962 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623895 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 1623895 # number of overall misses +system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 1624057 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1623895 # number of overall misses +system.cpu.dcache.overall_misses::total 1624057 # number of overall misses system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13364251 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13364251 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8396336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8396336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 21760587 # number of demand (read+write) accesses +system.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21760587 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 21760587 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21760587 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.097900 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.037579 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.074626 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.074626 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency @@ -517,7 +517,7 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1525259 # number of writebacks +system.cpu.dcache.writebacks 1525559 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index f05a137d3..3130a22aa 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -15,9 +15,11 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing +memories=system.physmem +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table @@ -704,6 +706,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -726,6 +729,7 @@ system=system [system.pc.behind_pci] type=IsaFake +fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 @@ -742,15 +746,31 @@ pio=system.iobus.port[12] [system.pc.com_1] type=Uart8250 +children=terminal pio_addr=9223372036854776824 pio_latency=1000 platform=system.pc system=system -terminal=system.pc.terminal +terminal=system.pc.com_1.terminal pio=system.iobus.port[13] +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.pc.fake_com_2] type=IsaFake +fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 @@ -767,6 +787,7 @@ pio=system.iobus.port[14] [system.pc.fake_com_3] type=IsaFake +fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 @@ -783,6 +804,7 @@ pio=system.iobus.port[15] [system.pc.fake_com_4] type=IsaFake +fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 @@ -799,6 +821,7 @@ pio=system.iobus.port[16] [system.pc.fake_floppy] type=IsaFake +fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 @@ -815,6 +838,7 @@ pio=system.iobus.port[17] [system.pc.i_dont_exist] type=IsaFake +fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 @@ -843,7 +867,6 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 -int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -855,7 +878,8 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos -int_pin=system.pc.south_bridge.int_lines2.source +children=int_pin +int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 platform=system.pc @@ -863,6 +887,9 @@ system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[1] +[system.pc.south_bridge.cmos.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.dma1] type=I8237 pio_addr=9223372036854775808 @@ -945,7 +972,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -965,70 +992,58 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines0.sink -source=system.pc.south_bridge.int_lines0.source +source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=0 -[system.pc.south_bridge.int_lines0.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines1] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines1.sink -source=system.pc.south_bridge.int_lines1.source +source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=2 -[system.pc.south_bridge.int_lines1.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines2] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines2.sink -source=system.pc.south_bridge.int_lines2.source +source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 number=0 -[system.pc.south_bridge.int_lines2.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines3] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines3.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=0 -[system.pc.south_bridge.int_lines3.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines4.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin @@ -1037,32 +1052,26 @@ number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines5.sink -source=system.pc.south_bridge.int_lines5.source +source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=1 -[system.pc.south_bridge.int_lines5.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines6] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines6.sink -source=system.pc.south_bridge.int_lines6.source +source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=12 -[system.pc.south_bridge.int_lines6.source] -type=X86IntSourcePin - [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 @@ -1077,20 +1086,28 @@ pio=system.iobus.port[9] [system.pc.south_bridge.keyboard] type=I8042 +children=keyboard_int_pin mouse_int_pin command_port=9223372036854775908 data_port=9223372036854775904 -keyboard_int_pin=system.pc.south_bridge.int_lines5.source -mouse_int_pin=system.pc.south_bridge.int_lines6.source +keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin +mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[4] +[system.pc.south_bridge.keyboard.keyboard_int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.keyboard.mouse_int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.pic1] type=I8259 +children=output mode=I8259Master -output=system.pc.south_bridge.int_lines0.source +output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 platform=system.pc @@ -1098,10 +1115,14 @@ slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[5] +[system.pc.south_bridge.pic1.output] +type=X86IntSourcePin + [system.pc.south_bridge.pic2] type=I8259 +children=output mode=I8259Slave -output=system.pc.south_bridge.int_lines1.source +output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 platform=system.pc @@ -1109,15 +1130,22 @@ slave=Null system=system pio=system.iobus.port[6] +[system.pc.south_bridge.pic2.output] +type=X86IntSourcePin + [system.pc.south_bridge.pit] type=I8254 -int_pin=system.pc.south_bridge.int_lines3.source +children=int_pin +int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[7] +[system.pc.south_bridge.pit.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.speaker] type=PcSpeaker i8254=system.pc.south_bridge.pit @@ -1127,13 +1155,6 @@ platform=system.pc system=system pio=system.iobus.port[8] -[system.pc.terminal] -type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - [system.physmem] type=PhysicalMemory file= diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr index 99f9676e9..fd09f1faf 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -1,17 +1,9 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Reading current count from inactive timer. -For more information see: http://www.m5sim.org/warn/1ea2be46 warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: Don't know what interrupt to clear for console. -For more information see: http://www.m5sim.org/warn/7fe1004f warn: instruction 'fxsave' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: Tried to clear PCI interrupt 14 -For more information see: http://www.m5sim.org/warn/77378d57 warn: Unknown mouse command 0xe1. -For more information see: http://www.m5sim.org/warn/2447512a warn: instruction 'wbinvd' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index f1baa96ff..ec51a2abf 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,15 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:44:38 -M5 started Apr 19 2011 12:46:29 -M5 executing on maize -command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing +gem5 compiled Jan 9 2012 20:47:38 +gem5 started Jan 9 2012 21:05:49 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing +warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5195470393000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index f2563a156..3c6185134 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -3,11 +3,11 @@ sim_seconds 5.195470 # Number of seconds simulated sim_ticks 5195470393000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1914891 # Simulator instruction rate (inst/s) -host_tick_rate 37635937594 # Simulator tick rate (ticks/s) -host_mem_usage 372104 # Number of bytes of host memory used -host_seconds 138.05 # Real time elapsed on the host -sim_insts 264342001 # Number of instructions simulated +host_inst_rate 1858401 # Simulator instruction rate (inst/s) +host_tick_rate 36414646229 # Simulator tick rate (ticks/s) +host_mem_usage 372180 # Number of bytes of host memory used +host_seconds 142.68 # Real time elapsed on the host +sim_insts 265147881 # Number of instructions simulated system.l2c.replacements 136133 # number of replacements system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use system.l2c.total_refs 3363370 # Total number of references to valid blocks. @@ -257,7 +257,7 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10390940786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 264342001 # Number of instructions executed +system.cpu.num_insts 265147881 # Number of instructions executed system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index bbf4c512c..b9ae49cc3 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -10,6 +10,7 @@ type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing memories=system.physmem system.funcmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,6 +205,7 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 +is_icache=false latency=1 replacement_policy=PSEUDO_LRU size=1024 @@ -241,6 +243,7 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -249,6 +252,7 @@ start_index_bit=6 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -257,6 +261,7 @@ start_index_bit=6 [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -299,6 +304,7 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -307,6 +313,7 @@ start_index_bit=6 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -315,6 +322,7 @@ start_index_bit=6 [system.l1_cntrl1.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -357,6 +365,7 @@ version=2 [system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -365,6 +374,7 @@ start_index_bit=6 [system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -373,6 +383,7 @@ start_index_bit=6 [system.l1_cntrl2.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -415,6 +426,7 @@ version=3 [system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -423,6 +435,7 @@ start_index_bit=6 [system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -431,6 +444,7 @@ start_index_bit=6 [system.l1_cntrl3.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -473,6 +487,7 @@ version=4 [system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -481,6 +496,7 @@ start_index_bit=6 [system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -489,6 +505,7 @@ start_index_bit=6 [system.l1_cntrl4.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -531,6 +548,7 @@ version=5 [system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -539,6 +557,7 @@ start_index_bit=6 [system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -547,6 +566,7 @@ start_index_bit=6 [system.l1_cntrl5.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -589,6 +609,7 @@ version=6 [system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -597,6 +618,7 @@ start_index_bit=6 [system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -605,6 +627,7 @@ start_index_bit=6 [system.l1_cntrl6.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 @@ -647,6 +670,7 @@ version=7 [system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -655,6 +679,7 @@ start_index_bit=6 [system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -663,6 +688,7 @@ start_index_bit=6 [system.l1_cntrl7.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index d120607c7..351f626be 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Dec/01/2011 11:06:07 +Real time: Jan/10/2012 12:44:02 Profiler Stats -------------- -Elapsed_time_in_seconds: 143 -Elapsed_time_in_minutes: 2.38333 -Elapsed_time_in_hours: 0.0397222 -Elapsed_time_in_days: 0.00165509 +Elapsed_time_in_seconds: 112 +Elapsed_time_in_minutes: 1.86667 +Elapsed_time_in_hours: 0.0311111 +Elapsed_time_in_days: 0.0012963 -Virtual_time_in_seconds: 142.63 -Virtual_time_in_minutes: 2.37717 -Virtual_time_in_hours: 0.0396194 -Virtual_time_in_days: 0.00165081 +Virtual_time_in_seconds: 111.5 +Virtual_time_in_minutes: 1.85833 +Virtual_time_in_hours: 0.0309722 +Virtual_time_in_days: 0.00129051 -Ruby_current_time: 19175808 +Ruby_current_time: 19129228 Ruby_start_time: 0 -Ruby_cycles: 19175808 +Ruby_cycles: 19129228 -mbytes_resident: 39.8008 -mbytes_total: 372.789 -resident_ratio: 0.106765 +mbytes_resident: 37.8594 +mbytes_total: 362.402 +resident_ratio: 0.104489 -ruby_cycles_executed: [ 19175809 19175809 19175809 19175809 19175809 19175809 19175809 19175809 ] +ruby_cycles_executed: [ 19129229 19129229 19129229 19129229 19129229 19129229 19129229 19129229 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,35 +66,35 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 616306 average: 15.9984 | standard deviation: 0.126863 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 616186 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 614830 average: 15.9984 | standard deviation: 0.127016 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 614710 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 19260 count: 616178 average: 3982.78 | standard deviation: 3082.99 | 1923 6985 12940 16852 16221 19485 21968 22951 19997 17263 18715 17525 14827 13389 11916 11467 9741 9146 8989 7432 7315 6919 7000 6576 5812 6092 6224 5757 5791 5458 5654 5406 5563 5824 5241 5556 5626 5960 5764 5346 5797 6190 5864 5845 5833 6364 5999 6055 6418 5956 6228 6258 6699 6227 5888 6447 6542 6194 5887 5714 5840 5660 5392 5444 4800 4719 4729 4711 4183 3673 3732 3729 3275 3025 2719 2757 2359 2299 2195 1846 1727 1590 1597 1397 1161 1163 1044 963 855 750 706 567 535 493 433 386 341 284 244 200 229 184 159 127 122 109 89 83 92 58 46 46 46 37 29 28 14 29 18 8 12 12 11 6 4 6 3 4 8 1 1 0 0 0 1 1 0 1 3 2 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 128 max: 19260 count: 400216 average: 3981.88 | standard deviation: 3082.28 | 1243 4477 8345 10896 10482 12822 14257 14991 13035 11171 12161 11312 9600 8686 7757 7430 6366 5969 5893 4842 4737 4498 4545 4304 3761 3939 4124 3752 3763 3597 3656 3521 3666 3822 3405 3568 3665 3830 3670 3513 3661 4055 3779 3750 3811 4107 3922 3889 4147 3877 4071 4022 4373 4030 3884 4203 4265 3973 3782 3724 3840 3696 3553 3494 3146 3017 3099 3015 2765 2385 2427 2442 2122 1932 1749 1789 1529 1490 1440 1187 1097 1038 1021 913 749 724 658 630 567 506 453 350 341 332 291 261 218 200 161 136 148 125 105 83 89 58 47 45 58 41 29 30 32 26 20 23 8 17 11 5 9 4 10 4 4 4 2 3 7 0 0 0 0 0 1 1 0 0 3 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 128 max: 18260 count: 215962 average: 3984.45 | standard deviation: 3084.31 | 680 2508 4595 5956 5739 6663 7711 7960 6962 6092 6554 6213 5227 4703 4159 4037 3375 3177 3096 2590 2578 2421 2455 2272 2051 2153 2100 2005 2028 1861 1998 1885 1897 2002 1836 1988 1961 2130 2094 1833 2136 2135 2085 2095 2022 2257 2077 2166 2271 2079 2157 2236 2326 2197 2004 2244 2277 2221 2105 1990 2000 1964 1839 1950 1654 1702 1630 1696 1418 1288 1305 1287 1153 1093 970 968 830 809 755 659 630 552 576 484 412 439 386 333 288 244 253 217 194 161 142 125 123 84 83 64 81 59 54 44 33 51 42 38 34 17 17 16 14 11 9 5 6 12 7 3 3 8 1 2 0 2 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 123 average: 2 | standard deviation: 0 | 0 0 123 ] -miss_latency_L2Cache: [binsize: 32 max: 4602 count: 587 average: 524.404 | standard deviation: 575.604 | 117 31 17 15 14 16 18 14 12 6 14 15 13 13 16 19 19 9 7 10 14 11 8 11 6 5 11 7 6 9 7 9 7 8 5 1 6 4 2 6 4 1 4 1 3 1 2 3 1 0 2 1 1 4 1 2 2 0 1 3 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 2 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Directory: [binsize: 128 max: 19260 count: 595460 average: 4004.24 | standard deviation: 3081.89 | 0 6188 12231 15961 15370 18780 21406 22348 19464 16843 18315 17167 14540 13140 11663 11195 9529 8941 8787 7206 7141 6741 6782 6375 5648 5897 6020 5592 5593 5286 5471 5226 5388 5643 5029 5377 5455 5741 5566 5141 5594 5959 5667 5695 5617 6159 5794 5853 6201 5728 6013 6050 6489 6025 5708 6264 6348 6005 5735 5541 5672 5497 5233 5308 4685 4600 4609 4592 4067 3569 3646 3647 3187 2942 2666 2707 2298 2240 2144 1802 1693 1562 1567 1371 1128 1143 1021 937 843 732 688 556 521 486 423 379 336 281 240 195 225 180 156 127 120 108 89 82 92 56 46 46 46 37 29 28 14 29 18 7 12 12 11 6 4 6 3 4 8 1 1 0 0 0 1 1 0 1 3 2 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache_wCC: [binsize: 128 max: 15323 count: 20008 average: 3470.19 | standard deviation: 3051.05 | 1620 735 662 830 806 661 533 572 512 402 390 349 283 241 247 271 211 204 202 225 173 176 216 201 164 195 204 165 198 170 183 180 175 181 212 178 171 219 198 205 203 231 197 150 216 205 205 202 217 228 215 208 210 202 180 183 194 189 152 173 168 163 159 136 115 119 120 119 116 104 86 82 88 83 53 50 61 59 51 44 34 28 30 26 33 20 23 26 12 18 18 11 14 7 10 7 5 3 4 5 4 4 3 0 2 1 0 1 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 14531 count: 19973 average: 3286.02 | standard deviation: 3034.97 | 2366 851 763 1000 739 600 526 499 414 279 302 284 223 190 201 205 196 202 204 188 168 184 204 174 176 191 200 175 170 184 179 180 197 203 153 181 200 211 221 172 223 211 206 174 215 238 200 205 218 193 205 203 241 178 171 171 195 185 156 151 169 144 142 120 117 103 131 116 94 82 64 82 79 67 55 42 58 58 38 31 26 26 26 27 24 20 21 20 8 18 13 7 6 6 9 3 7 1 4 3 2 1 2 2 2 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3577 count: 19973 average: 156.924 | standard deviation: 329.403 | 14267 324 247 266 249 212 209 211 267 213 183 195 183 269 202 178 182 149 178 113 114 89 79 82 79 88 86 74 84 68 68 55 59 68 33 45 35 33 33 35 22 37 23 32 20 18 18 18 18 11 10 10 15 6 11 7 6 8 10 4 5 5 5 4 1 3 5 1 2 0 1 2 4 4 2 1 3 0 2 1 0 2 1 1 2 0 1 0 1 0 0 0 1 0 0 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 36 count: 19973 average: 24.6278 | standard deviation: 1.16146 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14532 174 4629 66 198 202 135 17 12 3 1 3 1 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 13 count: 19973 average: 1.76343 | standard deviation: 1.58863 | 4611 5093 5259 3035 593 545 679 44 47 30 30 5 1 1 ] -imcomplete_wCC_Times: 35 -miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18671 count: 595460 average: 3283.61 | standard deviation: 3047.8 | 72165 24468 23589 28218 21559 18206 15911 15616 11515 8792 8964 8619 7132 6518 6106 6539 5828 5706 6059 5367 5389 5550 5744 5387 4929 5462 5563 5288 5190 4936 5610 5463 5285 5809 5185 5540 5654 6042 5818 5319 5923 6246 6141 5833 5842 6348 6011 6246 6403 5853 6123 6090 6408 5927 5445 5501 5710 5194 5091 4769 4841 4310 4148 4233 3521 3452 3346 3188 2807 2518 2419 2428 1989 1819 1664 1663 1394 1388 1305 1040 966 869 864 761 579 595 534 442 377 349 314 253 244 205 172 157 171 149 124 82 90 83 63 63 40 46 42 34 24 18 20 22 11 12 11 4 10 4 12 4 3 1 2 2 1 3 1 0 1 0 0 2 1 0 2 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_dir_initial_forward_request: [binsize: 32 max: 3303 count: 595460 average: 11.5399 | standard deviation: 54.8109 | 592211 155 150 128 123 141 148 120 118 67 88 105 59 56 83 79 110 112 109 98 98 110 60 65 61 45 46 39 36 40 34 44 47 40 33 32 31 20 18 26 25 20 8 13 15 15 15 15 14 13 6 16 11 7 4 1 6 4 2 2 8 1 3 4 6 5 7 5 2 0 1 3 2 3 0 1 1 0 0 1 3 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 38 count: 595460 average: 24.832 | standard deviation: 1.28038 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 382093 4983 183588 1587 7757 8248 5728 645 407 262 65 54 37 5 1 ] -miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4197 count: 595460 average: 684.261 | standard deviation: 462.33 | 0 0 0 14346 19482 17049 19024 22354 25699 21621 20682 20151 22254 24251 19256 18086 16597 16944 17480 13958 13719 13444 14504 15774 13254 12999 13088 13958 14531 10737 9327 7956 7818 7732 5995 5675 5481 5614 5737 4631 4569 4356 4641 4726 3602 3150 2765 2788 2741 2051 1964 1878 1781 1973 1553 1525 1390 1518 1506 1178 988 906 832 865 699 620 608 591 570 472 424 413 434 450 331 286 250 260 248 195 191 175 163 156 115 125 105 117 114 116 70 61 61 59 45 55 44 50 35 31 37 26 24 29 20 21 23 12 13 8 9 6 7 5 3 3 3 1 2 2 1 4 3 0 2 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 18400 count: 614702 average: 3982.61 | standard deviation: 2992.13 | 1914 7044 12490 16512 15889 18736 21128 22310 19250 16973 18228 17272 14440 12720 11919 11264 9796 9053 8574 7249 7243 6931 6893 6397 5679 6057 6153 5744 5637 5473 5792 5538 5524 5879 5303 5590 5887 6113 6011 5470 6192 6473 6248 6357 6359 6725 6660 6739 7291 6595 6853 7000 7480 7136 6581 7014 7149 6614 6533 6018 6336 6070 5893 5695 4978 4966 4720 4574 4042 3444 3609 3407 3036 2737 2400 2393 2037 1944 1791 1453 1461 1289 1239 1059 857 864 803 682 596 520 465 370 374 339 249 229 191 202 184 132 137 127 101 94 70 60 65 39 36 36 32 20 22 32 9 8 11 11 9 6 12 5 5 3 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 18400 count: 399338 average: 3984.32 | standard deviation: 2993.07 | 1293 4556 8079 10724 10277 12230 13719 14584 12466 11028 11779 11190 9428 8274 7711 7272 6322 5923 5519 4696 4662 4567 4416 4173 3768 3938 3924 3726 3668 3559 3700 3595 3595 3843 3447 3665 3876 3934 3968 3574 4048 4230 3998 4144 4226 4388 4372 4351 4686 4318 4387 4504 4824 4620 4208 4525 4646 4303 4241 3942 4160 3962 3811 3657 3286 3189 3052 3011 2667 2246 2369 2174 1966 1804 1563 1542 1288 1284 1181 970 934 826 851 676 572 564 527 421 387 353 302 249 249 226 159 151 122 120 123 77 95 90 59 60 45 45 47 23 25 19 19 12 10 23 5 4 6 7 6 4 8 4 3 3 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 18030 count: 215364 average: 3979.43 | standard deviation: 2990.39 | 621 2488 4411 5788 5612 6506 7409 7726 6784 5945 6449 6082 5012 4446 4208 3992 3474 3130 3055 2553 2581 2364 2477 2224 1911 2119 2229 2018 1969 1914 2092 1943 1929 2036 1856 1925 2011 2179 2043 1896 2144 2243 2250 2213 2133 2337 2288 2388 2605 2277 2466 2496 2656 2516 2373 2489 2503 2311 2292 2076 2176 2108 2082 2038 1692 1777 1668 1563 1375 1198 1240 1233 1070 933 837 851 749 660 610 483 527 463 388 383 285 300 276 261 209 167 163 121 125 113 90 78 69 82 61 55 42 37 42 34 25 15 18 16 11 17 13 8 12 9 4 4 5 4 3 2 4 1 2 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 133 average: 2 | standard deviation: 0 | 0 0 133 ] +miss_latency_L2Cache: [binsize: 64 max: 6752 count: 563 average: 510.815 | standard deviation: 605.328 | 140 23 36 31 29 33 25 30 22 38 18 13 12 14 11 19 4 8 4 7 4 5 2 1 4 1 1 3 3 5 3 3 1 2 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 128 max: 18400 count: 594120 average: 4003.79 | standard deviation: 2989.88 | 0 6288 11765 15680 15030 18066 20545 21710 18726 16571 17865 16936 14178 12478 11639 11012 9579 8867 8371 7049 7048 6737 6685 6232 5493 5911 5956 5559 5443 5302 5572 5383 5365 5701 5105 5394 5665 5945 5794 5261 5978 6245 6035 6145 6135 6512 6439 6522 7046 6336 6613 6777 7274 6916 6374 6811 6947 6451 6334 5838 6133 5925 5724 5551 4850 4840 4613 4467 3950 3351 3519 3329 2973 2680 2343 2347 1990 1902 1763 1420 1427 1265 1215 1038 838 843 785 667 584 514 457 362 366 333 242 225 186 201 180 130 135 124 98 94 67 59 64 38 36 35 30 19 22 32 9 8 10 11 9 5 12 5 4 2 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 128 max: 15824 count: 19886 average: 3474.77 | standard deviation: 2989.85 | 1618 689 663 777 799 639 557 570 512 391 354 333 257 238 272 246 214 184 202 199 195 194 208 165 185 146 196 185 194 171 220 155 158 178 198 196 222 168 217 209 214 228 213 212 224 213 221 217 245 259 240 223 205 220 207 203 202 163 199 180 203 145 169 144 128 126 107 107 92 93 90 78 63 57 57 46 47 42 28 33 34 24 24 21 19 21 18 15 12 6 8 8 8 6 7 4 5 1 4 2 2 3 3 0 3 1 1 1 0 1 2 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15681 count: 19858 average: 3294.08 | standard deviation: 2973.13 | 2401 789 781 887 699 566 528 485 416 305 282 260 243 202 195 228 167 178 197 169 200 185 206 145 164 171 203 192 183 160 192 163 182 213 176 211 215 209 201 181 236 224 213 244 216 220 207 217 246 221 241 234 220 216 202 188 200 186 188 162 184 140 147 144 111 92 98 97 81 79 88 73 44 46 45 38 39 33 31 22 36 23 16 13 15 14 11 12 12 5 5 9 6 3 5 4 3 2 2 2 0 2 2 2 2 2 1 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3227 count: 19858 average: 155.74 | standard deviation: 323.185 | 14126 352 258 301 235 217 214 193 257 201 194 199 172 274 199 186 177 173 167 106 89 89 79 113 83 76 64 91 100 74 65 66 55 64 37 43 33 25 31 28 30 28 23 17 21 21 21 14 11 15 16 13 2 16 10 6 9 9 14 9 7 5 4 1 3 2 2 0 0 2 1 0 3 2 5 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 39 count: 19858 average: 24.6141 | standard deviation: 1.15269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14566 121 4592 47 162 198 137 14 11 6 0 2 1 0 0 1 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 15 count: 19858 average: 1.76186 | standard deviation: 1.57127 | 4563 5054 5189 3095 640 542 633 35 49 30 20 5 1 1 0 1 ] +imcomplete_wCC_Times: 28 +miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18051 count: 594120 average: 3281.74 | standard deviation: 2955.22 | 70915 24061 22485 26839 20864 17583 15751 15347 11377 8651 8866 8376 7098 6392 6188 6335 5844 5688 5995 5148 5493 5406 5729 5236 4904 5474 5677 5276 5294 5230 5687 5306 5544 5949 5507 5825 5899 6456 6280 5788 6493 6783 6606 6801 6509 7149 6995 6970 7338 6522 6865 6751 6975 6391 5739 6040 6136 5568 5202 4825 4915 4299 4091 3958 3278 3193 2978 2814 2503 2209 2089 1919 1708 1485 1349 1302 1116 983 929 762 676 640 625 473 398 444 343 272 272 225 183 158 130 128 119 92 112 80 74 64 52 40 17 28 22 12 18 12 19 14 9 9 10 4 6 3 4 9 3 1 2 2 2 4 0 3 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_initial_forward_request: [binsize: 16 max: 3183 count: 594120 average: 11.5723 | standard deviation: 55.3785 | 590603 289 44 73 70 75 38 102 87 47 78 59 67 83 44 68 38 61 59 29 47 29 45 48 25 45 29 41 35 27 55 30 62 61 46 66 36 65 72 30 61 32 65 51 30 43 18 39 41 14 23 22 26 39 12 19 11 22 24 16 32 13 22 30 11 19 10 26 25 12 24 10 17 19 7 15 9 17 14 5 11 8 12 10 5 13 2 4 9 3 7 3 4 7 7 9 0 6 9 5 3 3 5 7 4 7 3 3 4 2 3 0 1 3 3 3 2 2 6 7 2 1 1 3 0 0 3 2 2 3 2 0 0 1 0 1 2 1 4 0 1 2 2 2 1 2 2 2 1 0 0 1 0 1 1 4 1 1 0 0 1 0 1 2 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 44 count: 594120 average: 24.8307 | standard deviation: 1.27614 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 381219 4947 183412 1522 7686 8318 5658 619 334 251 69 48 31 2 1 0 2 0 0 0 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4704 count: 594120 average: 685.644 | standard deviation: 462.597 | 0 0 0 14505 19454 17157 18632 21836 25332 21411 20516 20005 22296 24193 19296 17974 16634 16790 17488 13769 13634 13397 14499 15945 13165 13170 12959 14154 14461 10808 9503 8069 7842 7793 6041 5729 5422 5551 5820 4543 4542 4418 4789 4771 3559 3168 2848 2806 2691 2046 1922 1832 1861 1938 1548 1493 1390 1485 1485 1031 1022 860 944 857 675 579 560 607 596 451 494 416 404 478 307 324 254 259 253 203 193 173 174 163 112 124 127 108 111 94 80 75 54 61 54 42 41 40 45 38 24 28 24 18 16 12 10 20 7 7 4 5 8 7 6 7 4 8 8 4 3 1 2 2 4 2 2 0 1 1 0 1 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 74 average: 2 | standard deviation: 0 | 0 0 74 ] -miss_latency_LD_L2Cache: [binsize: 32 max: 4602 count: 386 average: 529.723 | standard deviation: 594.125 | 77 21 13 9 10 11 8 10 7 5 10 8 11 9 9 13 14 4 3 7 10 8 6 6 3 3 11 3 2 8 3 6 5 4 3 1 4 1 2 4 3 1 2 0 3 1 1 3 1 0 0 1 0 2 0 1 2 0 1 3 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_Directory: [binsize: 128 max: 19260 count: 386757 average: 4003.38 | standard deviation: 3081.43 | 0 3978 7889 10309 9945 12364 13879 14603 12682 10905 11892 11078 9410 8521 7581 7247 6229 5838 5769 4689 4633 4381 4401 4173 3648 3811 3989 3639 3626 3482 3548 3399 3559 3703 3281 3456 3557 3676 3544 3384 3529 3903 3647 3649 3677 3970 3780 3758 4010 3721 3937 3888 4239 3904 3761 4085 4136 3861 3680 3616 3728 3587 3441 3401 3072 2952 3024 2940 2693 2324 2370 2380 2063 1874 1721 1755 1485 1446 1403 1161 1078 1018 1004 896 730 711 645 613 559 494 443 343 332 331 286 258 214 197 158 132 147 122 102 83 87 58 47 45 58 40 29 30 32 26 20 23 8 17 11 4 9 4 10 4 4 4 2 3 7 0 0 0 0 0 1 1 0 0 3 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15323 count: 12999 average: 3467.41 | standard deviation: 3042.84 | 1049 460 426 545 509 428 358 369 340 255 263 226 188 162 170 182 137 130 124 152 104 115 142 131 113 128 135 113 137 114 108 122 107 119 124 111 108 154 126 129 132 152 132 101 134 137 142 131 137 156 134 134 134 126 123 118 129 112 102 108 112 109 112 93 74 65 75 75 72 61 57 62 59 58 28 34 44 44 37 26 19 20 17 17 19 13 13 17 8 12 10 7 9 1 5 3 4 3 3 4 1 3 3 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 49 average: 2 | standard deviation: 0 | 0 0 49 ] -miss_latency_ST_L2Cache: [binsize: 32 max: 3792 count: 201 average: 514.189 | standard deviation: 539.55 | 40 10 4 6 4 5 10 4 5 1 4 7 2 4 7 6 5 5 4 3 4 3 2 5 3 2 0 4 4 1 4 3 2 4 2 0 2 3 0 2 1 0 2 1 0 0 1 0 0 0 2 0 1 2 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ] -miss_latency_ST_Directory: [binsize: 128 max: 18260 count: 208703 average: 4005.83 | standard deviation: 3082.75 | 0 2210 4342 5652 5425 6416 7527 7745 6782 5938 6423 6089 5130 4619 4082 3948 3300 3103 3018 2517 2508 2360 2381 2202 2000 2086 2031 1953 1967 1804 1923 1827 1829 1940 1748 1921 1898 2065 2022 1757 2065 2056 2020 2046 1940 2189 2014 2095 2191 2007 2076 2162 2250 2121 1947 2179 2212 2144 2055 1925 1944 1910 1792 1907 1613 1648 1585 1652 1374 1245 1276 1267 1124 1068 945 952 813 794 741 641 615 544 563 475 398 432 376 324 284 238 245 213 189 155 137 121 122 84 82 63 78 58 54 44 33 50 42 37 34 16 17 16 14 11 9 5 6 12 7 3 3 8 1 2 0 2 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 13978 count: 7009 average: 3475.33 | standard deviation: 3066.41 | 571 275 236 285 297 233 175 203 172 147 127 123 95 79 77 89 74 74 78 73 69 61 74 70 51 67 69 52 61 56 75 58 68 62 88 67 63 65 72 76 71 79 65 49 82 68 63 71 80 72 81 74 76 76 57 65 65 77 50 65 56 54 47 43 41 54 45 44 44 43 29 20 29 25 25 16 17 15 14 18 15 8 13 9 14 7 10 9 4 6 8 4 5 6 5 4 1 0 1 1 3 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 95 average: 2 | standard deviation: 0 | 0 0 95 ] +miss_latency_LD_L2Cache: [binsize: 32 max: 3352 count: 371 average: 490.28 | standard deviation: 558.933 | 88 17 6 9 14 11 12 9 9 11 6 12 6 5 10 6 6 6 14 13 3 6 4 6 3 6 2 5 5 5 0 12 2 0 2 2 1 1 2 1 1 2 0 3 0 1 0 1 2 1 0 1 1 0 0 3 1 0 2 1 0 2 0 2 0 1 0 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 128 max: 18400 count: 385874 average: 4005.47 | standard deviation: 2990.64 | 0 4056 7628 10185 9716 11799 13351 14190 12136 10766 11544 10977 9253 8118 7530 7094 6181 5799 5395 4567 4540 4430 4274 4067 3645 3840 3797 3603 3549 3439 3549 3492 3491 3721 3315 3545 3726 3827 3835 3445 3896 4083 3868 4004 4068 4243 4229 4205 4528 4161 4239 4357 4684 4481 4075 4394 4519 4193 4111 3819 4025 3866 3715 3561 3202 3100 2988 2933 2604 2182 2315 2128 1924 1763 1524 1510 1254 1256 1160 945 909 810 833 661 560 551 515 411 382 349 295 244 243 220 154 148 120 119 119 76 95 88 57 60 44 44 46 23 25 18 19 12 10 23 5 4 6 7 6 3 8 4 3 2 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15824 count: 12998 average: 3485.28 | standard deviation: 2996.01 | 1078 454 413 512 522 412 352 372 324 257 229 211 171 152 177 174 138 122 123 128 122 137 142 106 122 98 126 123 119 120 151 103 104 122 132 120 150 107 133 129 152 147 130 140 158 145 143 146 158 157 148 147 140 139 133 131 127 110 130 123 135 96 96 96 84 89 64 78 63 64 54 46 42 41 39 32 34 28 21 25 25 16 18 15 12 13 12 10 5 4 7 5 6 6 5 3 2 1 4 1 0 2 2 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 38 average: 2 | standard deviation: 0 | 0 0 38 ] +miss_latency_ST_L2Cache: [binsize: 64 max: 6752 count: 192 average: 550.495 | standard deviation: 685.986 | 35 8 11 10 9 15 14 14 10 11 9 3 3 7 1 7 2 4 2 4 1 2 1 0 1 0 0 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 128 max: 18030 count: 208246 average: 4000.67 | standard deviation: 2988.48 | 0 2232 4137 5495 5314 6267 7194 7520 6590 5805 6321 5959 4925 4360 4109 3918 3398 3068 2976 2482 2508 2307 2411 2165 1848 2071 2159 1956 1894 1863 2023 1891 1874 1980 1790 1849 1939 2118 1959 1816 2082 2162 2167 2141 2067 2269 2210 2317 2518 2175 2374 2420 2590 2435 2299 2417 2428 2258 2223 2019 2108 2059 2009 1990 1648 1740 1625 1534 1346 1169 1204 1201 1049 917 819 837 736 646 603 475 518 455 382 377 278 292 270 256 202 165 162 118 123 113 88 77 66 82 61 54 40 36 41 34 23 15 18 15 11 17 11 7 12 9 4 4 4 4 3 2 4 1 1 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15717 count: 6888 average: 3454.94 | standard deviation: 2978.32 | 540 235 250 265 277 227 205 198 188 134 125 122 86 86 95 72 76 62 79 71 73 57 66 59 63 48 70 62 75 51 69 52 54 56 66 76 72 61 84 80 62 81 83 72 66 68 78 71 87 102 92 76 65 81 74 72 75 53 69 57 68 49 73 48 44 37 43 29 29 29 36 32 21 16 18 14 13 14 7 8 9 8 6 6 7 8 6 5 7 2 1 3 2 0 2 1 3 0 0 1 2 1 1 0 2 0 0 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -124,9 +124,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 142 +user_time: 111 system_time: 0 -page_reclaims: 11222 +page_reclaims: 10681 page_faults: 0 swaps: 0 block_inputs: 0 @@ -135,231 +135,231 @@ block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 1846575 14772600 -total_msg_count_Response_Data: 1846395 132940440 -total_msg_count_Response_Control: 12864582 102916656 -total_msg_count_Writeback_Data: 639753 46062216 -total_msg_count_Writeback_Control: 4586013 36688104 -total_msg_count_Broadcast_Control: 9231810 73854480 -total_msg_count_Unblock_Control: 1846434 14771472 -total_msgs: 32861562 total_bytes: 422005968 +total_msg_count_Request_Control: 1842177 14737416 +total_msg_count_Response_Data: 1842009 132624648 +total_msg_count_Response_Control: 12834456 102675648 +total_msg_count_Writeback_Data: 638355 45961560 +total_msg_count_Writeback_Control: 4574040 36592320 +total_msg_count_Broadcast_Control: 9210045 73680360 +total_msg_count_Unblock_Control: 1842045 14736360 +total_msgs: 32783127 total_bytes: 421008312 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 3.80255 - links_utilized_percent_switch_0_link_0: 4.80554 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 2.79956 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 77158 5555376 [ 0 0 0 0 77158 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 537519 4300152 [ 0 0 0 0 537519 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 72761 582088 [ 0 0 0 72761 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Broadcast_Control: 538300 4306400 [ 0 0 0 538300 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 77159 617272 [ 0 0 77159 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 2500 180000 [ 0 0 0 0 2500 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 535802 4286416 [ 0 0 0 0 535802 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 26942 1939824 [ 0 0 0 0 0 26942 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 118579 948632 [ 0 0 72761 0 0 45818 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 77158 617264 [ 0 0 0 0 0 77158 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 3.77789 + links_utilized_percent_switch_0_link_0: 4.7773 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.77847 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 76290 5492880 [ 0 0 0 0 76290 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 531541 4252328 [ 0 0 0 0 531541 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 71850 574800 [ 0 0 0 71850 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 537716 4301728 [ 0 0 0 537716 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 76294 610352 [ 0 0 76294 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 2509 180648 [ 0 0 0 0 2509 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 535210 4281680 [ 0 0 0 0 535210 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 26116 1880352 [ 0 0 0 0 0 26116 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 117581 940648 [ 0 0 71850 0 0 45731 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 76291 610328 [ 0 0 0 0 0 76291 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 3.7936 - links_utilized_percent_switch_1_link_0: 4.79165 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 2.79555 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 76825 5531400 [ 0 0 0 0 76825 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 535222 4281776 [ 0 0 0 0 535222 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 72394 579152 [ 0 0 0 72394 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Broadcast_Control: 538630 4309040 [ 0 0 0 538630 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 76828 614624 [ 0 0 76828 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 2539 182808 [ 0 0 0 0 2539 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 536093 4288744 [ 0 0 0 0 536093 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 26844 1932768 [ 0 0 0 0 0 26844 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 117943 943544 [ 0 0 72394 0 0 45549 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 76826 614608 [ 0 0 0 0 0 76826 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 3.7653 + links_utilized_percent_switch_1_link_0: 4.75571 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 2.77489 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 75768 5455296 [ 0 0 0 0 75768 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 527899 4223192 [ 0 0 0 0 527899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 71411 571288 [ 0 0 0 71411 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 538238 4305904 [ 0 0 0 538238 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 75771 606168 [ 0 0 75771 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 2543 183096 [ 0 0 0 0 2543 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 535695 4285560 [ 0 0 0 0 535695 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 26086 1878192 [ 0 0 0 0 0 26086 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 116734 933872 [ 0 0 71411 0 0 45323 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 75770 606160 [ 0 0 0 0 0 75770 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 3.78298 - links_utilized_percent_switch_2_link_0: 4.78107 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.7849 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 76562 5512464 [ 0 0 0 0 76562 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 533430 4267440 [ 0 0 0 0 533430 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 72230 577840 [ 0 0 0 72230 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Broadcast_Control: 538895 4311160 [ 0 0 0 538895 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 76566 612528 [ 0 0 76566 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 2532 182304 [ 0 0 0 0 2532 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 536364 4290912 [ 0 0 0 0 536364 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 26414 1901808 [ 0 0 0 0 0 26414 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 118043 944344 [ 0 0 72230 0 0 45813 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 76566 612528 [ 0 0 0 0 0 76566 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 3.80482 + links_utilized_percent_switch_2_link_0: 4.80949 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.80015 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 77050 5547600 [ 0 0 0 0 77050 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 536881 4295048 [ 0 0 0 0 536881 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 72745 581960 [ 0 0 0 72745 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 536954 4295632 [ 0 0 0 536954 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 77053 616424 [ 0 0 77053 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2530 182160 [ 0 0 0 0 2530 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 534427 4275416 [ 0 0 0 0 534427 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 26813 1930536 [ 0 0 0 0 0 26813 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 118676 949408 [ 0 0 72745 0 0 45931 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 77051 616408 [ 0 0 0 0 0 77051 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 3.7968 - links_utilized_percent_switch_3_link_0: 4.80233 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 2.79128 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 3.79764 + links_utilized_percent_switch_3_link_0: 4.80131 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 2.79397 bw: 16000 base_latency: 1 outgoing_messages_switch_3_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 77067 5548824 [ 0 0 0 0 77067 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 536996 4295968 [ 0 0 0 0 536996 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 72780 582240 [ 0 0 0 72780 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Broadcast_Control: 538388 4307104 [ 0 0 0 538388 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 77070 616560 [ 0 0 77070 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 2435 175320 [ 0 0 0 0 2435 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 535956 4287648 [ 0 0 0 0 535956 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 26617 1916424 [ 0 0 0 0 0 26617 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 118939 951512 [ 0 0 72780 0 0 46159 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 77069 616552 [ 0 0 0 0 0 77069 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 76848 5533056 [ 0 0 0 0 76848 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 535559 4284472 [ 0 0 0 0 535559 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 72563 580504 [ 0 0 0 72563 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 537150 4297200 [ 0 0 0 537150 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 76853 614824 [ 0 0 76853 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 2432 175104 [ 0 0 0 0 2432 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 534719 4277752 [ 0 0 0 0 534719 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 26687 1921464 [ 0 0 0 0 0 26687 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 118434 947472 [ 0 0 72563 0 0 45871 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 76854 614832 [ 0 0 0 0 0 76854 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 3.79588 - links_utilized_percent_switch_4_link_0: 4.79971 bw: 16000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 2.79204 bw: 16000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 77000 5544000 [ 0 0 0 0 77000 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 536573 4292584 [ 0 0 0 0 536573 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 72734 581872 [ 0 0 0 72734 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Broadcast_Control: 538458 4307664 [ 0 0 0 538458 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 77003 616024 [ 0 0 77003 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 2470 177840 [ 0 0 0 0 2470 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 535989 4287912 [ 0 0 0 0 535989 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Data: 26638 1917936 [ 0 0 0 0 0 26638 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Writeback_Control: 118830 950640 [ 0 0 72734 0 0 46096 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 77000 616000 [ 0 0 0 0 0 77000 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 3.80564 + links_utilized_percent_switch_4_link_0: 4.81386 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 2.79743 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 77157 5555304 [ 0 0 0 0 77157 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 537662 4301296 [ 0 0 0 0 537662 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 72784 582272 [ 0 0 0 72784 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 536846 4294768 [ 0 0 0 536846 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 77161 617288 [ 0 0 77161 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 2451 176472 [ 0 0 0 0 2451 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 534395 4275160 [ 0 0 0 0 534395 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 26739 1925208 [ 0 0 0 0 0 26739 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 118829 950632 [ 0 0 72784 0 0 46045 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 77157 617256 [ 0 0 0 0 0 77157 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 3.79933 - links_utilized_percent_switch_5_link_0: 4.80022 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 2.79844 bw: 16000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 77026 5545872 [ 0 0 0 0 77026 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 536618 4292944 [ 0 0 0 0 536618 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 72681 581448 [ 0 0 0 72681 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Broadcast_Control: 538427 4307416 [ 0 0 0 538427 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 77030 616240 [ 0 0 77030 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 2480 178560 [ 0 0 0 0 2480 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 535948 4287584 [ 0 0 0 0 535948 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Data: 26945 1940040 [ 0 0 0 0 0 26945 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Writeback_Control: 118416 947328 [ 0 0 72681 0 0 45735 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 77028 616224 [ 0 0 0 0 0 77028 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 3.81066 + links_utilized_percent_switch_5_link_0: 4.81794 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 2.80338 bw: 16000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 77256 5562432 [ 0 0 0 0 77256 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 538294 4306352 [ 0 0 0 0 538294 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 72924 583392 [ 0 0 0 72924 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 536745 4293960 [ 0 0 0 536745 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 77259 618072 [ 0 0 77259 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 2540 182880 [ 0 0 0 0 2540 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 534211 4273688 [ 0 0 0 0 534211 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 26887 1935864 [ 0 0 0 0 0 26887 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 118960 951680 [ 0 0 72924 0 0 46036 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 77257 618056 [ 0 0 0 0 0 77257 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 3.78971 - links_utilized_percent_switch_6_link_0: 4.7944 bw: 16000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 2.78502 bw: 16000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 76878 5535216 [ 0 0 0 0 76878 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 535716 4285728 [ 0 0 0 0 535716 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 72531 580248 [ 0 0 0 72531 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Broadcast_Control: 538575 4308600 [ 0 0 0 538575 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 76883 615064 [ 0 0 76883 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 2515 181080 [ 0 0 0 0 2515 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 536065 4288520 [ 0 0 0 0 536065 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Data: 26322 1895184 [ 0 0 0 0 0 26322 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Writeback_Control: 118739 949912 [ 0 0 72531 0 0 46208 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 76880 615040 [ 0 0 0 0 0 76880 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 3.79483 + links_utilized_percent_switch_6_link_0: 4.79668 bw: 16000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 2.79299 bw: 16000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 76749 5525928 [ 0 0 0 0 76749 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 534680 4277440 [ 0 0 0 0 534680 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 72458 579664 [ 0 0 0 72458 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 537253 4298024 [ 0 0 0 537253 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 76752 614016 [ 0 0 76752 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 2416 173952 [ 0 0 0 0 2416 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 534839 4278712 [ 0 0 0 0 534839 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 26694 1921968 [ 0 0 0 0 0 26694 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 118222 945776 [ 0 0 72458 0 0 45764 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 76750 614000 [ 0 0 0 0 0 76750 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 3.79344 - links_utilized_percent_switch_7_link_0: 4.79695 bw: 16000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 2.78993 bw: 16000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 76949 5540328 [ 0 0 0 0 76949 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 536120 4288960 [ 0 0 0 0 536120 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 72534 580272 [ 0 0 0 72534 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Broadcast_Control: 538505 4308040 [ 0 0 0 538505 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 76951 615608 [ 0 0 76951 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 2534 182448 [ 0 0 0 0 2534 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 535977 4287816 [ 0 0 0 0 535977 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Data: 26529 1910088 [ 0 0 0 0 0 26529 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Writeback_Control: 118537 948296 [ 0 0 72534 0 0 46003 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 76951 615608 [ 0 0 0 0 0 76951 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 3.79875 + links_utilized_percent_switch_7_link_0: 4.80193 bw: 16000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 2.79556 bw: 16000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 1 8 [ 0 0 0 1 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 76885 5535720 [ 0 0 0 0 76885 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 535636 4285088 [ 0 0 0 0 535636 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 72424 579392 [ 0 0 0 72424 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 537119 4296952 [ 0 0 0 537119 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 76888 615104 [ 0 0 76888 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 2462 177264 [ 0 0 0 0 2462 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 534656 4277248 [ 0 0 0 0 534656 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 26763 1926936 [ 0 0 0 0 0 26763 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 118085 944680 [ 0 0 72424 0 0 45661 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 76885 615080 [ 0 0 0 0 0 76885 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 13.8893 - links_utilized_percent_switch_8_link_0: 10.686 bw: 16000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 17.0926 bw: 16000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Request_Control: 615490 4923920 [ 0 0 615490 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Data: 213251 15354072 [ 0 0 0 0 0 213251 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Writeback_Control: 948026 7584208 [ 0 0 580645 0 0 367381 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 615478 4923824 [ 0 0 0 0 0 615478 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 35 280 [ 0 0 0 35 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 595460 42873120 [ 0 0 0 0 595460 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 580645 4645160 [ 0 0 0 580645 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Broadcast_Control: 615454 4923632 [ 0 0 0 615454 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 13.8909 + links_utilized_percent_switch_8_link_0: 10.6869 bw: 16000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 17.095 bw: 16000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 614031 4912248 [ 0 0 614031 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 212785 15320520 [ 0 0 0 0 0 212785 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 945521 7564168 [ 0 0 579159 0 0 366362 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 614015 4912120 [ 0 0 0 0 0 614015 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 28 224 [ 0 0 0 28 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 594120 42776640 [ 0 0 0 0 594120 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 579159 4633272 [ 0 0 0 579159 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Broadcast_Control: 614003 4912024 [ 0 0 0 614003 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 5.45088 - links_utilized_percent_switch_9_link_0: 4.80555 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 4.79165 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 4.78107 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 4.80233 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 4.79971 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 4.80022 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 4.7944 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 4.79695 bw: 16000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 10.686 bw: 16000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Data: 77158 5555376 [ 0 0 0 0 77158 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 537519 4300152 [ 0 0 0 0 537519 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 72761 582088 [ 0 0 0 72761 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Broadcast_Control: 538300 4306400 [ 0 0 0 538300 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 76825 5531400 [ 0 0 0 0 76825 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 535222 4281776 [ 0 0 0 0 535222 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 72394 579152 [ 0 0 0 72394 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Broadcast_Control: 538630 4309040 [ 0 0 0 538630 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 76562 5512464 [ 0 0 0 0 76562 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Control: 533430 4267440 [ 0 0 0 0 533430 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Writeback_Control: 72230 577840 [ 0 0 0 72230 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Broadcast_Control: 538895 4311160 [ 0 0 0 538895 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 5.45123 + links_utilized_percent_switch_9_link_0: 4.7773 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 4.75571 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 4.80949 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 4.80131 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 4.81386 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 4.81795 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 4.79668 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 4.80193 bw: 16000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 10.6869 bw: 16000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 76290 5492880 [ 0 0 0 0 76290 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 531541 4252328 [ 0 0 0 0 531541 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 71850 574800 [ 0 0 0 71850 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Broadcast_Control: 537716 4301728 [ 0 0 0 537716 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 75768 5455296 [ 0 0 0 0 75768 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 527899 4223192 [ 0 0 0 0 527899 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 71411 571288 [ 0 0 0 71411 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Broadcast_Control: 538238 4305904 [ 0 0 0 538238 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 77050 5547600 [ 0 0 0 0 77050 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Control: 536881 4295048 [ 0 0 0 0 536881 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 72745 581960 [ 0 0 0 72745 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Broadcast_Control: 536954 4295632 [ 0 0 0 536954 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_3_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 77067 5548824 [ 0 0 0 0 77067 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Control: 536996 4295968 [ 0 0 0 0 536996 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Writeback_Control: 72780 582240 [ 0 0 0 72780 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Broadcast_Control: 538388 4307104 [ 0 0 0 538388 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 77000 5544000 [ 0 0 0 0 77000 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Control: 536573 4292584 [ 0 0 0 0 536573 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Writeback_Control: 72734 581872 [ 0 0 0 72734 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Broadcast_Control: 538458 4307664 [ 0 0 0 538458 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 77026 5545872 [ 0 0 0 0 77026 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Control: 536618 4292944 [ 0 0 0 0 536618 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Writeback_Control: 72681 581448 [ 0 0 0 72681 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Broadcast_Control: 538427 4307416 [ 0 0 0 538427 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 76878 5535216 [ 0 0 0 0 76878 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Control: 535716 4285728 [ 0 0 0 0 535716 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Writeback_Control: 72531 580248 [ 0 0 0 72531 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Broadcast_Control: 538575 4308600 [ 0 0 0 538575 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 76949 5540328 [ 0 0 0 0 76949 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Control: 536120 4288960 [ 0 0 0 0 536120 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Writeback_Control: 72534 580272 [ 0 0 0 72534 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Broadcast_Control: 538505 4308040 [ 0 0 0 538505 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Request_Control: 615490 4923920 [ 0 0 615490 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Writeback_Data: 213251 15354072 [ 0 0 0 0 0 213251 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Writeback_Control: 948026 7584208 [ 0 0 580645 0 0 367381 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Unblock_Control: 615478 4923824 [ 0 0 0 0 0 615478 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 76848 5533056 [ 0 0 0 0 76848 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Control: 535559 4284472 [ 0 0 0 0 535559 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 72563 580504 [ 0 0 0 72563 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Broadcast_Control: 537150 4297200 [ 0 0 0 537150 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 77157 5555304 [ 0 0 0 0 77157 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Control: 537662 4301296 [ 0 0 0 0 537662 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 72784 582272 [ 0 0 0 72784 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Broadcast_Control: 536846 4294768 [ 0 0 0 536846 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 77256 5562432 [ 0 0 0 0 77256 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Control: 538294 4306352 [ 0 0 0 0 538294 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 72924 583392 [ 0 0 0 72924 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Broadcast_Control: 536745 4293960 [ 0 0 0 536745 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 76749 5525928 [ 0 0 0 0 76749 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Control: 534680 4277440 [ 0 0 0 0 534680 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 72458 579664 [ 0 0 0 72458 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Broadcast_Control: 537253 4298024 [ 0 0 0 537253 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Request_Control: 1 8 [ 0 0 0 1 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 76885 5535720 [ 0 0 0 0 76885 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Control: 535636 4285088 [ 0 0 0 0 535636 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 72424 579392 [ 0 0 0 72424 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Broadcast_Control: 537119 4296952 [ 0 0 0 537119 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Request_Control: 614031 4912248 [ 0 0 614031 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Data: 212785 15320520 [ 0 0 0 0 0 212785 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Control: 945521 7564168 [ 0 0 579159 0 0 366362 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Unblock_Control: 614015 4912120 [ 0 0 0 0 0 614015 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -370,187 +370,188 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 77237 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77237 + system.l1_cntrl0.L1DcacheMemory_total_misses: 76356 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76356 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.6853% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.3147% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.3727% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.6273% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 77237 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 76356 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 77237 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 77237 + system.l1_cntrl0.L2cacheMemory_total_misses: 76356 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 76356 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 64.6853% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 35.3147% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 65.3727% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 34.6273% - system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 77237 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 76356 100% --- L1Cache --- - Event Counts - -Load [50136 49921 50357 50224 50012 49787 49899 50223 ] 400559 +Load [50226 50162 49933 49936 49950 49466 49962 49958 ] 399593 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [27021 27243 26701 26881 27313 27202 26808 26983 ] 216152 -L2_Replacement [76992 77018 76870 76939 77149 76815 76551 77059 ] 615393 -L1_to_L2 [864411 861133 858042 856241 861917 856546 858388 857418 ] 6874096 -Trigger_L2_to_L1D [69 68 88 81 78 83 72 66 ] 605 +Store [27060 27258 26937 27082 26459 26444 27221 27049 ] 215510 +L2_Replacement [77144 77245 76740 76875 76282 75759 77037 76837 ] 613919 +L1_to_L2 [841564 837430 840967 837780 832569 831317 842943 837009 ] 6701579 +Trigger_L2_to_L1D [75 87 65 65 62 86 68 85 ] 593 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -Complete_L2_to_L1 [69 68 88 81 78 83 72 66 ] 605 -Other_GETX [188764 188525 189074 188898 188476 188570 188959 188774 ] 1510040 -Other_GETS [349694 349902 349501 349607 349824 350060 349936 349614 ] 2798138 -Merged_GETS [3 3 7 8 4 4 3 3 ] 35 +Complete_L2_to_L1 [75 87 65 65 62 86 68 85 ] 593 +Other_GETX [188117 187930 188238 188102 188720 188737 187986 188143 ] 1505973 +Other_GETS [348729 348815 349015 349017 348996 349501 348968 349007 ] 2792048 +Merged_GETS [2 8 4 1 3 2 5 3 ] 28 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 Invalidate [0 0 0 0 0 0 0 0 ] 0 -Ack [536505 536561 535658 536064 537454 535179 533370 536950 ] 4287741 -Shared_Ack [68 57 58 56 65 43 60 46 ] 453 -Data [2826 2857 2890 2843 2907 2930 2862 2864 ] 22979 -Shared_Data [1016 1083 990 1096 1067 1056 1035 1025 ] 8368 -Exclusive_Data [73158 73086 72998 73010 73184 72839 72665 73178 ] 584118 -Writeback_Ack [72734 72681 72531 72534 72761 72394 72230 72780 ] 580645 +Ack [537613 538244 534612 535568 531478 527832 536832 535493 ] 4277672 +Shared_Ack [49 50 68 68 63 67 49 66 ] 480 +Data [2928 2931 2904 2930 2916 2838 2791 2896 ] 23134 +Shared_Data [1033 1064 1027 1109 1056 1055 1027 1034 ] 8405 +Exclusive_Data [73196 73261 72818 72846 72318 71875 73232 72918 ] 582464 +Writeback_Ack [72784 72924 72458 72424 71850 71411 72745 72563 ] 579159 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -All_acks [1073 1133 1040 1146 1126 1092 1084 1065 ] 8759 -All_acks_no_sharers [75927 75894 75839 75803 76031 75733 75479 76002 ] 606708 +All_acks [1074 1108 1087 1167 1109 1111 1066 1090 ] 8812 +All_acks_no_sharers [76083 76148 75663 75718 75181 74657 75984 75759 ] 605193 Flush_line [0 0 0 0 0 0 0 0 ] 0 Block_Ack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -I Load [50047 49835 50236 50128 49915 49677 49804 50123 ] 399765 +I Load [50137 50050 49851 49850 49875 49369 49898 49855 ] 398885 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [26955 27193 26644 26819 27244 27148 26758 26946 ] 215707 -I L2_Replacement [1447 1462 1521 1513 1490 1522 1468 1451 ] 11874 -I L1_to_L2 [325 321 333 286 324 339 341 298 ] 2567 -I Trigger_L2_to_L1D [0 1 2 2 0 2 2 1 ] 10 +I Store [27017 27205 26899 27035 26418 26400 27149 26992 ] 215115 +I L2_Replacement [1480 1454 1402 1469 1495 1454 1505 1429 ] 11688 +I L1_to_L2 [324 304 306 328 333 308 317 322 ] 2542 +I Trigger_L2_to_L1D [3 1 1 1 1 1 3 4 ] 15 I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -I Other_GETX [187875 187612 188145 187963 187564 187635 188071 187887 ] 1502752 -I Other_GETS [348011 348249 347829 347932 348133 348354 348179 347977 ] 2784664 +I Other_GETX [187219 187022 187382 187188 187800 187877 187064 187266 ] 1498818 +I Other_GETS [347074 347104 347370 347357 347306 347716 347261 347378 ] 2778566 I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 I NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 I Invalidate [0 0 0 0 0 0 0 0 ] 0 I Flush_line [0 0 0 0 0 0 0 0 ] 0 -S Load [2 0 1 0 1 1 0 0 ] 5 +S Load [0 2 0 0 0 1 0 1 ] 4 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 0 0 0 0 0 0 ] 0 -S L2_Replacement [2811 2875 2818 2892 2898 2899 2853 2828 ] 22874 -S L1_to_L2 [2840 2904 2849 2910 2927 2932 2884 2855 ] 23101 -S Trigger_L2_to_L1D [4 2 5 3 3 4 2 3 ] 26 +S Store [0 0 0 1 0 0 0 0 ] 1 +S L2_Replacement [2880 2867 2880 2982 2937 2894 2787 2845 ] 23072 +S L1_to_L2 [2918 2897 2902 3011 2962 2913 2816 2865 ] 23284 +S Trigger_L2_to_L1D [6 7 1 2 1 2 5 4 ] 28 S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -S Other_GETX [33 37 32 24 31 36 37 31 ] 261 -S Other_GETS [58 42 51 51 67 63 67 54 ] 453 +S Other_GETX [39 33 28 34 30 24 30 21 ] 239 +S Other_GETS [57 52 56 63 61 71 65 55 ] 480 S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 S NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 S Invalidate [0 0 0 0 0 0 0 0 ] 0 S Flush_line [0 0 0 0 0 0 0 0 ] 0 -O Load [1 0 0 0 0 0 0 0 ] 1 +O Load [0 0 0 1 0 0 0 0 ] 1 O Ifetch [0 0 0 0 0 0 0 0 ] 0 O Store [0 0 0 0 0 0 0 0 ] 0 -O L2_Replacement [1034 1025 1000 1026 1017 1022 1069 1000 ] 8193 -O L1_to_L2 [233 219 218 238 204 238 227 241 ] 1818 -O Trigger_L2_to_L1D [1 1 1 0 1 0 2 0 ] 6 +O L2_Replacement [985 1088 1013 1004 1016 1086 1017 993 ] 8202 +O L1_to_L2 [217 230 240 228 212 238 237 220 ] 1822 +O Trigger_L2_to_L1D [1 1 2 1 0 2 0 1 ] 8 O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -O Other_GETX [7 6 6 6 5 14 7 4 ] 55 -O Other_GETS [11 16 15 6 12 8 15 6 ] 89 -O Merged_GETS [0 2 0 2 3 2 2 1 ] 12 +O Other_GETX [9 7 8 5 5 7 6 4 ] 51 +O Other_GETS [9 12 16 12 12 11 23 13 ] 108 +O Merged_GETS [1 2 2 0 2 2 0 1 ] 10 O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 O NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 O Invalidate [0 0 0 0 0 0 0 0 ] 0 O Flush_line [0 0 0 0 0 0 0 0 ] 0 -M Load [6 4 6 4 7 7 6 3 ] 43 +M Load [5 8 8 10 6 5 8 9 ] 59 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [5 3 3 6 5 6 3 4 ] 35 -M L2_Replacement [45602 45311 45801 45565 45377 45134 45302 45711 ] 363803 -M L1_to_L2 [46867 46598 47080 46895 46684 46406 46592 46951 ] 374073 -M Trigger_L2_to_L1D [44 35 54 51 42 49 41 37 ] 353 +M Store [1 2 5 2 2 1 5 4 ] 22 +M L2_Replacement [45635 45519 45374 45234 45296 44789 45455 45429 ] 362731 +M L1_to_L2 [46902 46843 46611 46507 46580 46124 46732 46661 ] 372960 +M Trigger_L2_to_L1D [38 50 37 37 44 53 36 52 ] 347 M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -M Other_GETX [525 553 558 591 557 545 513 532 ] 4374 -M Other_GETS [1038 1031 1000 1026 1021 1034 1076 1002 ] 8228 -M Merged_GETS [0 1 3 3 1 2 1 0 ] 11 +M Other_GETX [567 512 529 570 567 540 578 537 ] 4400 +M Other_GETS [993 1090 1020 1008 1020 1093 1018 996 ] 8238 +M Merged_GETS [0 0 1 0 0 0 2 0 ] 3 M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 M NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 M Invalidate [0 0 0 0 0 0 0 0 ] 0 M Flush_line [0 0 0 0 0 0 0 0 ] 0 -MM Load [6 4 4 0 1 4 3 3 ] 25 +MM Load [6 5 1 6 4 0 6 3 ] 31 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [1 2 3 3 3 1 1 0 ] 14 -MM L2_Replacement [26098 26345 25730 25943 26367 26238 25859 26069 ] 208649 -MM L1_to_L2 [26802 27050 26484 26695 27094 26988 26585 26786 ] 214484 -MM Trigger_L2_to_L1D [20 29 26 25 32 28 25 25 ] 210 +MM Store [1 2 3 3 2 1 2 2 ] 16 +MM L2_Replacement [26164 26317 26071 26186 25538 25536 26273 26141 ] 208226 +MM L1_to_L2 [26864 27064 26752 26872 26263 26268 27008 26860 ] 213951 +MM Trigger_L2_to_L1D [27 28 24 24 16 28 24 24 ] 195 MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -MM Other_GETX [319 314 330 311 316 338 323 315 ] 2566 -MM Other_GETS [563 553 597 583 582 592 591 570 ] 4631 -MM Merged_GETS [3 0 4 3 0 0 0 2 ] 12 +MM Other_GETX [279 354 287 298 312 281 304 309 ] 2424 +MM Other_GETS [589 550 551 563 583 603 591 563 ] 4593 +MM Merged_GETS [1 6 1 1 1 0 3 2 ] 15 MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MM Invalidate [0 0 0 0 0 0 0 0 ] 0 MM Flush_line [0 0 0 0 0 0 0 0 ] 0 -IR Load [0 0 1 1 0 0 1 1 ] 4 +IR Load [2 0 0 1 0 0 2 2 ] 7 IR Ifetch [0 0 0 0 0 0 0 0 ] 0 -IR Store [0 1 1 1 0 2 1 0 ] 6 -IR L1_to_L2 [0 0 10 8 0 11 5 0 ] 34 +IR Store [1 1 1 0 1 1 1 2 ] 8 +IR L1_to_L2 [0 0 0 0 0 0 0 5 ] 5 IR Flush_line [0 0 0 0 0 0 0 0 ] 0 -SR Load [3 2 5 1 3 3 1 3 ] 21 +SR Load [2 5 1 1 1 1 2 3 ] 16 SR Ifetch [0 0 0 0 0 0 0 0 ] 0 -SR Store [1 0 0 2 0 1 1 0 ] 5 -SR L1_to_L2 [0 7 10 3 7 9 12 3 ] 51 +SR Store [4 2 0 1 0 1 3 1 ] 12 +SR L1_to_L2 [13 20 14 16 2 0 7 0 ] 72 SR Flush_line [0 0 0 0 0 0 0 0 ] 0 -OR Load [1 0 0 0 1 0 1 0 ] 3 +OR Load [1 0 1 1 0 2 0 0 ] 5 OR Ifetch [0 0 0 0 0 0 0 0 ] 0 -OR Store [0 1 1 0 0 0 1 0 ] 3 -OR L1_to_L2 [9 1 0 0 0 0 0 0 ] 10 +OR Store [0 1 1 0 0 0 0 1 ] 3 +OR L1_to_L2 [2 0 10 1 0 0 0 0 ] 13 OR Flush_line [0 0 0 0 0 0 0 0 ] 0 -MR Load [20 17 39 36 23 34 27 30 ] 226 +MR Load [25 33 30 25 28 33 19 36 ] 229 MR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MR Store [24 18 15 15 19 15 14 7 ] 127 -MR L1_to_L2 [149 91 150 151 166 136 118 77 ] 1038 +MR Store [13 17 7 12 16 20 17 16 ] 118 +MR L1_to_L2 [45 115 67 80 92 100 100 102 ] 701 +MR Flush_line [0 0 0 0 0 0 0 0 ] 0 -MMR Load [14 22 14 15 19 17 18 17 ] 136 +MMR Load [18 19 13 12 12 23 10 14 ] 121 MMR Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMR Store [6 7 12 10 13 11 7 8 ] 74 -MMR L1_to_L2 [72 72 66 74 102 75 52 93 ] 606 +MMR Store [9 9 11 12 4 5 14 10 ] 74 +MMR L1_to_L2 [37 47 30 35 16 52 58 39 ] 314 MMR Flush_line [0 0 0 0 0 0 0 0 ] 0 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM L1_to_L2 [276842 276456 272937 272333 276389 275394 273741 269624 ] 2193716 -IM Other_GETX [2 1 1 0 2 1 2 1 ] 10 -IM Other_GETS [3 4 2 3 2 2 1 2 ] 19 +IM L1_to_L2 [267178 264984 265366 266693 262467 263874 265817 265929 ] 2122308 +IM Other_GETX [0 1 0 3 2 4 1 1 ] 12 +IM Other_GETS [1 0 0 4 0 1 1 0 ] 7 IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IM Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM Ack [185315 186777 183129 184420 187041 186647 183757 185106 ] 1482192 -IM Data [996 1028 1030 1019 1045 1049 1004 1030 ] 8201 -IM Exclusive_Data [25958 26164 25614 25801 26198 26099 25753 25916 ] 207503 +IM Ack [185758 186865 184602 185732 181665 181521 186523 185609 ] 1478275 +IM Data [1034 1091 1023 1019 1005 973 995 1062 ] 8202 +IM Exclusive_Data [25982 26114 25876 26016 25413 25428 26155 25932 ] 206916 IM Flush_line [0 0 0 0 0 0 0 0 ] 0 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM L1_to_L2 [1 0 0 3 0 2 11 0 ] 17 +SM L1_to_L2 [3 1 0 2 0 4 5 0 ] 15 SM Other_GETX [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 SM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 SM Invalidate [0 0 0 0 0 0 0 0 ] 0 -SM Ack [7 0 0 14 0 7 7 0 ] 35 -SM Data [1 0 0 2 0 1 1 0 ] 5 +SM Ack [28 13 0 14 0 7 21 7 ] 90 +SM Data [4 2 0 2 0 1 3 1 ] 13 SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 SM Flush_line [0 0 0 0 0 0 0 0 ] 0 @@ -565,69 +566,69 @@ OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OM Invalidate [0 0 0 0 0 0 0 0 ] 0 -OM Ack [0 7 7 0 0 0 7 0 ] 21 +OM Ack [0 7 7 0 0 0 0 7 ] 21 OM All_acks [0 0 0 0 0 0 0 0 ] 0 -OM All_acks_no_sharers [0 1 1 0 0 0 1 0 ] 3 +OM All_acks_no_sharers [0 1 1 0 0 0 0 1 ] 3 OM Flush_line [0 0 0 0 0 0 0 0 ] 0 ISM Load [0 0 0 0 0 0 0 0 ] 0 ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 ISM Store [0 0 0 0 0 0 0 0 ] 0 ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ISM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -ISM Ack [28 15 25 9 38 27 31 21 ] 194 -ISM All_acks_no_sharers [997 1028 1030 1021 1045 1050 1005 1030 ] 8206 +ISM L1_to_L2 [0 0 0 0 0 0 1 0 ] 1 +ISM Ack [6 24 17 40 25 16 21 28 ] 177 +ISM All_acks_no_sharers [1038 1093 1023 1021 1005 974 998 1063 ] 8215 ISM Flush_line [0 0 0 0 0 0 0 0 ] 0 M_W Load [0 0 0 0 0 0 0 0 ] 0 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 M_W Store [0 0 0 0 0 0 0 0 ] 0 M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_W L1_to_L2 [452 467 453 489 544 459 543 469 ] 3876 -M_W Ack [1629 1807 1767 1717 1719 1755 1715 1612 ] 13721 -M_W All_acks_no_sharers [47200 46922 47384 47209 46986 46740 46912 47262 ] 376615 +M_W L1_to_L2 [495 483 546 484 441 445 521 480 ] 3895 +M_W Ack [1722 1778 1846 1696 1767 1619 1591 1608 ] 13627 +M_W All_acks_no_sharers [47214 47146 46942 46830 46905 46447 47077 46986 ] 375547 M_W Flush_line [0 0 0 0 0 0 0 0 ] 0 MM_W Load [0 0 0 0 0 0 0 0 ] 0 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 MM_W Store [0 0 0 0 0 0 0 0 ] 0 MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_to_L2 [801 846 874 523 893 734 591 741 ] 6003 -MM_W Ack [2493 2679 2501 2472 2713 2487 2629 2618 ] 20592 -MM_W All_acks_no_sharers [25958 26164 25614 25801 26197 26099 25753 25916 ] 207502 +MM_W L1_to_L2 [676 844 599 687 621 569 726 718 ] 5440 +MM_W Ack [2536 2677 2767 2603 2413 2420 2608 2494 ] 20518 +MM_W All_acks_no_sharers [25982 26114 25876 26016 25413 25428 26155 25932 ] 206916 MM_W Flush_line [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS L1_to_L2 [507841 505109 505606 504236 505442 501862 505670 508309 ] 4044075 -IS Other_GETX [3 1 1 1 0 0 3 2 ] 11 -IS Other_GETS [6 4 6 5 5 4 6 2 ] 38 +IS L1_to_L2 [494798 492535 496530 491719 491353 489381 497477 491607 ] 3945400 +IS Other_GETX [4 0 4 4 3 2 2 0 ] 19 +IS Other_GETS [3 1 1 5 8 2 5 0 ] 25 IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 IS NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IS Invalidate [0 0 0 0 0 0 0 0 ] 0 -IS Ack [344063 342120 345379 344164 342669 340985 342128 344477 ] 2745985 -IS Shared_Ack [65 55 54 55 62 41 55 44 ] 431 -IS Data [1829 1829 1860 1822 1862 1880 1857 1834 ] 14773 -IS Shared_Data [1016 1083 990 1096 1067 1056 1035 1025 ] 8368 -IS Exclusive_Data [47200 46922 47384 47209 46986 46740 46912 47262 ] 376615 +IS Ack [344545 343618 342316 342229 342600 339194 343073 342768 ] 2740343 +IS Shared_Ack [45 47 66 60 60 63 46 59 ] 446 +IS Data [1890 1838 1881 1909 1911 1864 1793 1833 ] 14919 +IS Shared_Data [1033 1064 1027 1109 1056 1055 1027 1034 ] 8405 +IS Exclusive_Data [47214 47147 46942 46830 46905 46447 47077 46986 ] 375548 IS Flush_line [0 0 0 0 0 0 0 0 ] 0 SS Load [0 0 0 0 0 0 0 0 ] 0 SS Ifetch [0 0 0 0 0 0 0 0 ] 0 SS Store [0 0 0 0 0 0 0 0 ] 0 SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SS L1_to_L2 [947 753 688 1089 794 730 802 724 ] 6527 -SS Ack [2970 3156 2850 3268 3274 3271 3096 3116 ] 25001 -SS Shared_Ack [3 2 4 1 3 2 5 2 ] 22 -SS All_acks [1073 1133 1040 1146 1126 1092 1084 1065 ] 8759 -SS All_acks_no_sharers [1772 1779 1810 1772 1803 1844 1808 1794 ] 14382 +SS L1_to_L2 [745 788 789 851 1045 751 868 853 ] 6690 +SS Ack [3018 3262 3057 3254 3008 3055 2995 2972 ] 24621 +SS Shared_Ack [4 3 2 8 3 4 3 7 ] 34 +SS All_acks [1074 1108 1087 1167 1109 1111 1066 1090 ] 8812 +SS All_acks_no_sharers [1849 1794 1821 1851 1858 1808 1754 1777 ] 14512 SS Flush_line [0 0 0 0 0 0 0 0 ] 0 -OI Load [0 0 0 0 1 0 0 0 ] 1 +OI Load [0 0 0 0 0 0 0 0 ] 0 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 -OI Store [1 0 0 0 0 0 0 0 ] 1 +OI Store [0 0 0 0 0 0 0 0 ] 0 OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 OI Other_GETX [0 0 0 0 0 0 0 0 ] 0 @@ -636,21 +637,21 @@ OI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 OI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OI Invalidate [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack [1038 1028 1001 1027 1019 1025 1070 1001 ] 8209 +OI Writeback_Ack [988 1094 1014 1009 1022 1090 1021 995 ] 8233 OI Flush_line [0 0 0 0 0 0 0 0 ] 0 -MI Load [12 8 11 9 11 10 9 9 ] 79 +MI Load [10 11 12 9 7 10 6 12 ] 77 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [4 1 4 7 6 3 5 7 ] 37 +MI Store [4 7 4 4 6 5 8 6 ] 44 MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MI Other_GETX [0 1 1 2 1 1 3 2 ] 11 -MI Other_GETS [4 3 1 1 2 3 1 1 ] 16 +MI Other_GETX [0 1 0 0 1 2 1 5 ] 10 +MI Other_GETS [3 6 1 5 6 4 4 2 ] 31 MI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 MI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MI Invalidate [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [71696 71652 71529 71505 71741 71368 71157 71777 ] 572425 +MI Writeback_Ack [71796 71829 71444 71415 70827 70319 71723 71563 ] 570916 MI Flush_line [0 0 0 0 0 0 0 0 ] 0 II Load [0 0 0 0 0 0 0 0 ] 0 @@ -663,44 +664,44 @@ II Other_GETS [0 0 0 0 0 0 0 0 ] 0 II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 II NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 II Invalidate [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack [0 1 1 2 1 1 3 2 ] 11 +II Writeback_Ack [0 1 0 0 1 2 1 5 ] 10 II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 II Flush_line [0 0 0 0 0 0 0 0 ] 0 -IT Load [0 0 0 1 0 0 1 1 ] 3 +IT Load [0 0 0 0 0 0 1 1 ] 2 IT Ifetch [0 0 0 0 0 0 0 0 ] 0 -IT Store [0 1 2 1 0 1 0 0 ] 5 +IT Store [0 0 0 0 0 0 0 0 ] 0 IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IT L1_to_L2 [0 0 10 32 0 11 5 0 ] 58 -IT Complete_L2_to_L1 [0 1 2 2 0 2 2 1 ] 10 +IT L1_to_L2 [4 0 1 4 0 12 0 5 ] 26 +IT Complete_L2_to_L1 [3 1 1 1 1 1 3 4 ] 15 -ST Load [0 2 3 0 2 2 1 1 ] 11 +ST Load [0 2 1 1 1 0 0 0 ] 5 ST Ifetch [0 0 0 0 0 0 0 0 ] 0 -ST Store [0 0 0 2 0 0 1 0 ] 3 +ST Store [1 1 0 1 0 0 3 1 ] 7 ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ST L1_to_L2 [0 7 10 3 7 9 12 3 ] 51 -ST Complete_L2_to_L1 [4 2 5 3 3 4 2 3 ] 26 +ST L1_to_L2 [16 28 14 16 2 10 15 7 ] 108 +ST Complete_L2_to_L1 [6 7 1 2 1 2 5 4 ] 28 -OT Load [1 0 0 0 0 0 0 0 ] 1 +OT Load [1 0 0 1 0 0 0 0 ] 2 OT Ifetch [0 0 0 0 0 0 0 0 ] 0 -OT Store [0 1 0 0 0 0 1 0 ] 2 +OT Store [0 1 1 0 0 0 0 0 ] 2 OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OT L1_to_L2 [9 1 0 0 0 0 0 0 ] 10 -OT Complete_L2_to_L1 [1 1 1 0 1 0 2 0 ] 6 +OT L1_to_L2 [2 0 22 1 0 5 0 0 ] 30 +OT Complete_L2_to_L1 [1 1 2 1 0 2 0 1 ] 8 -MT Load [12 12 28 19 15 22 15 19 ] 142 +MT Load [10 17 12 12 13 12 8 17 ] 101 MT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MT Store [20 11 8 8 14 8 11 4 ] 84 +MT Store [5 7 2 7 8 8 10 11 ] 58 MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MT L1_to_L2 [149 113 176 175 166 136 119 151 ] 1185 -MT Complete_L2_to_L1 [44 35 54 51 42 49 41 37 ] 353 +MT L1_to_L2 [154 168 108 143 148 156 141 241 ] 1259 +MT Complete_L2_to_L1 [38 50 37 37 44 53 36 52 ] 347 -MMT Load [11 15 9 10 13 10 12 13 ] 93 +MMT Load [9 10 3 6 3 10 2 5 ] 48 MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMT Store [4 4 8 7 9 6 4 7 ] 49 +MMT Store [4 3 3 4 2 2 9 3 ] 30 MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MMT L1_to_L2 [72 118 88 98 174 75 78 93 ] 796 -MMT Complete_L2_to_L1 [20 29 26 25 32 28 25 25 ] 210 +MMT L1_to_L2 [171 79 60 102 32 107 97 95 ] 743 +MMT Complete_L2_to_L1 [27 28 24 24 16 28 24 24 ] 195 MI_F Load [0 0 0 0 0 0 0 0 ] 0 MI_F Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -798,28 +799,28 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 76911 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76911 + system.l1_cntrl1.L1DcacheMemory_total_misses: 75857 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 75857 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 64.6605% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 35.3395% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 65.1594% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 34.8406% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 76911 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 75857 100% Cache Stats: system.l1_cntrl1.L2cacheMemory - system.l1_cntrl1.L2cacheMemory_total_misses: 76911 - system.l1_cntrl1.L2cacheMemory_total_demand_misses: 76911 + system.l1_cntrl1.L2cacheMemory_total_misses: 75857 + system.l1_cntrl1.L2cacheMemory_total_demand_misses: 75857 system.l1_cntrl1.L2cacheMemory_total_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L2cacheMemory_request_type_LD: 64.6605% - system.l1_cntrl1.L2cacheMemory_request_type_ST: 35.3395% + system.l1_cntrl1.L2cacheMemory_request_type_LD: 65.1594% + system.l1_cntrl1.L2cacheMemory_request_type_ST: 34.8406% - system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor: 76911 100% + system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor: 75857 100% Cache Stats: system.l1_cntrl2.L1IcacheMemory system.l1_cntrl2.L1IcacheMemory_total_misses: 0 @@ -830,28 +831,28 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory Cache Stats: system.l1_cntrl2.L1DcacheMemory - system.l1_cntrl2.L1DcacheMemory_total_misses: 76638 - system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76638 + system.l1_cntrl2.L1DcacheMemory_total_misses: 77121 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 77121 system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L1DcacheMemory_request_type_LD: 65.05% - system.l1_cntrl2.L1DcacheMemory_request_type_ST: 34.95% + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.7463% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.2537% - system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 76638 100% + system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor: 77121 100% Cache Stats: system.l1_cntrl2.L2cacheMemory - system.l1_cntrl2.L2cacheMemory_total_misses: 76638 - system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76638 + system.l1_cntrl2.L2cacheMemory_total_misses: 77121 + system.l1_cntrl2.L2cacheMemory_total_demand_misses: 77121 system.l1_cntrl2.L2cacheMemory_total_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L2cacheMemory_request_type_LD: 65.05% - system.l1_cntrl2.L2cacheMemory_request_type_ST: 34.95% + system.l1_cntrl2.L2cacheMemory_request_type_LD: 64.7463% + system.l1_cntrl2.L2cacheMemory_request_type_ST: 35.2537% - system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor: 76638 100% + system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor: 77121 100% Cache Stats: system.l1_cntrl3.L1IcacheMemory system.l1_cntrl3.L1IcacheMemory_total_misses: 0 @@ -862,28 +863,28 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory Cache Stats: system.l1_cntrl3.L1DcacheMemory - system.l1_cntrl3.L1DcacheMemory_total_misses: 77136 - system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 77136 + system.l1_cntrl3.L1DcacheMemory_total_misses: 76938 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76938 system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.0474% - system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.9526% + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 64.873% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 35.127% - system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 77136 100% + system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor: 76938 100% Cache Stats: system.l1_cntrl3.L2cacheMemory - system.l1_cntrl3.L2cacheMemory_total_misses: 77136 - system.l1_cntrl3.L2cacheMemory_total_demand_misses: 77136 + system.l1_cntrl3.L2cacheMemory_total_misses: 76938 + system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76938 system.l1_cntrl3.L2cacheMemory_total_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L2cacheMemory_request_type_LD: 65.0474% - system.l1_cntrl3.L2cacheMemory_request_type_ST: 34.9526% + system.l1_cntrl3.L2cacheMemory_request_type_LD: 64.873% + system.l1_cntrl3.L2cacheMemory_request_type_ST: 35.127% - system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor: 77136 100% + system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor: 76938 100% Cache Stats: system.l1_cntrl4.L1IcacheMemory system.l1_cntrl4.L1IcacheMemory_total_misses: 0 @@ -894,28 +895,28 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory Cache Stats: system.l1_cntrl4.L1DcacheMemory - system.l1_cntrl4.L1DcacheMemory_total_misses: 77072 - system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 77072 + system.l1_cntrl4.L1DcacheMemory_total_misses: 77236 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 77236 system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.9847% - system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.0153% + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.9788% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.0212% - system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 77072 100% + system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor: 77236 100% Cache Stats: system.l1_cntrl4.L2cacheMemory - system.l1_cntrl4.L2cacheMemory_total_misses: 77072 - system.l1_cntrl4.L2cacheMemory_total_demand_misses: 77072 + system.l1_cntrl4.L2cacheMemory_total_misses: 77236 + system.l1_cntrl4.L2cacheMemory_total_demand_misses: 77236 system.l1_cntrl4.L2cacheMemory_total_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L2cacheMemory_request_type_LD: 64.9847% - system.l1_cntrl4.L2cacheMemory_request_type_ST: 35.0153% + system.l1_cntrl4.L2cacheMemory_request_type_LD: 64.9788% + system.l1_cntrl4.L2cacheMemory_request_type_ST: 35.0212% - system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor: 77072 100% + system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor: 77236 100% Cache Stats: system.l1_cntrl5.L1IcacheMemory system.l1_cntrl5.L1IcacheMemory_total_misses: 0 @@ -926,28 +927,28 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory Cache Stats: system.l1_cntrl5.L1DcacheMemory - system.l1_cntrl5.L1DcacheMemory_total_misses: 77098 - system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77098 + system.l1_cntrl5.L1DcacheMemory_total_misses: 77346 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77346 system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.6917% - system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.3083% + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 64.7829% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 35.2171% - system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 77098 100% + system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor: 77346 100% Cache Stats: system.l1_cntrl5.L2cacheMemory - system.l1_cntrl5.L2cacheMemory_total_misses: 77098 - system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77098 + system.l1_cntrl5.L2cacheMemory_total_misses: 77346 + system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77346 system.l1_cntrl5.L2cacheMemory_total_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L2cacheMemory_request_type_LD: 64.6917% - system.l1_cntrl5.L2cacheMemory_request_type_ST: 35.3083% + system.l1_cntrl5.L2cacheMemory_request_type_LD: 64.7829% + system.l1_cntrl5.L2cacheMemory_request_type_ST: 35.2171% - system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor: 77098 100% + system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor: 77346 100% Cache Stats: system.l1_cntrl6.L1IcacheMemory system.l1_cntrl6.L1IcacheMemory_total_misses: 0 @@ -958,28 +959,28 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory Cache Stats: system.l1_cntrl6.L1DcacheMemory - system.l1_cntrl6.L1DcacheMemory_total_misses: 76971 - system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76971 + system.l1_cntrl6.L1DcacheMemory_total_misses: 76817 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76817 system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L1DcacheMemory_request_type_LD: 65.3441% - system.l1_cntrl6.L1DcacheMemory_request_type_ST: 34.6559% + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.9544% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.0456% - system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76971 100% + system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor: 76817 100% Cache Stats: system.l1_cntrl6.L2cacheMemory - system.l1_cntrl6.L2cacheMemory_total_misses: 76971 - system.l1_cntrl6.L2cacheMemory_total_demand_misses: 76971 + system.l1_cntrl6.L2cacheMemory_total_misses: 76817 + system.l1_cntrl6.L2cacheMemory_total_demand_misses: 76817 system.l1_cntrl6.L2cacheMemory_total_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L2cacheMemory_request_type_LD: 65.3441% - system.l1_cntrl6.L2cacheMemory_request_type_ST: 34.6559% + system.l1_cntrl6.L2cacheMemory_request_type_LD: 64.9544% + system.l1_cntrl6.L2cacheMemory_request_type_ST: 35.0456% - system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor: 76971 100% + system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor: 76817 100% Cache Stats: system.l1_cntrl7.L1IcacheMemory system.l1_cntrl7.L1IcacheMemory_total_misses: 0 @@ -990,28 +991,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory Cache Stats: system.l1_cntrl7.L1DcacheMemory - system.l1_cntrl7.L1DcacheMemory_total_misses: 77032 - system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77032 + system.l1_cntrl7.L1DcacheMemory_total_misses: 76953 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76953 system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L1DcacheMemory_request_type_LD: 65.1444% - system.l1_cntrl7.L1DcacheMemory_request_type_ST: 34.8556% + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.8331% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.1669% - system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 77032 100% + system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor: 76953 100% Cache Stats: system.l1_cntrl7.L2cacheMemory - system.l1_cntrl7.L2cacheMemory_total_misses: 77032 - system.l1_cntrl7.L2cacheMemory_total_demand_misses: 77032 + system.l1_cntrl7.L2cacheMemory_total_misses: 76953 + system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76953 system.l1_cntrl7.L2cacheMemory_total_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L2cacheMemory_request_type_LD: 65.1444% - system.l1_cntrl7.L2cacheMemory_request_type_ST: 34.8556% + system.l1_cntrl7.L2cacheMemory_request_type_LD: 64.8331% + system.l1_cntrl7.L2cacheMemory_request_type_ST: 35.1669% - system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor: 77032 100% + system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor: 76953 100% Cache Stats: system.dir_cntrl0.probeFilter system.dir_cntrl0.probeFilter_total_misses: 0 @@ -1022,42 +1023,42 @@ Cache Stats: system.dir_cntrl0.probeFilter Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 808732 - memory_reads: 595464 - memory_writes: 213239 - memory_refreshes: 39950 - memory_total_request_delays: 51490960 - memory_delays_per_request: 63.6688 - memory_delays_in_input_queue: 644740 - memory_delays_behind_head_of_bank_queue: 21033206 - memory_delays_stalled_at_head_of_bank_queue: 29813014 - memory_stalls_for_bank_busy: 4502024 + memory_total_requests: 806930 + memory_reads: 594122 + memory_writes: 212776 + memory_refreshes: 39853 + memory_total_request_delays: 51498750 + memory_delays_per_request: 63.8206 + memory_delays_in_input_queue: 643231 + memory_delays_behind_head_of_bank_queue: 21064894 + memory_delays_stalled_at_head_of_bank_queue: 29790625 + memory_stalls_for_bank_busy: 4493474 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 7572316 - memory_stalls_for_arbitration: 6089674 - memory_stalls_for_bus: 8254819 + memory_stalls_for_anti_starvation: 7575671 + memory_stalls_for_arbitration: 6083551 + memory_stalls_for_bus: 8248278 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2040089 - memory_stalls_for_read_read_turnaround: 1354092 - accesses_per_bank: 25475 25139 25271 25488 25557 25416 25567 25333 25458 25373 25338 25458 25092 25108 25283 25098 25229 25311 25279 25201 25282 25211 25353 25102 25122 24801 25255 24809 25129 25398 25504 25292 + memory_stalls_for_read_write_turnaround: 2039991 + memory_stalls_for_read_read_turnaround: 1349660 + accesses_per_bank: 25394 25147 25249 25452 25456 25358 25579 25279 25469 25293 25305 25375 25044 25055 25245 25044 25128 25227 25252 25145 25222 25167 25232 25093 25055 24752 25158 24793 25021 25318 25415 25208 --- Directory --- - Event Counts - -GETX [218960 ] 218960 -GETS [405714 ] 405714 -PUT [580856 ] 580856 -Unblock [11 ] 11 -UnblockS [23141 ] 23141 -UnblockM [592326 ] 592326 -Writeback_Clean [8089 ] 8089 -Writeback_Dirty [120 ] 120 -Writeback_Exclusive_Clean [359292 ] 359292 -Writeback_Exclusive_Dirty [213131 ] 213131 +GETX [218369 ] 218369 +GETS [404869 ] 404869 +PUT [579376 ] 579376 +Unblock [10 ] 10 +UnblockS [23324 ] 23324 +UnblockM [590681 ] 590681 +Writeback_Clean [8134 ] 8134 +Writeback_Dirty [99 ] 99 +Writeback_Exclusive_Clean [358228 ] 358228 +Writeback_Exclusive_Dirty [212686 ] 212686 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [595460 ] 595460 -Memory_Ack [213239 ] 213239 +Memory_Data [594120 ] 594120 +Memory_Ack [212774 ] 212774 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 @@ -1066,22 +1067,22 @@ Exclusive_Data [0 ] 0 All_acks_and_shared_data [0 ] 0 All_acks_and_owner_data [0 ] 0 All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [35 ] 35 +All_Unblocks [28 ] 28 GETF [0 ] 0 PUTF [0 ] 0 - Transitions - -NX GETX [58 ] 58 -NX GETS [89 ] 89 -NX PUT [8220 ] 8220 +NX GETX [54 ] 54 +NX GETS [108 ] 108 +NX PUT [8243 ] 8243 NX Pf_Replacement [0 ] 0 NX DMA_READ [0 ] 0 NX DMA_WRITE [0 ] 0 NX GETF [0 ] 0 -NO GETX [6952 ] 6952 -NO GETS [12875 ] 12875 -NO PUT [572425 ] 572425 +NO GETX [6834 ] 6834 +NO GETS [12862 ] 12862 +NO PUT [570916 ] 570916 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 @@ -1095,16 +1096,16 @@ S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 S GETF [0 ] 0 -O GETX [8140 ] 8140 -O GETS [14773 ] 14773 +O GETX [8154 ] 8154 +O GETS [14919 ] 14919 O PUT [0 ] 0 O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O GETF [0 ] 0 -E GETX [200571 ] 200571 -E GETS [371997 ] 371997 +E GETX [200097 ] 200097 +E GETS [370975 ] 370975 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 @@ -1143,11 +1144,11 @@ NO_R Exclusive_Data [0 ] 0 NO_R All_acks_and_data_no_sharers [0 ] 0 NO_R GETF [0 ] 0 -NO_B GETX [23 ] 23 -NO_B GETS [35 ] 35 -NO_B PUT [211 ] 211 -NO_B UnblockS [8312 ] 8312 -NO_B UnblockM [592289 ] 592289 +NO_B GETX [18 ] 18 +NO_B GETS [28 ] 28 +NO_B PUT [217 ] 217 +NO_B UnblockS [8362 ] 8362 +NO_B UnblockM [590650 ] 590650 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 @@ -1156,8 +1157,8 @@ NO_B GETF [0 ] 0 NO_B_X GETX [0 ] 0 NO_B_X GETS [0 ] 0 NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [9 ] 9 -NO_B_X UnblockM [14 ] 14 +NO_B_X UnblockS [5 ] 5 +NO_B_X UnblockM [13 ] 13 NO_B_X Pf_Replacement [0 ] 0 NO_B_X DMA_READ [0 ] 0 NO_B_X DMA_WRITE [0 ] 0 @@ -1166,8 +1167,8 @@ NO_B_X GETF [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [12 ] 12 -NO_B_S UnblockM [23 ] 23 +NO_B_S UnblockS [10 ] 10 +NO_B_S UnblockM [18 ] 18 NO_B_S Pf_Replacement [0 ] 0 NO_B_S DMA_READ [0 ] 0 NO_B_S DMA_WRITE [0 ] 0 @@ -1176,42 +1177,42 @@ NO_B_S GETF [0 ] 0 NO_B_S_W GETX [0 ] 0 NO_B_S_W GETS [0 ] 0 NO_B_S_W PUT [0 ] 0 -NO_B_S_W UnblockS [35 ] 35 +NO_B_S_W UnblockS [28 ] 28 NO_B_S_W Pf_Replacement [0 ] 0 NO_B_S_W DMA_READ [0 ] 0 NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [35 ] 35 +NO_B_S_W All_Unblocks [28 ] 28 NO_B_S_W GETF [0 ] 0 O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 -O_B UnblockS [14773 ] 14773 +O_B UnblockS [14919 ] 14919 O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 O_B GETF [0 ] 0 -NO_B_W GETX [2034 ] 2034 -NO_B_W GETS [3695 ] 3695 +NO_B_W GETX [2005 ] 2005 +NO_B_W GETS [3743 ] 3743 NO_B_W PUT [0 ] 0 NO_B_W UnblockS [0 ] 0 NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [580687 ] 580687 +NO_B_W Memory_Data [579201 ] 579201 NO_B_W GETF [0 ] 0 -O_B_W GETX [45 ] 45 -O_B_W GETS [103 ] 103 +O_B_W GETX [51 ] 51 +O_B_W GETS [90 ] 90 O_B_W PUT [0 ] 0 O_B_W UnblockS [0 ] 0 O_B_W Pf_Replacement [0 ] 0 O_B_W DMA_READ [0 ] 0 O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [14773 ] 14773 +O_B_W Memory_Data [14919 ] 14919 O_B_W GETF [0 ] 0 NO_W GETX [0 ] 0 @@ -1322,35 +1323,35 @@ O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 O_DR_B GETF [0 ] 0 -WB GETX [77 ] 77 -WB GETS [161 ] 161 +WB GETX [94 ] 94 +WB GETS [184 ] 184 WB PUT [0 ] 0 -WB Unblock [11 ] 11 -WB Writeback_Clean [8089 ] 8089 -WB Writeback_Dirty [120 ] 120 -WB Writeback_Exclusive_Clean [359292 ] 359292 -WB Writeback_Exclusive_Dirty [213131 ] 213131 +WB Unblock [10 ] 10 +WB Writeback_Clean [8134 ] 8134 +WB Writeback_Dirty [99 ] 99 +WB Writeback_Exclusive_Clean [358228 ] 358228 +WB Writeback_Exclusive_Dirty [212686 ] 212686 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 WB GETF [0 ] 0 -WB_O_W GETX [1 ] 1 -WB_O_W GETS [3 ] 3 +WB_O_W GETX [0 ] 0 +WB_O_W GETS [1 ] 1 WB_O_W PUT [0 ] 0 WB_O_W Pf_Replacement [0 ] 0 WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [120 ] 120 +WB_O_W Memory_Ack [99 ] 99 WB_O_W GETF [0 ] 0 -WB_E_W GETX [1059 ] 1059 -WB_E_W GETS [1983 ] 1983 +WB_E_W GETX [1062 ] 1062 +WB_E_W GETS [1959 ] 1959 WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [213119 ] 213119 +WB_E_W Memory_Ack [212675 ] 212675 WB_E_W GETF [0 ] 0 NO_F GETX [0 ] 0 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index 4cc740cdd..5f7af8d92 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -1,74 +1,74 @@ -system.cpu4: completed 10000 read, 5368 write accesses @1896819 -system.cpu0: completed 10000 read, 5327 write accesses @1910725 -system.cpu5: completed 10000 read, 5493 write accesses @1929799 -system.cpu2: completed 10000 read, 5341 write accesses @1933339 -system.cpu1: completed 10000 read, 5585 write accesses @1940439 -system.cpu7: completed 10000 read, 5510 write accesses @1944309 -system.cpu6: completed 10000 read, 5231 write accesses @1946469 -system.cpu3: completed 10000 read, 5461 write accesses @1963728 -system.cpu0: completed 20000 read, 10595 write accesses @3805359 -system.cpu2: completed 20000 read, 10586 write accesses @3820599 -system.cpu3: completed 20000 read, 10867 write accesses @3829429 -system.cpu4: completed 20000 read, 10761 write accesses @3846318 -system.cpu6: completed 20000 read, 10413 write accesses @3857570 -system.cpu5: completed 20000 read, 10874 write accesses @3859158 -system.cpu7: completed 20000 read, 10747 write accesses @3866018 -system.cpu1: completed 20000 read, 11096 write accesses @3900361 -system.cpu3: completed 30000 read, 16232 write accesses @5720598 -system.cpu2: completed 30000 read, 15880 write accesses @5740479 -system.cpu7: completed 30000 read, 16148 write accesses @5769618 -system.cpu0: completed 30000 read, 16080 write accesses @5774128 -system.cpu6: completed 30000 read, 15848 write accesses @5779758 -system.cpu4: completed 30000 read, 16090 write accesses @5782899 -system.cpu1: completed 30000 read, 16550 write accesses @5821028 -system.cpu5: completed 30000 read, 16439 write accesses @5824429 -system.cpu3: completed 40000 read, 21587 write accesses @7653178 -system.cpu0: completed 40000 read, 21623 write accesses @7670365 -system.cpu2: completed 40000 read, 21273 write accesses @7684699 -system.cpu7: completed 40000 read, 21445 write accesses @7713338 -system.cpu6: completed 40000 read, 21321 write accesses @7719841 -system.cpu4: completed 40000 read, 21451 write accesses @7726211 -system.cpu1: completed 40000 read, 21832 write accesses @7734179 -system.cpu5: completed 40000 read, 21913 write accesses @7792051 -system.cpu0: completed 50000 read, 27135 write accesses @9608539 -system.cpu4: completed 50000 read, 26878 write accesses @9641109 -system.cpu3: completed 50000 read, 27076 write accesses @9643149 -system.cpu6: completed 50000 read, 26709 write accesses @9646978 -system.cpu2: completed 50000 read, 26734 write accesses @9654151 -system.cpu7: completed 50000 read, 26876 write accesses @9682409 -system.cpu5: completed 50000 read, 27248 write accesses @9689700 -system.cpu1: completed 50000 read, 27302 write accesses @9695809 -system.cpu0: completed 60000 read, 32449 write accesses @11491779 -system.cpu3: completed 60000 read, 32401 write accesses @11561629 -system.cpu6: completed 60000 read, 32081 write accesses @11565049 -system.cpu7: completed 60000 read, 32080 write accesses @11566379 -system.cpu4: completed 60000 read, 32352 write accesses @11573283 -system.cpu5: completed 60000 read, 32718 write accesses @11575018 -system.cpu2: completed 60000 read, 32150 write accesses @11585149 -system.cpu1: completed 60000 read, 32680 write accesses @11632119 -system.cpu0: completed 70000 read, 37771 write accesses @13429459 -system.cpu7: completed 70000 read, 37234 write accesses @13447809 -system.cpu4: completed 70000 read, 37607 write accesses @13456099 -system.cpu6: completed 70000 read, 37614 write accesses @13484149 -system.cpu5: completed 70000 read, 38039 write accesses @13487310 -system.cpu3: completed 70000 read, 37787 write accesses @13523429 -system.cpu1: completed 70000 read, 38168 write accesses @13544389 -system.cpu2: completed 70000 read, 37479 write accesses @13559549 -system.cpu0: completed 80000 read, 43086 write accesses @15325259 -system.cpu4: completed 80000 read, 42854 write accesses @15364368 -system.cpu7: completed 80000 read, 42627 write accesses @15378763 -system.cpu6: completed 80000 read, 42741 write accesses @15379020 -system.cpu3: completed 80000 read, 43087 write accesses @15412649 -system.cpu5: completed 80000 read, 43504 write accesses @15439469 -system.cpu1: completed 80000 read, 43522 write accesses @15480429 -system.cpu2: completed 80000 read, 42764 write accesses @15493419 -system.cpu0: completed 90000 read, 48539 write accesses @17246629 -system.cpu5: completed 90000 read, 48747 write accesses @17277729 -system.cpu6: completed 90000 read, 48097 write accesses @17293679 -system.cpu4: completed 90000 read, 48405 write accesses @17331308 -system.cpu7: completed 90000 read, 48155 write accesses @17349560 -system.cpu3: completed 90000 read, 48566 write accesses @17362109 -system.cpu2: completed 90000 read, 48156 write accesses @17435789 -system.cpu1: completed 90000 read, 49002 write accesses @17469038 -system.cpu0: completed 100000 read, 53926 write accesses @19175808 +system.cpu2: completed 10000 read, 5414 write accesses @1885229 +system.cpu1: completed 10000 read, 5302 write accesses @1890168 +system.cpu3: completed 10000 read, 5360 write accesses @1915688 +system.cpu7: completed 10000 read, 5642 write accesses @1921599 +system.cpu4: completed 10000 read, 5405 write accesses @1938259 +system.cpu0: completed 10000 read, 5276 write accesses @1954368 +system.cpu5: completed 10000 read, 5459 write accesses @1966609 +system.cpu6: completed 10000 read, 5462 write accesses @1976068 +system.cpu7: completed 20000 read, 10887 write accesses @3769229 +system.cpu2: completed 20000 read, 10839 write accesses @3812419 +system.cpu3: completed 20000 read, 10626 write accesses @3834729 +system.cpu4: completed 20000 read, 10795 write accesses @3849978 +system.cpu6: completed 20000 read, 10711 write accesses @3859128 +system.cpu1: completed 20000 read, 10709 write accesses @3868509 +system.cpu0: completed 20000 read, 10487 write accesses @3883829 +system.cpu5: completed 20000 read, 10981 write accesses @3886079 +system.cpu7: completed 30000 read, 16345 write accesses @5699399 +system.cpu2: completed 30000 read, 16163 write accesses @5707569 +system.cpu3: completed 30000 read, 16054 write accesses @5753608 +system.cpu4: completed 30000 read, 16228 write accesses @5762628 +system.cpu1: completed 30000 read, 15958 write accesses @5788449 +system.cpu5: completed 30000 read, 16533 write accesses @5821749 +system.cpu0: completed 30000 read, 15924 write accesses @5824589 +system.cpu6: completed 30000 read, 16129 write accesses @5834348 +system.cpu7: completed 40000 read, 21899 write accesses @7654549 +system.cpu4: completed 40000 read, 21830 write accesses @7666399 +system.cpu2: completed 40000 read, 21530 write accesses @7670799 +system.cpu3: completed 40000 read, 21349 write accesses @7687899 +system.cpu5: completed 40000 read, 21853 write accesses @7706209 +system.cpu1: completed 40000 read, 21335 write accesses @7740999 +system.cpu0: completed 40000 read, 21207 write accesses @7785709 +system.cpu6: completed 40000 read, 21495 write accesses @7787590 +system.cpu2: completed 50000 read, 26843 write accesses @9593621 +system.cpu4: completed 50000 read, 27326 write accesses @9612259 +system.cpu7: completed 50000 read, 27316 write accesses @9617878 +system.cpu5: completed 50000 read, 27312 write accesses @9642000 +system.cpu3: completed 50000 read, 26959 write accesses @9653721 +system.cpu6: completed 50000 read, 26913 write accesses @9694819 +system.cpu1: completed 50000 read, 26597 write accesses @9697068 +system.cpu0: completed 50000 read, 26748 write accesses @9738679 +system.cpu2: completed 60000 read, 32089 write accesses @11467409 +system.cpu4: completed 60000 read, 32735 write accesses @11491009 +system.cpu5: completed 60000 read, 32633 write accesses @11520189 +system.cpu7: completed 60000 read, 32794 write accesses @11539719 +system.cpu3: completed 60000 read, 32320 write accesses @11596739 +system.cpu0: completed 60000 read, 32089 write accesses @11619948 +system.cpu6: completed 60000 read, 32335 write accesses @11642479 +system.cpu1: completed 60000 read, 31985 write accesses @11677349 +system.cpu4: completed 70000 read, 38118 write accesses @13391159 +system.cpu2: completed 70000 read, 37499 write accesses @13402439 +system.cpu5: completed 70000 read, 38044 write accesses @13419869 +system.cpu7: completed 70000 read, 38074 write accesses @13454578 +system.cpu3: completed 70000 read, 37729 write accesses @13532920 +system.cpu0: completed 70000 read, 37349 write accesses @13535619 +system.cpu6: completed 70000 read, 37688 write accesses @13582560 +system.cpu1: completed 70000 read, 37275 write accesses @13667028 +system.cpu4: completed 80000 read, 43427 write accesses @15278311 +system.cpu5: completed 80000 read, 43269 write accesses @15290669 +system.cpu2: completed 80000 read, 42945 write accesses @15354249 +system.cpu7: completed 80000 read, 43467 write accesses @15377329 +system.cpu3: completed 80000 read, 42965 write accesses @15400433 +system.cpu0: completed 80000 read, 42539 write accesses @15436171 +system.cpu6: completed 80000 read, 42985 write accesses @15520509 +system.cpu1: completed 80000 read, 42662 write accesses @15613459 +system.cpu4: completed 90000 read, 48791 write accesses @17215361 +system.cpu5: completed 90000 read, 48724 write accesses @17227780 +system.cpu2: completed 90000 read, 48516 write accesses @17311279 +system.cpu7: completed 90000 read, 48844 write accesses @17312899 +system.cpu3: completed 90000 read, 48360 write accesses @17361088 +system.cpu0: completed 90000 read, 47879 write accesses @17373929 +system.cpu6: completed 90000 read, 48388 write accesses @17425899 +system.cpu1: completed 90000 read, 48067 write accesses @17546750 +system.cpu5: completed 100000 read, 53955 write accesses @19129228 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index a28e6b92e..3955733a4 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 1 2011 11:03:29 -gem5 started Dec 1 2011 11:03:44 -gem5 executing on SC2B0612 -command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer +gem5 compiled Jan 10 2012 12:41:45 +gem5 started Jan 10 2012 12:42:10 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 19175808 because maximum number of loads reached +Exiting @ tick 19129228 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 253ebdbe3..f21ff7ff3 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.019176 # Number of seconds simulated -sim_ticks 19175808 # Number of ticks simulated +sim_seconds 0.019129 # Number of seconds simulated +sim_ticks 19129228 # Number of ticks simulated sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 134618 # Simulator tick rate (ticks/s) -host_mem_usage 381740 # Number of bytes of host memory used -host_seconds 142.45 # Real time elapsed on the host -system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 53926 # number of write accesses completed +host_tick_rate 171766 # Simulator tick rate (ticks/s) +host_mem_usage 371104 # Number of bytes of host memory used +host_seconds 111.37 # Real time elapsed on the host +system.cpu0.num_reads 99101 # number of read accesses completed +system.cpu0.num_writes 52800 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98882 # number of read accesses completed -system.cpu1.num_writes 53707 # number of write accesses completed +system.cpu1.num_reads 98228 # number of read accesses completed +system.cpu1.num_writes 52503 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98977 # number of read accesses completed -system.cpu2.num_writes 53060 # number of write accesses completed +system.cpu2.num_reads 99319 # number of read accesses completed +system.cpu2.num_writes 53658 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99594 # number of read accesses completed -system.cpu3.num_writes 53686 # number of write accesses completed +system.cpu3.num_reads 99213 # number of read accesses completed +system.cpu3.num_writes 53383 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99524 # number of read accesses completed -system.cpu4.num_writes 53497 # number of write accesses completed +system.cpu4.num_reads 99738 # number of read accesses completed +system.cpu4.num_writes 54039 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99742 # number of read accesses completed -system.cpu5.num_writes 53984 # number of write accesses completed +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 53955 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99887 # number of read accesses completed -system.cpu6.num_writes 53292 # number of write accesses completed +system.cpu6.num_reads 98936 # number of read accesses completed +system.cpu6.num_writes 53130 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99347 # number of read accesses completed -system.cpu7.num_writes 53300 # number of write accesses completed +system.cpu7.num_reads 99406 # number of read accesses completed +system.cpu7.num_writes 53912 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index 8c6320343..510e558ad 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -10,6 +10,7 @@ type=System children=dir_cntrl0 l1_cntrl0 physmem ruby tester mem_mode=timing memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -68,6 +69,7 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 +is_icache=false latency=1 replacement_policy=PSEUDO_LRU size=1024 @@ -95,6 +97,7 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 +is_icache=false latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -103,6 +106,7 @@ start_index_bit=6 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 +is_icache=true latency=2 replacement_policy=PSEUDO_LRU size=256 @@ -111,6 +115,7 @@ start_index_bit=6 [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 +is_icache=false latency=10 replacement_policy=PSEUDO_LRU size=512 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index bb46babb6..577ddb4ca 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Dec/01/2011 11:03:43 +Real time: Jan/10/2012 12:44:12 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.46 -Virtual_time_in_minutes: 0.00766667 -Virtual_time_in_hours: 0.000127778 -Virtual_time_in_days: 5.32407e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 -Ruby_current_time: 208411 +Ruby_current_time: 213131 Ruby_start_time: 0 -Ruby_cycles: 208411 +Ruby_cycles: 213131 -mbytes_resident: 37.7227 -mbytes_total: 242.977 -resident_ratio: 0.155268 +mbytes_resident: 35.9023 +mbytes_total: 232.609 +resident_ratio: 0.154396 -ruby_cycles_executed: [ 208412 ] +ruby_cycles_executed: [ 213132 ] Busy Controller Counts: L1Cache-0:0 @@ -65,17 +65,17 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 956 average: 15.7887 | standard deviation: 1.16133 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 5 75 863 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.7883 | standard deviation: 1.14907 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 4 82 879 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 64 max: 6811 count: 941 average: 3500.81 | standard deviation: 1691.94 | 69 9 9 1 10 4 14 20 8 15 4 7 3 4 5 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 7 1 9 8 8 18 13 21 17 21 28 37 31 37 40 46 28 35 31 30 27 28 32 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 64 max: 6620 count: 49 average: 3597.61 | standard deviation: 1746.75 | 5 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 64 max: 6811 count: 841 average: 3677.95 | standard deviation: 1562.59 | 61 8 4 0 5 4 3 14 3 9 2 3 1 3 5 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 1 2 5 1 9 7 8 18 12 20 17 18 28 37 27 35 37 43 27 32 30 29 26 26 31 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 8 max: 1159 count: 51 average: 486.745 | standard deviation: 255.245 | 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] -miss_latency_L1Cache: [binsize: 1 max: 116 count: 70 average: 16.2571 | standard deviation: 35.3332 | 0 9 16 14 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 0 1 ] -miss_latency_L2Cache: [binsize: 32 max: 4640 count: 34 average: 2534.59 | standard deviation: 1878.68 | 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ] -miss_latency_Directory: [binsize: 64 max: 6811 count: 837 average: 3831.48 | standard deviation: 1383.91 | 0 0 9 1 9 4 14 19 7 15 4 7 2 4 4 3 1 3 1 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 6 1 8 8 8 16 12 19 17 21 27 36 30 35 39 45 28 35 30 27 27 27 31 25 19 20 32 20 12 11 9 7 4 3 5 2 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 64 max: 6858 count: 963 average: 3505.41 | standard deviation: 1666 | 67 16 4 2 10 5 22 17 6 9 5 8 4 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 9 13 24 17 17 29 22 26 32 30 39 37 41 29 39 32 34 28 34 30 27 28 19 18 10 3 7 12 5 7 7 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 6253 count: 51 average: 3926.14 | standard deviation: 1480.7 | 3 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 64 max: 6858 count: 863 average: 3652.34 | standard deviation: 1553.9 | 60 13 3 2 7 3 9 13 1 7 0 4 1 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 5 5 4 4 12 8 13 21 16 16 26 21 25 32 30 37 35 38 27 38 28 33 28 33 28 23 25 18 18 9 1 7 10 5 7 7 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1022 count: 49 average: 479.796 | standard deviation: 243.565 | 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 114 count: 72 average: 17.4167 | standard deviation: 35.9832 | 0 9 9 12 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 1 2 0 0 1 0 0 0 1 ] +miss_latency_L2Cache: [binsize: 32 max: 5339 count: 41 average: 2283.05 | standard deviation: 1908.79 | 5 0 0 6 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_Directory: [binsize: 64 max: 6858 count: 850 average: 3859.83 | standard deviation: 1320.43 | 0 0 4 0 10 4 22 15 6 8 5 8 3 2 4 3 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 9 12 23 17 15 27 21 25 31 29 38 35 41 29 39 32 33 28 32 30 27 28 19 18 9 3 7 12 5 7 6 4 7 1 5 3 3 3 2 0 0 0 1 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,14 +85,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_dir_Times: 837 -miss_latency_LD_L1Cache: [binsize: 1 max: 104 count: 6 average: 19.8333 | standard deviation: 41.248 | 0 1 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_Directory: [binsize: 64 max: 6620 count: 43 average: 4096.84 | standard deviation: 1184.49 | 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 1 1 0 3 0 0 4 2 3 3 1 3 1 1 1 2 1 1 0 0 0 1 2 1 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 64 average: 15.9219 | standard deviation: 35.0852 | 0 8 16 12 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 0 1 ] -miss_latency_ST_L2Cache: [binsize: 32 max: 4640 count: 31 average: 2779.26 | standard deviation: 1783.63 | 5 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 1 0 2 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 2 0 0 0 1 0 1 ] -miss_latency_ST_Directory: [binsize: 64 max: 6811 count: 746 average: 4029.46 | standard deviation: 1146.93 | 0 0 4 0 4 4 3 13 2 9 2 3 0 3 4 2 1 2 0 0 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 2 0 1 0 0 0 2 4 1 8 7 8 16 11 18 17 18 27 36 26 33 36 42 27 32 29 26 26 25 30 24 19 20 32 19 10 10 9 6 2 3 5 1 1 1 0 0 1 2 2 0 0 2 0 0 1 0 0 1 1 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 9 count: 3 average: 6.33333 | standard deviation: 3.08221 | 0 0 0 1 0 0 0 1 0 1 ] -miss_latency_IFETCH_Directory: [binsize: 8 max: 1159 count: 48 average: 516.771 | standard deviation: 231.637 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 3 1 0 0 1 0 0 0 0 0 0 0 0 3 1 2 2 1 0 1 1 0 0 0 0 2 0 2 2 1 0 0 0 1 0 2 1 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] +imcomplete_dir_Times: 850 +miss_latency_LD_L1Cache: [binsize: 1 max: 103 count: 4 average: 27.75 | standard deviation: 50.183 | 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 32 max: 6253 count: 47 average: 4257.91 | standard deviation: 974.148 | 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 1 0 1 0 0 3 0 1 1 0 0 0 0 0 1 1 0 2 0 3 1 1 1 0 2 2 1 0 0 0 1 0 0 2 1 3 3 0 1 0 0 0 1 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 114 count: 66 average: 17.197 | standard deviation: 35.8598 | 0 8 9 11 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 2 0 0 1 0 0 0 1 ] +miss_latency_ST_L2Cache: [binsize: 32 max: 5339 count: 37 average: 2523.57 | standard deviation: 1854.34 | 3 0 0 4 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 0 1 0 1 0 1 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_Directory: [binsize: 64 max: 6858 count: 760 average: 4022.97 | standard deviation: 1109.22 | 0 0 3 0 7 2 9 11 1 6 0 4 0 2 3 1 0 1 0 1 2 1 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 4 3 3 4 11 8 12 20 16 14 24 20 24 31 29 36 33 38 27 38 28 32 28 31 28 23 25 18 18 8 1 7 10 5 7 6 4 7 0 5 3 2 3 2 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 2 average: 4 | standard deviation: 0 | 0 0 0 0 2 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 112 count: 4 average: 58.25 | standard deviation: 60.9289 | 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1022 count: 43 average: 541.14 | standard deviation: 189.677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 4 3 1 1 0 2 1 0 0 0 0 0 0 0 3 1 2 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 2 1 0 1 0 0 0 2 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -124,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10661 +page_reclaims: 10130 page_faults: 0 swaps: 0 block_inputs: 0 @@ -133,98 +134,98 @@ block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 2511 20088 -total_msg_count_Response_Data: 2511 180792 -total_msg_count_Writeback_Data: 2248 161856 -total_msg_count_Writeback_Control: 5220 41760 -total_msg_count_Unblock_Control: 2506 20048 -total_msgs: 14996 total_bytes: 424544 +total_msg_count_Request_Control: 2553 20424 +total_msg_count_Response_Data: 2550 183600 +total_msg_count_Writeback_Data: 2292 165024 +total_msg_count_Writeback_Control: 5291 42328 +total_msg_count_Unblock_Control: 2546 20368 +total_msgs: 15232 total_bytes: 431744 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 2.12273 - links_utilized_percent_switch_0_link_0: 2.00637 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 2.23909 bw: 16000 base_latency: 1 +links_utilized_percent_switch_0: 2.11044 + links_utilized_percent_switch_0_link_0: 1.9922 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.22868 bw: 16000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 750 54000 [ 0 0 0 0 0 750 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 836 6688 [ 0 0 0 0 0 836 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 923 7384 [ 0 0 845 0 0 78 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 2.12153 - links_utilized_percent_switch_1_link_0: 2.23669 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 2.00637 bw: 16000 base_latency: 1 +links_utilized_percent_switch_1: 2.10985 + links_utilized_percent_switch_1_link_0: 2.2275 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 1.9922 bw: 16000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 850 6800 [ 0 0 850 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 848 6784 [ 0 0 0 0 0 848 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 2.12153 - links_utilized_percent_switch_2_link_0: 2.00637 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 2.23669 bw: 16000 base_latency: 1 +links_utilized_percent_switch_2: 2.11009 + links_utilized_percent_switch_2_link_0: 1.9922 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.22797 bw: 16000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 837 60264 [ 0 0 0 0 837 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 830 6640 [ 0 0 0 830 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 837 6696 [ 0 0 837 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 749 53928 [ 0 0 0 0 0 749 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 910 7280 [ 0 0 830 0 0 80 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 835 6680 [ 0 0 0 0 0 835 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 850 61200 [ 0 0 0 0 850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 842 6736 [ 0 0 0 842 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 851 6808 [ 0 0 851 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 764 55008 [ 0 0 0 0 0 764 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 921 7368 [ 0 0 843 0 0 78 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 849 6792 [ 0 0 0 0 0 849 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory - system.l1_cntrl0.L1IcacheMemory_total_misses: 51 - system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 51 + system.l1_cntrl0.L1IcacheMemory_total_misses: 47 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 47 system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 51 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 47 100% Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 820 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 820 + system.l1_cntrl0.L1DcacheMemory_total_misses: 846 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 846 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.2439% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.7561% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.55556% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.4444% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 820 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 846 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 871 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 871 + system.l1_cntrl0.L2cacheMemory_total_misses: 893 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 893 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.93685% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2078% - system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.85534% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 5.26316% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.4737% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.26316% - system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 871 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 893 100% --- L1Cache --- - Event Counts - -Load [49 ] 49 -Ifetch [55 ] 55 -Store [863 ] 863 -L2_Replacement [830 ] 830 -L1_to_L2 [15990 ] 15990 -Trigger_L2_to_L1D [31 ] 31 -Trigger_L2_to_L1I [3 ] 3 -Complete_L2_to_L1 [34 ] 34 +Load [51 ] 51 +Ifetch [52 ] 52 +Store [889 ] 889 +L2_Replacement [845 ] 845 +L1_to_L2 [15901 ] 15901 +Trigger_L2_to_L1D [37 ] 37 +Trigger_L2_to_L1I [4 ] 4 +Complete_L2_to_L1 [41 ] 41 Other_GETX [0 ] 0 Other_GETS [0 ] 0 Merged_GETS [0 ] 0 @@ -235,18 +236,18 @@ Ack [0 ] 0 Shared_Ack [0 ] 0 Data [0 ] 0 Shared_Data [0 ] 0 -Exclusive_Data [837 ] 837 -Writeback_Ack [830 ] 830 +Exclusive_Data [850 ] 850 +Writeback_Ack [842 ] 842 Writeback_Nack [0 ] 0 All_acks [0 ] 0 -All_acks_no_sharers [836 ] 836 +All_acks_no_sharers [850 ] 850 Flush_line [0 ] 0 Block_Ack [0 ] 0 - Transitions - -I Load [43 ] 43 -I Ifetch [48 ] 48 -I Store [746 ] 746 +I Load [47 ] 47 +I Ifetch [43 ] 43 +I Store [762 ] 762 I L2_Replacement [0 ] 0 I L1_to_L2 [0 ] 0 I Trigger_L2_to_L1D [0 ] 0 @@ -288,11 +289,11 @@ O Invalidate [0 ] 0 O Flush_line [0 ] 0 M Load [0 ] 0 -M Ifetch [0 ] 0 +M Ifetch [1 ] 1 M Store [0 ] 0 -M L2_Replacement [80 ] 80 -M L1_to_L2 [87 ] 87 -M Trigger_L2_to_L1D [7 ] 7 +M L2_Replacement [79 ] 79 +M L1_to_L2 [88 ] 88 +M Trigger_L2_to_L1D [9 ] 9 M Trigger_L2_to_L1I [0 ] 0 M Other_GETX [0 ] 0 M Other_GETS [0 ] 0 @@ -302,13 +303,13 @@ M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 M Flush_line [0 ] 0 -MM Load [6 ] 6 -MM Ifetch [0 ] 0 -MM Store [63 ] 63 -MM L2_Replacement [750 ] 750 -MM L1_to_L2 [779 ] 779 -MM Trigger_L2_to_L1D [24 ] 24 -MM Trigger_L2_to_L1I [3 ] 3 +MM Load [4 ] 4 +MM Ifetch [1 ] 1 +MM Store [65 ] 65 +MM L2_Replacement [766 ] 766 +MM L1_to_L2 [800 ] 800 +MM Trigger_L2_to_L1D [28 ] 28 +MM Trigger_L2_to_L1I [4 ] 4 MM Other_GETX [0 ] 0 MM Other_GETS [0 ] 0 MM Merged_GETS [0 ] 0 @@ -337,20 +338,21 @@ OR Flush_line [0 ] 0 MR Load [0 ] 0 MR Ifetch [0 ] 0 -MR Store [7 ] 7 -MR L1_to_L2 [52 ] 52 +MR Store [9 ] 9 +MR L1_to_L2 [43 ] 43 +MR Flush_line [0 ] 0 MMR Load [0 ] 0 -MMR Ifetch [3 ] 3 -MMR Store [24 ] 24 -MMR L1_to_L2 [92 ] 92 +MMR Ifetch [4 ] 4 +MMR Store [28 ] 28 +MMR L1_to_L2 [78 ] 78 MMR Flush_line [0 ] 0 IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 IM L2_Replacement [0 ] 0 -IM L1_to_L2 [9590 ] 9590 +IM L1_to_L2 [9451 ] 9451 IM Other_GETX [0 ] 0 IM Other_GETS [0 ] 0 IM Other_GETS_No_Mig [0 ] 0 @@ -358,7 +360,7 @@ IM NC_DMA_GETS [0 ] 0 IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 -IM Exclusive_Data [746 ] 746 +IM Exclusive_Data [760 ] 760 IM Flush_line [0 ] 0 SM Load [0 ] 0 @@ -405,7 +407,7 @@ M_W Load [0 ] 0 M_W Ifetch [0 ] 0 M_W Store [0 ] 0 M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [263 ] 263 +M_W L1_to_L2 [239 ] 239 M_W Ack [0 ] 0 M_W All_acks_no_sharers [90 ] 90 M_W Flush_line [0 ] 0 @@ -414,16 +416,16 @@ MM_W Load [0 ] 0 MM_W Ifetch [0 ] 0 MM_W Store [1 ] 1 MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [4391 ] 4391 +MM_W L1_to_L2 [4486 ] 4486 MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [746 ] 746 +MM_W All_acks_no_sharers [760 ] 760 MM_W Flush_line [0 ] 0 IS Load [0 ] 0 IS Ifetch [0 ] 0 IS Store [0 ] 0 IS L2_Replacement [0 ] 0 -IS L1_to_L2 [619 ] 619 +IS L1_to_L2 [611 ] 611 IS Other_GETX [0 ] 0 IS Other_GETS [0 ] 0 IS Other_GETS_No_Mig [0 ] 0 @@ -433,7 +435,7 @@ IS Ack [0 ] 0 IS Shared_Ack [0 ] 0 IS Data [0 ] 0 IS Shared_Data [0 ] 0 -IS Exclusive_Data [91 ] 91 +IS Exclusive_Data [90 ] 90 IS Flush_line [0 ] 0 SS Load [0 ] 0 @@ -462,8 +464,8 @@ OI Writeback_Ack [0 ] 0 OI Flush_line [0 ] 0 MI Load [0 ] 0 -MI Ifetch [3 ] 3 -MI Store [1 ] 1 +MI Ifetch [1 ] 1 +MI Store [2 ] 2 MI L2_Replacement [0 ] 0 MI L1_to_L2 [0 ] 0 MI Other_GETX [0 ] 0 @@ -472,7 +474,7 @@ MI Merged_GETS [0 ] 0 MI Other_GETS_No_Mig [0 ] 0 MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 -MI Writeback_Ack [830 ] 830 +MI Writeback_Ack [842 ] 842 MI Flush_line [0 ] 0 II Load [0 ] 0 @@ -512,17 +514,17 @@ OT Complete_L2_to_L1 [0 ] 0 MT Load [0 ] 0 MT Ifetch [0 ] 0 -MT Store [2 ] 2 +MT Store [3 ] 3 MT L2_Replacement [0 ] 0 -MT L1_to_L2 [52 ] 52 -MT Complete_L2_to_L1 [7 ] 7 +MT L1_to_L2 [81 ] 81 +MT Complete_L2_to_L1 [9 ] 9 MMT Load [0 ] 0 -MMT Ifetch [1 ] 1 +MMT Ifetch [2 ] 2 MMT Store [19 ] 19 MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [65 ] 65 -MMT Complete_L2_to_L1 [27 ] 27 +MMT L1_to_L2 [24 ] 24 +MMT Complete_L2_to_L1 [32 ] 32 MI_F Load [0 ] 0 MI_F Ifetch [0 ] 0 @@ -620,42 +622,42 @@ Cache Stats: system.dir_cntrl0.probeFilter Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 1586 - memory_reads: 837 - memory_writes: 749 - memory_refreshes: 435 - memory_total_request_delays: 1175 - memory_delays_per_request: 0.740858 - memory_delays_in_input_queue: 168 - memory_delays_behind_head_of_bank_queue: 3 - memory_delays_stalled_at_head_of_bank_queue: 1004 - memory_stalls_for_bank_busy: 269 + memory_total_requests: 1614 + memory_reads: 850 + memory_writes: 764 + memory_refreshes: 444 + memory_total_request_delays: 1136 + memory_delays_per_request: 0.703841 + memory_delays_in_input_queue: 148 + memory_delays_behind_head_of_bank_queue: 4 + memory_delays_stalled_at_head_of_bank_queue: 984 + memory_stalls_for_bank_busy: 278 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 76 - memory_stalls_for_bus: 376 + memory_stalls_for_arbitration: 71 + memory_stalls_for_bus: 363 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 160 - memory_stalls_for_read_read_turnaround: 123 - accesses_per_bank: 59 53 47 85 75 57 58 40 39 53 46 64 35 48 41 50 42 53 58 54 53 40 32 36 33 45 49 57 36 47 49 52 + memory_stalls_for_read_write_turnaround: 151 + memory_stalls_for_read_read_turnaround: 121 + accesses_per_bank: 44 58 47 90 75 58 58 48 47 49 56 50 32 37 53 44 53 47 48 55 53 40 39 41 34 44 54 59 55 47 50 49 --- Directory --- - Event Counts - -GETX [747 ] 747 -GETS [92 ] 92 -PUT [900 ] 900 +GETX [760 ] 760 +GETS [91 ] 91 +PUT [889 ] 889 Unblock [0 ] 0 UnblockS [0 ] 0 -UnblockM [835 ] 835 +UnblockM [848 ] 848 Writeback_Clean [0 ] 0 Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [79 ] 79 -Writeback_Exclusive_Dirty [749 ] 749 +Writeback_Exclusive_Clean [78 ] 78 +Writeback_Exclusive_Dirty [764 ] 764 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [837 ] 837 -Memory_Ack [749 ] 749 +Memory_Data [850 ] 850 +Memory_Ack [763 ] 763 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 @@ -679,7 +681,7 @@ NX GETF [0 ] 0 NO GETX [0 ] 0 NO GETS [0 ] 0 -NO PUT [830 ] 830 +NO PUT [842 ] 842 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 @@ -701,8 +703,8 @@ O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O GETF [0 ] 0 -E GETX [746 ] 746 -E GETS [91 ] 91 +E GETX [760 ] 760 +E GETS [90 ] 90 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 @@ -743,9 +745,9 @@ NO_R GETF [0 ] 0 NO_B GETX [0 ] 0 NO_B GETS [0 ] 0 -NO_B PUT [70 ] 70 +NO_B PUT [47 ] 47 NO_B UnblockS [0 ] 0 -NO_B UnblockM [835 ] 835 +NO_B UnblockM [848 ] 848 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 @@ -799,7 +801,7 @@ NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [837 ] 837 +NO_B_W Memory_Data [850 ] 850 NO_B_W GETF [0 ] 0 O_B_W GETX [0 ] 0 @@ -920,14 +922,14 @@ O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 O_DR_B GETF [0 ] 0 -WB GETX [1 ] 1 +WB GETX [0 ] 0 WB GETS [1 ] 1 WB PUT [0 ] 0 WB Unblock [0 ] 0 WB Writeback_Clean [0 ] 0 WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [79 ] 79 -WB Writeback_Exclusive_Dirty [749 ] 749 +WB Writeback_Exclusive_Clean [78 ] 78 +WB Writeback_Exclusive_Dirty [764 ] 764 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 @@ -948,7 +950,7 @@ WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [749 ] 749 +WB_E_W Memory_Ack [763 ] 763 WB_E_W GETF [0 ] 0 NO_F GETX [0 ] 0 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 02ed228c9..61c2c4ddb 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 1 2011 11:03:29 -gem5 started Dec 1 2011 11:03:42 -gem5 executing on SC2B0612 -command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer +gem5 compiled Jan 10 2012 12:41:45 +gem5 started Jan 10 2012 12:44:12 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA_SE_MOESI_hammer/gem5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 208411 because Ruby Tester completed +Exiting @ tick 213131 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 493c4848e..902497bf0 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000208 # Number of seconds simulated -sim_ticks 208411 # Number of ticks simulated +sim_seconds 0.000213 # Number of seconds simulated +sim_ticks 213131 # Number of ticks simulated sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1657766 # Simulator tick rate (ticks/s) -host_mem_usage 248812 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 2251733 # Simulator tick rate (ticks/s) +host_mem_usage 238196 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host ---------- End Simulation Statistics ---------- |