diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-09 17:52:13 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-09 17:52:13 -0400 |
| commit | 0746e92cd3c0255b51959cd3de9bc067c34bdb1e (patch) | |
| tree | 0d925214cabcfafd4f8b31c83581c8454d6d62d4 /tests | |
| parent | cd8023a1eebba79e60a62c5cd9bd0ec111d9d88c (diff) | |
| download | gem5-0746e92cd3c0255b51959cd3de9bc067c34bdb1e.tar.xz | |
stats: Add DRAM power statistics to reference output
Diffstat (limited to 'tests')
65 files changed, 4002 insertions, 2821 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 1996e7f30..498e99dcf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.883224 # Nu sim_ticks 1883224346500 # Number of ticks simulated final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 283997 # Simulator instruction rate (inst/s) -host_op_rate 283997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9530044697 # Simulator tick rate (ticks/s) -host_mem_usage 369276 # Number of bytes of host memory used -host_seconds 197.61 # Real time elapsed on the host +host_inst_rate 293967 # Simulator instruction rate (inst/s) +host_op_rate 293967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9864607727 # Simulator tick rate (ticks/s) +host_mem_usage 317632 # Number of bytes of host memory used +host_seconds 190.91 # Real time elapsed on the host sim_insts 56120453 # Number of instructions simulated sim_ops 56120453 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -286,6 +286,24 @@ system.physmem.memoryStateTime::REF 62884900000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 232613640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 244724760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 126922125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 133530375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1579227000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1579858800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 380855520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 384808320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 123002864400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 123002864400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 59595719580 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 60657122565 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1077656022750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1076724967500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1262574225015 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1262727876720 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.433163 # Core power per rank (mW) +system.physmem.averagePower::1 670.514753 # Core power per rank (mW) system.membus.trans_dist::ReadReq 295760 # Transaction distribution system.membus.trans_dist::ReadResp 295744 # Transaction distribution system.membus.trans_dist::WriteReq 9618 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 05acb9522..6b49ba8d7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.905068 # Nu sim_ticks 1905067807000 # Number of ticks simulated final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162284 # Simulator instruction rate (inst/s) -host_op_rate 162284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5403466257 # Simulator tick rate (ticks/s) -host_mem_usage 375680 # Number of bytes of host memory used -host_seconds 352.56 # Real time elapsed on the host +host_inst_rate 133407 # Simulator instruction rate (inst/s) +host_op_rate 133407 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4441980470 # Simulator tick rate (ticks/s) +host_mem_usage 322876 # Number of bytes of host memory used +host_seconds 428.88 # Real time elapsed on the host sim_insts 57215334 # Number of instructions simulated sim_ops 57215334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -299,6 +299,24 @@ system.physmem.memoryStateTime::REF 63614200000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 37016700250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 243908280 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 243137160 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 133084875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 132664125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1597408800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1598750400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 384555600 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 406470960 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 124429375200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 124429375200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 57078983475 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 56985810705 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1092967983000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1093049713500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1276835299230 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1276845922050 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.232898 # Core power per rank (mW) +system.physmem.averagePower::1 670.238474 # Core power per rank (mW) system.membus.trans_dist::ReadReq 296853 # Transaction distribution system.membus.trans_dist::ReadResp 296773 # Transaction distribution system.membus.trans_dist::WriteReq 13665 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index fe03695e1..9bbc0f37f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.859039 # Nu sim_ticks 1859038679000 # Number of ticks simulated final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164972 # Simulator instruction rate (inst/s) -host_op_rate 164972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5794497034 # Simulator tick rate (ticks/s) -host_mem_usage 371088 # Number of bytes of host memory used -host_seconds 320.83 # Real time elapsed on the host +host_inst_rate 145866 # Simulator instruction rate (inst/s) +host_op_rate 145866 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5123409698 # Simulator tick rate (ticks/s) +host_mem_usage 320704 # Number of bytes of host memory used +host_seconds 362.85 # Real time elapsed on the host sim_insts 52927600 # Number of instructions simulated sim_ops 52927600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -292,6 +292,24 @@ system.physmem.memoryStateTime::REF 62077340000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 230322960 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 232953840 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 125672250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 127107750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1579991400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1570522200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 379747440 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 381438720 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 121423277040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 121423277040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 55561357620 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 55436078745 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1066684481250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1066794375000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1245984849960 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1245965753295 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.231146 # Core power per rank (mW) +system.physmem.averagePower::1 670.220874 # Core power per rank (mW) system.membus.trans_dist::ReadReq 296046 # Transaction distribution system.membus.trans_dist::ReadResp 295957 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 85c742feb..d190e77d2 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.841612 # Nu sim_ticks 1841612450000 # Number of ticks simulated final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222430 # Simulator instruction rate (inst/s) -host_op_rate 222430 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6273480939 # Simulator tick rate (ticks/s) -host_mem_usage 370816 # Number of bytes of host memory used -host_seconds 293.56 # Real time elapsed on the host +host_inst_rate 216403 # Simulator instruction rate (inst/s) +host_op_rate 216403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6103470891 # Simulator tick rate (ticks/s) +host_mem_usage 319676 # Number of bytes of host memory used +host_seconds 301.73 # Real time elapsed on the host sim_insts 65295558 # Number of instructions simulated sim_ops 65295558 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -295,6 +295,24 @@ system.physmem.memoryStateTime::REF 61495460000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 13553394000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 81912600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 81527040 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 44694375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 44484000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 325096200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 324948000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 152701200 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 149713920 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 120285119760 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 120285119760 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 46099249605 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 45830401695 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1064529191250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1064765022750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1231517964990 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1231481217165 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.717430 # Core power per rank (mW) +system.physmem.averagePower::1 668.697476 # Core power per rank (mW) system.membus.trans_dist::ReadReq 294949 # Transaction distribution system.membus.trans_dist::ReadResp 294942 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index e666b7d0c..37ec7ce19 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.658488 # Nu sim_ticks 2658488068000 # Number of ticks simulated final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84054 # Simulator instruction rate (inst/s) -host_op_rate 101215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3545231727 # Simulator tick rate (ticks/s) -host_mem_usage 436668 # Number of bytes of host memory used -host_seconds 749.88 # Real time elapsed on the host +host_inst_rate 70694 # Simulator instruction rate (inst/s) +host_op_rate 85127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2981704600 # Simulator tick rate (ticks/s) +host_mem_usage 438480 # Number of bytes of host memory used +host_seconds 891.60 # Real time elapsed on the host sim_insts 63030433 # Number of instructions simulated sim_ops 75898814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -295,6 +295,24 @@ system.physmem.memoryStateTime::REF 88772580000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3923753400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3920570640 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2140936875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2139200250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 60504077400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 60482814600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 378432000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 369729360 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 173639166480 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 173639166480 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 146077789680 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 145345956705 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1466951353500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1467593312250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1853615509335 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1853490750285 # Total energy per rank (pJ) +system.physmem.averagePower::0 697.245591 # Core power per rank (mW) +system.physmem.averagePower::1 697.198662 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index c758d0203..7ddeb2364 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.566404 # Nu sim_ticks 2566404096500 # Number of ticks simulated final_tick 2566404096500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108919 # Simulator instruction rate (inst/s) -host_op_rate 131120 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4613194748 # Simulator tick rate (ticks/s) -host_mem_usage 411228 # Number of bytes of host memory used -host_seconds 556.32 # Real time elapsed on the host +host_inst_rate 75271 # Simulator instruction rate (inst/s) +host_op_rate 90613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3188038304 # Simulator tick rate (ticks/s) +host_mem_usage 412076 # Number of bytes of host memory used +host_seconds 805.01 # Real time elapsed on the host sim_insts 60593541 # Number of instructions simulated sim_ops 72944224 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -278,6 +278,24 @@ system.physmem.memoryStateTime::REF 85697820000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 271160177250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3833766720 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3836442960 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2091837000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2093297250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 59650523400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 59648323800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 342357840 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 349945920 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 167624935920 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 167624935920 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 149819559525 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 149631019200 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1408420983750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1408586370000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1791783964155 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1791770335050 # Total energy per rank (pJ) +system.physmem.averagePower::0 698.169437 # Core power per rank (mW) +system.physmem.averagePower::1 698.164127 # Core power per rank (mW) system.membus.trans_dist::ReadReq 16348869 # Transaction distribution system.membus.trans_dist::ReadResp 16348869 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index ffb671fcc..40f0cc994 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,27 +4,15 @@ sim_seconds 2.542157 # Nu sim_ticks 2542156879500 # Number of ticks simulated final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45011 # Simulator instruction rate (inst/s) -host_op_rate 54228 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1897222602 # Simulator tick rate (ticks/s) -host_mem_usage 464684 # Number of bytes of host memory used -host_seconds 1339.94 # Real time elapsed on the host +host_inst_rate 45837 # Simulator instruction rate (inst/s) +host_op_rate 55223 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1932040285 # Simulator tick rate (ticks/s) +host_mem_usage 415140 # Number of bytes of host memory used +host_seconds 1315.79 # Real time elapsed on the host sim_insts 60311972 # Number of instructions simulated sim_ops 72661518 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -287,6 +275,36 @@ system.physmem.memoryStateTime::REF 84888180000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ) +system.physmem.averagePower::0 698.235540 # Core power per rank (mW) +system.physmem.averagePower::1 698.237375 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) system.membus.trans_dist::ReadReq 16348037 # Transaction distribution system.membus.trans_dist::ReadResp 16348037 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 74aa0b266..3111af0d9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,174 +1,192 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.607938 # Number of seconds simulated -sim_ticks 2607938427000 # Number of ticks simulated -final_tick 2607938427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.607932 # Number of seconds simulated +sim_ticks 2607931908500 # Number of ticks simulated +final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67776 # Simulator instruction rate (inst/s) -host_op_rate 81630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2816320200 # Simulator tick rate (ticks/s) -host_mem_usage 438748 # Number of bytes of host memory used -host_seconds 926.01 # Real time elapsed on the host -sim_insts 62761521 # Number of instructions simulated -sim_ops 75590331 # Number of ops (including micro ops) simulated +host_inst_rate 52184 # Simulator instruction rate (inst/s) +host_op_rate 62850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2168410643 # Simulator tick rate (ticks/s) +host_mem_usage 492092 # Number of bytes of host memory used +host_seconds 1202.69 # Real time elapsed on the host +sim_insts 62761278 # Number of instructions simulated +sim_ops 75589768 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 121488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 457468 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 4606656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 70992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 622136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5389248 # Number of bytes read from this memory -system.physmem.bytes_read::total 132379476 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 121488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 70992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 192480 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4393536 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory +system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7422672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 4422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 7207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 71979 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1152 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 84207 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15317537 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 68649 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 825933 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46439182 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 98 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 46584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 175414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1766398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 238555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 2066478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50760200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 46584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27222 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 73805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1684678 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1154987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2846184 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1684678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46439182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 98 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 46584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 181932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1766398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1393542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 2066478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53606384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15317537 # Number of read requests accepted -system.physmem.writeReqs 825933 # Number of write requests accepted -system.physmem.readBursts 15317537 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 825933 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976408384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3913984 # Total number of bytes read from write queue -system.physmem.bytesWritten 7445376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132379476 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7422672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 61156 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709570 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15921 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 957324 # Per bank write bursts -system.physmem.perBankRdBursts::1 954296 # Per bank write bursts -system.physmem.perBankRdBursts::2 951048 # Per bank write bursts -system.physmem.perBankRdBursts::3 951190 # Per bank write bursts -system.physmem.perBankRdBursts::4 960560 # Per bank write bursts -system.physmem.perBankRdBursts::5 954642 # Per bank write bursts -system.physmem.perBankRdBursts::6 950634 # Per bank write bursts -system.physmem.perBankRdBursts::7 950367 # Per bank write bursts -system.physmem.perBankRdBursts::8 957475 # Per bank write bursts -system.physmem.perBankRdBursts::9 955236 # Per bank write bursts -system.physmem.perBankRdBursts::10 950657 # Per bank write bursts -system.physmem.perBankRdBursts::11 950055 # Per bank write bursts -system.physmem.perBankRdBursts::12 957021 # Per bank write bursts -system.physmem.perBankRdBursts::13 954396 # Per bank write bursts -system.physmem.perBankRdBursts::14 950984 # Per bank write bursts -system.physmem.perBankRdBursts::15 950496 # Per bank write bursts -system.physmem.perBankWrBursts::0 7473 # Per bank write bursts -system.physmem.perBankWrBursts::1 7236 # Per bank write bursts -system.physmem.perBankWrBursts::2 7209 # Per bank write bursts -system.physmem.perBankWrBursts::3 7113 # Per bank write bursts -system.physmem.perBankWrBursts::4 7623 # Per bank write bursts -system.physmem.perBankWrBursts::5 7510 # Per bank write bursts -system.physmem.perBankWrBursts::6 7170 # Per bank write bursts -system.physmem.perBankWrBursts::7 7098 # Per bank write bursts -system.physmem.perBankWrBursts::8 7538 # Per bank write bursts -system.physmem.perBankWrBursts::9 7733 # Per bank write bursts -system.physmem.perBankWrBursts::10 7167 # Per bank write bursts -system.physmem.perBankWrBursts::11 6553 # Per bank write bursts -system.physmem.perBankWrBursts::12 7248 # Per bank write bursts -system.physmem.perBankWrBursts::13 7122 # Per bank write bursts -system.physmem.perBankWrBursts::14 7350 # Per bank write bursts -system.physmem.perBankWrBursts::15 7191 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15317443 # Number of read requests accepted +system.physmem.writeReqs 825902 # Number of write requests accepted +system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue +system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 957415 # Per bank write bursts +system.physmem.perBankRdBursts::1 954356 # Per bank write bursts +system.physmem.perBankRdBursts::2 951532 # Per bank write bursts +system.physmem.perBankRdBursts::3 951095 # Per bank write bursts +system.physmem.perBankRdBursts::4 960453 # Per bank write bursts +system.physmem.perBankRdBursts::5 954333 # Per bank write bursts +system.physmem.perBankRdBursts::6 950562 # Per bank write bursts +system.physmem.perBankRdBursts::7 950350 # Per bank write bursts +system.physmem.perBankRdBursts::8 957423 # Per bank write bursts +system.physmem.perBankRdBursts::9 955252 # Per bank write bursts +system.physmem.perBankRdBursts::10 950399 # Per bank write bursts +system.physmem.perBankRdBursts::11 949996 # Per bank write bursts +system.physmem.perBankRdBursts::12 957025 # Per bank write bursts +system.physmem.perBankRdBursts::13 954231 # Per bank write bursts +system.physmem.perBankRdBursts::14 950565 # Per bank write bursts +system.physmem.perBankRdBursts::15 950154 # Per bank write bursts +system.physmem.perBankWrBursts::0 7537 # Per bank write bursts +system.physmem.perBankWrBursts::1 7271 # Per bank write bursts +system.physmem.perBankWrBursts::2 7519 # Per bank write bursts +system.physmem.perBankWrBursts::3 7339 # Per bank write bursts +system.physmem.perBankWrBursts::4 7525 # Per bank write bursts +system.physmem.perBankWrBursts::5 7506 # Per bank write bursts +system.physmem.perBankWrBursts::6 7304 # Per bank write bursts +system.physmem.perBankWrBursts::7 7173 # Per bank write bursts +system.physmem.perBankWrBursts::8 7520 # Per bank write bursts +system.physmem.perBankWrBursts::9 7613 # Per bank write bursts +system.physmem.perBankWrBursts::10 6934 # Per bank write bursts +system.physmem.perBankWrBursts::11 6533 # Per bank write bursts +system.physmem.perBankWrBursts::12 7225 # Per bank write bursts +system.physmem.perBankWrBursts::13 7011 # Per bank write bursts +system.physmem.perBankWrBursts::14 7249 # Per bank write bursts +system.physmem.perBankWrBursts::15 7053 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2607936588500 # Total gap between requests +system.physmem.totGap 2607930021000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) system.physmem.readPktSize::3 15138841 # Read request sizes (log2) -system.physmem.readPktSize::4 3422 # Read request sizes (log2) +system.physmem.readPktSize::4 3437 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175215 # Read request sizes (log2) +system.physmem.readPktSize::6 175106 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68649 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1023042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1020695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1089381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 978756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1042832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2673243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2574268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3352848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 134504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 116771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 107699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19722 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68618 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -184,45 +202,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -233,57 +251,57 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1020745 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 963.858515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 884.982288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 219.503901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 33091 3.24% 3.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19420 1.90% 5.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8756 0.86% 6.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2666 0.26% 6.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3150 0.31% 6.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2102 0.21% 6.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8576 0.84% 7.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1045 0.10% 7.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 941939 92.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1020745 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6738 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2264.229742 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98171.784681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6732 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6738 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.265361 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.193186 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.647301 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3643 54.07% 54.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 48 0.71% 54.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1665 24.71% 79.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1002 14.87% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 147 2.18% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 65 0.96% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 57 0.85% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 53 0.79% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 33 0.49% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 11 0.16% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.13% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6738 # Writes before turning the bus around for reads -system.physmem.totQLat 399562219250 # Total ticks spent queuing -system.physmem.totMemAccLat 685619363000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76281905000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26189.84 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads +system.physmem.totQLat 400005056750 # Total ticks spent queuing +system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44939.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s @@ -291,565 +309,564 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.95 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.38 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.08 # Average write queue length when enqueuing -system.physmem.readRowHits 14264224 # Number of row buffer hits during reads -system.physmem.writeRowHits 87746 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing +system.physmem.readRowHits 14262971 # Number of row buffer hits during reads +system.physmem.writeRowHits 87526 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.41 # Row buffer hit rate for writes -system.physmem.avgGap 161547.46 # Average gap between requests +system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes +system.physmem.avgGap 161548.30 # Average gap between requests system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2277806510000 # Time in different power states -system.physmem.memoryStateTime::REF 87084660000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states +system.physmem.memoryStateTime::REF 87084400000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 243043451250 # Time in different power states +system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16496833 # Transaction distribution -system.membus.trans_dist::ReadResp 16496833 # Transaction distribution -system.membus.trans_dist::WriteReq 769198 # Transaction distribution -system.membus.trans_dist::WriteResp 769198 # Transaction distribution -system.membus.trans_dist::Writeback 68649 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58344 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 23631 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15921 # Transaction distribution -system.membus.trans_dist::ReadExReq 15704 # Transaction distribution -system.membus.trans_dist::ReadExResp 8956 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384374 # Packet count per connected master and slave (bytes) +system.physmem.actEnergy::0 3862736640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3855690720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2107644000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2103799500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 59514748800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 59475351000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 383447520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 370254240 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 170337086400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 170337086400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 141921165285 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 140687744850 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1440263842500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1441345790250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1818390671145 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1818175716960 # Total energy per rank (pJ) +system.physmem.averagePower::0 697.255251 # Core power per rank (mW) +system.physmem.averagePower::1 697.172828 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 16496763 # Transaction distribution +system.membus.trans_dist::ReadResp 16496763 # Transaction distribution +system.membus.trans_dist::WriteReq 769202 # Transaction distribution +system.membus.trans_dist::WriteResp 769202 # Transaction distribution +system.membus.trans_dist::Writeback 68618 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution +system.membus.trans_dist::ReadExReq 15703 # Transaction distribution +system.membus.trans_dist::ReadExResp 8933 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13882 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045303 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4445635 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34723267 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392689 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27764 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18691620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21116357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 142226885 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 72802 # Total snoops (count) -system.membus.snoop_fanout::samples 332587 # Request fanout histogram +system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 72850 # Total snoops (count) +system.membus.snoop_fanout::samples 332577 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332587 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332587 # Request fanout histogram -system.membus.reqLayer0.occupancy 1569233990 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332577 # Request fanout histogram +system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11974494 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1549500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17698127000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5007859946 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37384021831 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 91703 # number of replacements -system.l2c.tags.tagsinuse 54901.298749 # Cycle average of tags in use -system.l2c.tags.total_refs 387577 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 156499 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.476546 # Average number of references to valid blocks. +system.l2c.tags.replacements 91666 # number of replacements +system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use +system.l2c.tags.total_refs 387443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 7788.394578 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.341349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.981982 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 674.734753 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1668.636810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24293.005252 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.419961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 676.905989 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3493.827255 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16296.050819 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.118841 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 7736.589041 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.331203 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.025467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 672.803532 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1677.780077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24285.244228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.407687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 678.722766 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3493.963497 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16278.332216 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.118051 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.010296 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.025461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370682 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.010266 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.025601 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370563 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010329 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.053312 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248658 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.837727 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 52420 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 12367 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 215 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5971 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 46232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2304 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 9709 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.799866 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.188705 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5051801 # Number of tag accesses -system.l2c.tags.data_accesses 5051801 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 125 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 40 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 4738 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 15024 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72119 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 182 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 64 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7352 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 16354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75111 # number of ReadReq hits -system.l2c.ReadReq_hits::total 191109 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 213952 # number of Writeback hits -system.l2c.Writeback_hits::total 213952 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3082 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2112 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5194 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 89 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 239 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 1876 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2742 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4618 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 125 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 40 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 4738 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 16900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 72119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 182 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7352 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 19096 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 75111 # number of demand (read+write) hits -system.l2c.demand_hits::total 195727 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 125 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 40 # number of overall hits -system.l2c.overall_hits::cpu0.inst 4738 # number of overall hits -system.l2c.overall_hits::cpu0.data 16900 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 72119 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 182 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7352 # number of overall hits -system.l2c.overall_hits::cpu1.data 19096 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 75111 # number of overall hits -system.l2c.overall_hits::total 195727 # number of overall hits +system.l2c.tags.occ_percent::cpu1.inst 0.010356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.053314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248388 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.836658 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 52524 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 12291 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5897 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 46469 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2272 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 9679 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.801453 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.187546 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5049935 # Number of tag accesses +system.l2c.tags.data_accesses 5049935 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 44 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 4746 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 14884 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72204 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 72 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7407 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 16636 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 74707 # number of ReadReq hits +system.l2c.ReadReq_hits::total 190984 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 213987 # number of Writeback hits +system.l2c.Writeback_hits::total 213987 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3107 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2045 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5152 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 90 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 245 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 1803 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2746 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4549 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 44 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 4746 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 16687 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 72204 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 168 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 72 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7407 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 19382 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 74707 # number of demand (read+write) hits +system.l2c.demand_hits::total 195533 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 44 # number of overall hits +system.l2c.overall_hits::cpu0.inst 4746 # number of overall hits +system.l2c.overall_hits::cpu0.data 16687 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 72204 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 168 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 72 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7407 # number of overall hits +system.l2c.overall_hits::cpu1.data 19382 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 74707 # number of overall hits +system.l2c.overall_hits::total 195533 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 1057 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 3257 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 71979 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 1063 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 3259 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1095 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4649 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84207 # number of ReadReq misses -system.l2c.ReadReq_misses::total 166259 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7810 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5551 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13361 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1270 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1186 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2456 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 3938 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5122 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 9060 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 1104 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4621 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq misses +system.l2c.ReadReq_misses::total 166173 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 7830 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5610 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13440 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1272 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1187 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2459 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 3945 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5092 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 9037 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 1057 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 7195 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 71979 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 1063 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 7204 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1095 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9771 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 84207 # number of demand (read+write) misses -system.l2c.demand_misses::total 175319 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1104 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9713 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) misses +system.l2c.demand_misses::total 175210 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 1057 # number of overall misses -system.l2c.overall_misses::cpu0.data 7195 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 71979 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 1063 # number of overall misses +system.l2c.overall_misses::cpu0.data 7204 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 72015 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1095 # number of overall misses -system.l2c.overall_misses::cpu1.data 9771 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 84207 # number of overall misses -system.l2c.overall_misses::total 175319 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 219750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 271250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 87748250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 250538998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 662750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 96997750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 362821248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17132951668 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11966992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 6050751 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 18017743 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 511478 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4288817 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4800295 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 296071197 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 384274697 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 680345894 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 219750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 271250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 87748250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 546610195 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 662750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 96997750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 747095945 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17813297562 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 219750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 271250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 87748250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 546610195 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6879023630 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 662750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 96997750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 747095945 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9454668042 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17813297562 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 128 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 44 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 5795 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 18281 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144098 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 64 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 8447 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 21003 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 159318 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 357368 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 213952 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 213952 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10892 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 7663 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18555 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1359 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1425 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2784 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 5814 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 7864 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 13678 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 128 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 44 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 5795 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 24095 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144098 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 64 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8447 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 28867 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 159318 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 371046 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 128 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 44 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 5795 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 24095 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144098 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 64 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8447 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 28867 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 159318 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 371046 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.090909 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.182399 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.178163 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.129632 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.221349 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.465232 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.717040 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.724390 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.720075 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934511 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.832281 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.882184 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.677331 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.651322 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.662378 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.090909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.182399 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.298610 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.129632 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.338483 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.472499 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.023438 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.090909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.182399 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.298610 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.042105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.129632 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.338483 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.528547 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.472499 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 73250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 67812.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83016.319773 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 76923.241633 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95569.869406 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88582.420091 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78042.858249 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 103049.769745 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1532.265301 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1090.029004 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1348.532520 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 402.738583 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3616.203204 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1954.517508 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 75183.137887 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75024.345373 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 75093.365784 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 73250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 67812.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 83016.319773 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 75970.840167 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95569.869406 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 88582.420091 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76460.540886 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 101605.060273 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 73250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 67812.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 83016.319773 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 75970.840167 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95569.869406 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82843.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 88582.420091 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76460.540886 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112278.884677 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 101605.060273 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 124 # number of cycles access was blocked +system.l2c.overall_misses::cpu1.inst 1104 # number of overall misses +system.l2c.overall_misses::cpu1.data 9713 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 84097 # number of overall misses +system.l2c.overall_misses::total 175210 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 88517249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 251848999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 744500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 96486500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 359268498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17143743646 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 12214974 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 6369731 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 18584705 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 508980 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4358314 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4867294 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 294129193 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 380271953 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 674401146 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 195250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 88517249 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 545978192 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 744500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 96486500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 739540451 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17818144792 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 195250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 182000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 88517249 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 545978192 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 744500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 96486500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 739540451 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17818144792 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 119 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 47 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 5809 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 18143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144219 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 176 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 72 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 8511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 21257 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 158804 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 357157 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 213987 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 213987 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10937 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 7655 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18592 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1362 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1432 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2794 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 5748 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 7838 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 13586 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 119 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 47 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 5809 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 23891 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144219 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 72 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8511 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 29095 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 158804 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 370743 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 119 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 47 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 5809 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 23891 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144219 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 176 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 72 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8511 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 29095 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 158804 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 370743 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.063830 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.182992 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.179629 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.129714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.217387 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.465266 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.715918 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.732854 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.722892 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.933921 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828911 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.880100 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.686326 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.649656 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.665170 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.063830 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.182992 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.301536 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.129714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.333837 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.472592 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.063830 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.182992 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.301536 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.129714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.333837 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.472592 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83271.165569 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 77277.999079 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87397.192029 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77746.915819 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 103168.045627 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1560.022222 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1135.424421 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1382.790551 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 400.141509 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3671.705139 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1979.379423 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74557.463371 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74680.273566 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 74626.662167 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 101695.935118 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 101695.935118 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 369 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 36.900000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 68649 # number of writebacks -system.l2c.writebacks::total 68649 # number of writebacks +system.l2c.writebacks::writebacks 68618 # number of writebacks +system.l2c.writebacks::total 68618 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 1057 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 3257 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 71979 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 1063 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 3259 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1095 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4649 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84207 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 166259 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 7810 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5551 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 13361 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1270 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1186 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2456 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 3938 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5122 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 9060 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1104 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4621 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 166173 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 7830 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5610 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 13440 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1272 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1187 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2459 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 3945 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5092 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 9037 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 1057 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 7195 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 71979 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 1063 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 7204 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1095 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9771 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84207 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 175319 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1104 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9713 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 175210 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 1057 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 7195 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 71979 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 1063 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 7204 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1095 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9771 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84207 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 175319 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 182750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 221250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 74667250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 209834998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5986714130 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 563750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 83479750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 304868248 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8418931550 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15079463676 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 78934077 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56101003 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 135035080 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12761264 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11939675 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 24700939 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 246811801 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 319899303 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 566711104 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 182750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 221250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 74667250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 456646799 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5986714130 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 563750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 83479750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 624767551 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8418931550 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15646174780 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 182750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 221250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 74667250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 456646799 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5986714130 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 563750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 83479750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 624767551 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8418931550 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15646174780 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 177326500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343963753 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3540500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154954228993 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167479059746 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076373001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16024726896 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17101099897 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 177326500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420336754 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3540500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978955889 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184580159643 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.178163 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.221349 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.465232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.717040 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.724390 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.720075 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934511 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.832281 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.882184 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.677331 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.651322 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.662378 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.298610 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.338483 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.472499 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.023438 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.090909 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182399 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.298610 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499514 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.042105 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129632 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.338483 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.528547 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.472499 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64425.851397 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65577.166703 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 90698.630907 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10106.796031 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.467844 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10106.659681 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10048.239370 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.179595 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10057.385586 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62674.403504 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62455.935767 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62550.894481 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63467.241001 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63941.004094 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 89244.033904 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60916.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 55312.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70640.728477 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63467.241001 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83173.066172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70468.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76237.214612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63941.004094 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99978.998777 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 89244.033904 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 1104 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9713 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 175210 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 145000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 75361749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 211101499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 645000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 82874000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 301675998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15091446656 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 79003615 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56662566 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 135666181 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12832754 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11966179 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 24798933 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 244772807 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 316260047 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 561032854 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 75361749 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 455874306 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 645000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 82874000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 617936045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 15652479510 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 75361749 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 455874306 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 645000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 82874000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 617936045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 15652479510 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 178129250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343853503 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3278250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154953535743 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167478796746 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076363997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16025248776 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17101612773 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -870,48 +887,48 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 1651156 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1651155 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769198 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769198 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 213952 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 63434 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 23959 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 87393 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 23242 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 23242 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760832 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337498 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5098330 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18164043 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24784826 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 42948869 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 177697 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 784039 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 177868 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 784039 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 784039 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2614289788 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1150553389 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2660791344 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16322919 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322919 # Transaction distribution +system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution system.iobus.trans_dist::WriteReq 8084 # Transaction distribution system.iobus.trans_dist::WriteResp 8084 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8838 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -933,12 +950,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32662006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17676 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -960,13 +977,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2392689 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 123503217 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4425000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1012,19 +1029,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376290000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38179589169 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6443222 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4514499 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 302125 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3729781 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2837348 # Number of BTB hits +system.cpu0.branchPred.lookups 6445077 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.072777 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 778118 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 15176 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1048,25 +1065,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6735842 # DTB read hits -system.cpu0.dtb.read_misses 20815 # DTB read misses -system.cpu0.dtb.write_hits 5107742 # DTB write hits -system.cpu0.dtb.write_misses 5078 # DTB write misses +system.cpu0.dtb.read_hits 6738270 # DTB read hits +system.cpu0.dtb.read_misses 20792 # DTB read misses +system.cpu0.dtb.write_hits 5108254 # DTB write hits +system.cpu0.dtb.write_misses 4938 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 367 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6756657 # DTB read accesses -system.cpu0.dtb.write_accesses 5112820 # DTB write accesses +system.cpu0.dtb.read_accesses 6759062 # DTB read accesses +system.cpu0.dtb.write_accesses 5113192 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11843584 # DTB hits -system.cpu0.dtb.misses 25893 # DTB misses -system.cpu0.dtb.accesses 11869477 # DTB accesses +system.cpu0.dtb.hits 11846524 # DTB hits +system.cpu0.dtb.misses 25730 # DTB misses +system.cpu0.dtb.accesses 11872254 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1088,8 +1105,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 11247992 # ITB inst hits -system.cpu0.itb.inst_misses 5846 # ITB inst misses +system.cpu0.itb.inst_hits 11251934 # ITB inst hits +system.cpu0.itb.inst_misses 5844 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1098,143 +1115,143 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1213 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2388 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 11253838 # ITB inst accesses -system.cpu0.itb.hits 11247992 # DTB hits -system.cpu0.itb.misses 5846 # DTB misses -system.cpu0.itb.accesses 11253838 # DTB accesses -system.cpu0.numCycles 70572029 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses +system.cpu0.itb.hits 11251934 # DTB hits +system.cpu0.itb.misses 5844 # DTB misses +system.cpu0.itb.accesses 11257778 # DTB accesses +system.cpu0.numCycles 70547986 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 4765934 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 34354024 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6443222 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3615466 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61748976 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 827418 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 76155 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 31280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 103338 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 2296149 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 8939 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 11248771 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 69018 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1645 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 69444480 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.597050 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.081482 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 50353589 72.51% 72.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 6606705 9.51% 82.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2597434 3.74% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 9886752 14.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 69444480 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.091300 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.486794 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 6420501 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48533578 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12241748 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1929473 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 319180 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 871648 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 96104 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 34913571 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 1200749 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 319180 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 8404067 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 22318095 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11023940 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 12127048 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 15252150 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 33557627 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 347095 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 4724247 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2950612 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 10590884 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 2755476 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 34851569 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 154470161 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 39932563 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3839 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30129647 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4721913 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 454205 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 374005 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4735093 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6116299 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5560853 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 585692 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 726458 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 32313533 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 795864 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 32787954 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 169648 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 3622039 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 7620869 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 145783 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 69444480 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.472146 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.871579 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 50308599 72.44% 72.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9186806 13.23% 85.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 6613722 9.52% 95.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2968134 4.27% 99.47% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 366793 0.53% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 426 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 69444480 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2914015 33.72% 33.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 370 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 2945355 34.08% 67.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 2781781 32.19% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14545 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 20237485 61.72% 61.77% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42714 0.13% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued @@ -1258,101 +1275,101 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7055748 21.52% 83.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5436782 16.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 32787954 # Type of FU issued -system.cpu0.iq.rate 0.464603 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8641521 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.263558 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 143819965 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 36733067 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 31072945 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11591 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued +system.cpu0.iq.rate 0.464855 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 41407644 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7286 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 165926 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 774444 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 6361 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 333599 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1087774 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 167955 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 319180 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7637637 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6671195 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 33211836 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6116299 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5560853 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 485055 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 10847 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6650997 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 6361 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 101358 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 128388 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 229746 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 32419905 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 6900946 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 342549 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102439 # number of nop insts executed -system.cpu0.iew.exec_refs 12280176 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4698919 # Number of branches executed -system.cpu0.iew.exec_stores 5379230 # Number of stores executed -system.cpu0.iew.exec_rate 0.459387 # Inst execution rate -system.cpu0.iew.wb_sent 32226620 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 31076783 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15728135 # num instructions producing a value -system.cpu0.iew.wb_consumers 27168028 # num instructions consuming a value +system.cpu0.iew.exec_nop 102446 # number of nop insts executed +system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4700114 # Number of branches executed +system.cpu0.iew.exec_stores 5379801 # Number of stores executed +system.cpu0.iew.exec_rate 0.459648 # Inst execution rate +system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15739944 # num instructions producing a value +system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.440356 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.578921 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 3251168 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 650081 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 207596 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 68809072 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.427174 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.181510 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 54941660 79.85% 79.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7926001 11.52% 91.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2553754 3.71% 95.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1118993 1.63% 96.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 777653 1.13% 97.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 424728 0.62% 98.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 260082 0.38% 98.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241415 0.35% 99.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 564786 0.82% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 68809072 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24063345 # Number of instructions committed -system.cpu0.commit.committedOps 29393425 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24068410 # Number of instructions committed +system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10569108 # Number of memory references committed -system.cpu0.commit.loads 5341854 # Number of loads committed -system.cpu0.commit.membars 231843 # Number of memory barriers committed -system.cpu0.commit.branches 4350514 # Number of branches committed +system.cpu0.commit.refs 10570507 # Number of memory references committed +system.cpu0.commit.loads 5342633 # Number of loads committed +system.cpu0.commit.membars 231974 # Number of memory barriers committed +system.cpu0.commit.branches 4351471 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 25739481 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499600 # Number of function calls committed. +system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499778 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 18783880 63.91% 63.91% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39757 0.14% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction @@ -1376,523 +1393,523 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 5341854 18.17% 82.22% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5227254 17.78% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 29393425 # Class of committed instruction -system.cpu0.commit.bw_lim_events 564786 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction +system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 100015321 # The number of ROB reads -system.cpu0.rob.rob_writes 65887471 # The number of ROB writes -system.cpu0.timesIdled 89304 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1127549 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5145313600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23982603 # Number of Instructions Simulated -system.cpu0.committedOps 29312683 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.942634 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.942634 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.339832 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.339832 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 37149809 # number of integer regfile reads -system.cpu0.int_regfile_writes 18849024 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads +system.cpu0.rob.rob_reads 99997744 # The number of ROB reads +system.cpu0.rob.rob_writes 65895627 # The number of ROB writes +system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23987668 # Number of Instructions Simulated +system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads +system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads system.cpu0.fp_regfile_writes 840 # number of floating regfile writes -system.cpu0.cc_regfile_reads 113743711 # number of cc regfile reads -system.cpu0.cc_regfile_writes 12811786 # number of cc regfile writes -system.cpu0.misc_regfile_reads 112044501 # number of misc regfile reads -system.cpu0.misc_regfile_writes 501943 # number of misc regfile writes -system.cpu0.toL2Bus.trans_dist::ReadReq 900890 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 693810 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 10816 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 10816 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 228377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 268020 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 56323 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24618 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 62769 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 133666 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 124628 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651345 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1224806 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16460 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46873 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 1939484 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20679616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38657675 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 81552 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 59446187 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 639427 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 1524092 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.371625 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.483239 # Request fanout histogram +system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads +system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes +system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads +system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 640729 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 957702 62.84% 62.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 566390 37.16% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 1524092 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 762289909 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 71149999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 488209636 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 613845688 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 9628741 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 26509702 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 321808 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.716294 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10911549 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 322320 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.853155 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6537059000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.716294 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999446 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999446 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 322116 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 22813002 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 22813002 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 10911549 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10911549 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 10911549 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10911549 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 10911549 # number of overall hits -system.cpu0.icache.overall_hits::total 10911549 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 333786 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 333786 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 333786 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 333786 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 333786 # number of overall misses -system.cpu0.icache.overall_misses::total 333786 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863204339 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 2863204339 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 2863204339 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 2863204339 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 2863204339 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 2863204339 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 11245335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11245335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 11245335 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11245335 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 11245335 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11245335 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029682 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029682 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029682 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029682 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029682 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029682 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8577.964142 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8577.964142 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8577.964142 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8577.964142 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8577.964142 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8577.964142 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 178990 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 306 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 22304 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10915164 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 10915164 # number of overall hits +system.cpu0.icache.overall_hits::total 10915164 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 334091 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 334091 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 334091 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 334091 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 334091 # number of overall misses +system.cpu0.icache.overall_misses::total 334091 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863305358 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 2863305358 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 2863305358 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029699 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029699 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029699 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029699 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029699 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8570.435474 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8570.435474 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8570.435474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8570.435474 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8.025018 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 61.200000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11454 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 11454 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 11454 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 11454 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 11454 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 11454 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322332 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 322332 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 322332 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 322332 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 322332 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 322332 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310843125 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310843125 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310843125 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 2310843125 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310843125 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 2310843125 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 271667749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 271667749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 271667749 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 271667749 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028664 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028664 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028664 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028664 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7169.139660 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7169.139660 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7169.139660 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7169.139660 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 272886999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 272886999 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 272886999 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028681 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028681 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028681 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529022 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247159 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2982180 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86515 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16169 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 196999 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 262402 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 165246 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15954.893231 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 747835 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 181374 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.123165 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 4999584000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4776.473696 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.474561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.133588 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 734.105729 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1523.434218 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8907.271439 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.291533 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000761 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000069 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044806 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092983 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543657 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.973809 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7357 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8758 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 33 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 96 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1021 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5218 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 989 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 165160 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15951.411231 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 747099 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 181321 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.120311 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 4999805500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4772.372752 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.637155 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.084033 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8811 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1027 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 943 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 470 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1658 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5972 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 621 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.449036 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.534546 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 15532089 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 15532089 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 20030 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6663 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314349 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 163060 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 504102 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 228376 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 228376 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6687 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 6687 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 642 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 642 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95716 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 95716 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 20030 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6663 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 314349 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 258776 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 599818 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 20030 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6663 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 314349 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 258776 # number of overall hits -system.cpu0.l2cache.overall_hits::total 599818 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 358 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7928 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 50645 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 59104 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19619 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 19619 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10843 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 10843 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23636 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 23636 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 358 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 7928 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 74281 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 82740 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 358 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 7928 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 74281 # number of overall misses -system.cpu0.l2cache.overall_misses::total 82740 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7810749 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3821249 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 257932474 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1300025301 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1569589773 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 308952932 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 308952932 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 211975648 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 211975648 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 651000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 651000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 895614551 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 895614551 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7810749 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3821249 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 257932474 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 2195639852 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 2465204324 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7810749 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3821249 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 257932474 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 2195639852 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 2465204324 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20388 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6836 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322277 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213705 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 563206 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 228377 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 228377 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26306 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26306 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11485 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 11485 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119352 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 119352 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20388 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6836 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 322277 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 333057 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 682558 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20388 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6836 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 322277 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 333057 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 682558 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025307 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024600 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.236986 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.104942 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745799 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745799 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.944101 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.944101 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6017 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.447876 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.537781 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 15517001 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 15517001 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 19658 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6554 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314769 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 162769 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 503750 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 228045 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 228045 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6593 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 6593 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 622 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 622 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95529 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 95529 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 19658 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6554 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 314769 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 258298 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 599279 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 19658 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6554 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 314769 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 258298 # number of overall hits +system.cpu0.l2cache.overall_hits::total 599279 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 345 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7801 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 50805 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 59122 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19680 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 19680 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10856 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 10856 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23597 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 23597 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 345 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 7801 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 74402 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 82719 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 345 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 7801 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 74402 # number of overall misses +system.cpu0.l2cache.overall_misses::total 82719 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7498249 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3753000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 255179729 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1303745054 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1570176032 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 310997961 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 310997961 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 212766148 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 212766148 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 609000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 609000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 893661798 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 893661798 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7498249 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3753000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 255179729 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 2197406852 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 2463837830 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7498249 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3753000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 255179729 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 2197406852 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 2463837830 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20003 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6725 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322570 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213574 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 562872 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 228050 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 228050 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11478 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 11478 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119126 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 119126 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20003 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6725 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 322570 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 332700 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 681998 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20003 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6725 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 322570 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 332700 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 681998 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025428 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024184 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.237880 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.105036 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000022 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000022 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.749058 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.945809 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.945809 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198036 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198036 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025307 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024600 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223028 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.121220 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017559 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025307 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024600 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223028 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.121220 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22088.144509 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32534.368567 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25669.371132 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26556.405201 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15747.639125 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15747.639125 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19549.538689 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19549.538689 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 325500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 325500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37891.967803 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37891.967803 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22088.144509 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32534.368567 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29558.566147 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 29794.589364 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21817.734637 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22088.144509 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32534.368567 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29558.566147 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 29794.589364 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 7107 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198084 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198084 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025428 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024184 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223631 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.121289 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025428 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024184 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223631 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.121289 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21947.368421 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32711.156134 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26558.236054 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15802.741921 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19598.945099 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 609000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 609000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37871.839556 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37871.839556 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 29785.633651 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 29785.633651 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 4781 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 273 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 266 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26.032967 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 17.973684 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 105341 # number of writebacks -system.cpu0.l2cache.writebacks::total 105341 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 105131 # number of writebacks +system.cpu0.l2cache.writebacks::total 105131 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1954 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 952 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 2908 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 913 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 913 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1845 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 997 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 936 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 936 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1954 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1865 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3821 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1845 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1933 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3780 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1954 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1865 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3821 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 357 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 172 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5974 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49693 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 56196 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 196993 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 196993 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19619 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19619 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10843 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10843 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22723 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 22723 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 357 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 172 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5974 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72416 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 78919 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 357 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 172 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5974 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72416 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 196993 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 275912 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2604249 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 180571011 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 937505841 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1125907352 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8176644028 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8176644028 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 352932260 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 352932260 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158150720 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158150720 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 518000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 518000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 604135928 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 604135928 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2604249 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 180571011 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541641769 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 1730043280 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5226251 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2604249 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 180571011 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541641769 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8176644028 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 9906687308 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243146000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865472761 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14108618761 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262025986 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262025986 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243146000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127498747 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15370644747 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.232531 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099779 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1845 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1933 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3780 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 170 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5956 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49808 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 56278 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 198779 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19680 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19680 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10856 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10856 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22661 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 22661 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 344 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 170 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5956 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72469 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 78939 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 344 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 170 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5956 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72469 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 277718 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2550500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 181100759 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 940424592 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1129080602 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8151036272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 354005766 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158485722 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 601346170 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2550500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 181100759 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541770762 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 1730426772 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2550500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745799 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745799 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.944101 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.944101 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190386 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190386 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115622 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017510 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025161 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018537 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217428 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.404232 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18865.953776 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20035.364652 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41507.282127 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17989.309343 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17989.309343 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14585.513234 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14585.513234 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 259000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 259000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26586.979184 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26586.979184 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.758765 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14639.358543 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15140.982558 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30226.148477 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21288.689917 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41507.282127 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35905.242643 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1902,192 +1919,192 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 297776 # number of replacements -system.cpu0.dcache.tags.tagsinuse 472.735885 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9026842 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 298288 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.262169 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 297335 # number of replacements +system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 472.735885 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.923312 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.923312 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 20884973 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 20884973 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4735429 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4735429 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3898152 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3898152 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45417 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 45417 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135242 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 135242 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133435 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 133435 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8633581 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8633581 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8678998 # number of overall hits -system.cpu0.dcache.overall_hits::total 8678998 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 322548 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 322548 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 908505 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 908505 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74956 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 74956 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10777 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10777 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11487 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11487 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1231053 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1231053 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1306009 # number of overall misses -system.cpu0.dcache.overall_misses::total 1306009 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3690700649 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3690700649 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13101093488 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 13101093488 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182297251 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 182297251 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273170236 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 273170236 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 708000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 708000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 16791794137 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16791794137 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 16791794137 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16791794137 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5057977 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5057977 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4806657 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4806657 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120373 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 120373 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146019 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 146019 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144922 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144922 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9864634 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9864634 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9985007 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9985007 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063770 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063770 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.189010 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.189010 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.622698 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.622698 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073805 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073805 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079263 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079263 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124795 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.124795 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130797 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.130797 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11442.329976 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11442.329976 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14420.496847 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14420.496847 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16915.398627 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16915.398627 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23780.816227 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23780.816227 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits +system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses +system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273467244 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 660000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 16742760911 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13640.187821 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13640.187821 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12857.334166 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12857.334166 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 95 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1898059 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 12 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 100067 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.916667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18.967882 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 228377 # number of writebacks -system.cpu0.dcache.writebacks::total 228377 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162400 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 162400 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 764106 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 764106 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1174 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1174 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 926506 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 926506 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 926506 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 926506 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160148 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 160148 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144399 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 144399 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44137 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 44137 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9603 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9603 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11487 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11487 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 304547 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 304547 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 348684 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 348684 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1658754828 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1658754828 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2155336775 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2155336775 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 705733496 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 705733496 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 146716749 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146716749 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 248972764 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 248972764 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 670000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 670000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3814091603 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 3814091603 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4519825099 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4519825099 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541509738 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541509738 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345509995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345509995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15887019733 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15887019733 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031662 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031662 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030041 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030041 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366669 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366669 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065765 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065765 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079263 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079263 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030873 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030873 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034921 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.034921 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10357.636861 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10357.636861 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14926.258319 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14926.258319 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15989.611800 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15989.611800 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15278.220244 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15278.220244 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21674.306956 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21674.306956 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks +system.cpu0.dcache.writebacks::total 228050 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12523.819322 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12523.819322 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12962.525091 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12962.525091 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -2095,15 +2112,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9152424 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6787583 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 422463 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5824908 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4287107 # Number of BTB hits +system.cpu1.branchPred.lookups 9149866 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.599566 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 928023 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 19411 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2127,25 +2144,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25102485 # DTB read hits -system.cpu1.dtb.read_misses 30131 # DTB read misses -system.cpu1.dtb.write_hits 6842228 # DTB write hits -system.cpu1.dtb.write_misses 6831 # DTB write misses +system.cpu1.dtb.read_hits 25102636 # DTB read hits +system.cpu1.dtb.read_misses 30137 # DTB read misses +system.cpu1.dtb.write_hits 6841685 # DTB write hits +system.cpu1.dtb.write_misses 6769 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1185 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 216 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 721 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25132616 # DTB read accesses -system.cpu1.dtb.write_accesses 6849059 # DTB write accesses +system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25132773 # DTB read accesses +system.cpu1.dtb.write_accesses 6848454 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31944713 # DTB hits -system.cpu1.dtb.misses 36962 # DTB misses -system.cpu1.dtb.accesses 31981675 # DTB accesses +system.cpu1.dtb.hits 31944321 # DTB hits +system.cpu1.dtb.misses 36906 # DTB misses +system.cpu1.dtb.accesses 31981227 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2167,8 +2184,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 16807994 # ITB inst hits -system.cpu1.itb.inst_misses 6151 # ITB inst misses +system.cpu1.itb.inst_hits 16803682 # ITB inst hits +system.cpu1.itb.inst_misses 6173 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2177,108 +2194,108 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1324 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2317 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16814145 # ITB inst accesses -system.cpu1.itb.hits 16807994 # DTB hits -system.cpu1.itb.misses 6151 # DTB misses -system.cpu1.itb.accesses 16814145 # DTB accesses -system.cpu1.numCycles 436928341 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses +system.cpu1.itb.hits 16803682 # DTB hits +system.cpu1.itb.misses 6173 # DTB misses +system.cpu1.itb.accesses 16809855 # DTB accesses +system.cpu1.numCycles 436917069 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7782698 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 51596763 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9152424 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5215130 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 424941710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 1120750 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78139 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 42302 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 114025 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 2394073 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 15193 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 16805493 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 110231 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1848 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 435928515 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.141220 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 0.582447 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 407583971 93.50% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 9418988 2.16% 95.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4633784 1.06% 96.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 14291772 3.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 435928515 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.020947 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.118090 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 9900364 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 404223223 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 17614980 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3776395 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 413553 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1053442 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 149008 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53092008 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1695759 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 413553 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13042723 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 210396712 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 23472613 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 17904868 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 170698046 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51368721 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 446510 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 60461955 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 44486739 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 161543607 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 5691516 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 54461405 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 239791189 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 64663371 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6318 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 48773612 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 5687793 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 755066 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 650305 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9515083 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9672416 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7398818 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 540509 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 901013 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 49760651 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1064041 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 65151517 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 226257 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 4310331 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 9274124 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 164398 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 435928515 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.149455 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.502708 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 391744994 89.86% 89.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 28933513 6.64% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 10221564 2.34% 98.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4339119 1.00% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 689106 0.16% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 219 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 435928515 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4423159 17.50% 17.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available @@ -2307,130 +2324,130 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 17781771 70.36% 87.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3065221 12.13% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14259 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32355462 49.66% 49.68% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 60215 0.09% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 25491374 39.13% 88.91% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7228505 11.09% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 65151517 # Type of FU issued -system.cpu1.iq.rate 0.149113 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 25270842 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.387878 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 591706993 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 55136909 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 48344835 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 21655 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8050 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6779 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 90394215 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 13885 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 164856 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued +system.cpu1.iq.rate 0.149104 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 923073 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 694 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9989 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 405691 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16016634 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 154537 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 413553 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 90101438 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 101307050 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 50914326 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9672416 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7398818 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 775912 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 15376 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 101229610 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9989 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 133261 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 167875 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 301136 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 64660152 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25297767 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 454579 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 89634 # number of nop insts executed -system.cpu1.iew.exec_refs 32444465 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6847399 # Number of branches executed -system.cpu1.iew.exec_stores 7146698 # Number of stores executed -system.cpu1.iew.exec_rate 0.147988 # Inst execution rate -system.cpu1.iew.wb_sent 64445126 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 48351614 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25812211 # num instructions producing a value -system.cpu1.iew.wb_consumers 39463324 # num instructions consuming a value +system.cpu1.iew.exec_nop 89541 # number of nop insts executed +system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6846575 # Number of branches executed +system.cpu1.iew.exec_stores 7146063 # Number of stores executed +system.cpu1.iew.exec_rate 0.147981 # Inst execution rate +system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25811466 # num instructions producing a value +system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.110663 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.654081 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3859606 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899643 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 275641 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 435147565 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.106509 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.626853 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 413414233 95.01% 95.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12938839 2.97% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 3517188 0.81% 98.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1361627 0.31% 99.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1314784 0.30% 99.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 785099 0.18% 99.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 557735 0.13% 99.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 306330 0.07% 99.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 951730 0.22% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 435147565 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38848557 # Number of instructions committed -system.cpu1.commit.committedOps 46347287 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38843249 # Number of instructions committed +system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 15742470 # Number of memory references committed -system.cpu1.commit.loads 8749343 # Number of loads committed -system.cpu1.commit.membars 195410 # Number of memory barriers committed -system.cpu1.commit.branches 6420016 # Number of branches committed +system.cpu1.commit.refs 15740654 # Number of memory references committed +system.cpu1.commit.loads 8748353 # Number of loads committed +system.cpu1.commit.membars 195273 # Number of memory barriers committed +system.cpu1.commit.branches 6419002 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 41063846 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553629 # Number of function calls committed. +system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553431 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 30544997 65.90% 65.90% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction @@ -2459,499 +2476,511 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 8749343 18.88% 84.91% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6993127 15.09% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 46347287 # Class of committed instruction -system.cpu1.commit.bw_lim_events 951730 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction +system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 483333475 # The number of ROB reads -system.cpu1.rob.rob_writes 101149089 # The number of ROB writes -system.cpu1.timesIdled 117660 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 999826 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4778389305 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38778918 # Number of Instructions Simulated -system.cpu1.committedOps 46277648 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 11.267162 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 11.267162 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.088753 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.088753 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 76052012 # number of integer regfile reads -system.cpu1.int_regfile_writes 30999334 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5023 # number of floating regfile reads +system.cpu1.rob.rob_reads 483317632 # The number of ROB reads +system.cpu1.rob.rob_writes 101136219 # The number of ROB writes +system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38773610 # Number of Instructions Simulated +system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads +system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes -system.cpu1.cc_regfile_reads 220747200 # number of cc regfile reads -system.cpu1.cc_regfile_writes 19380007 # number of cc regfile writes -system.cpu1.misc_regfile_reads 519889697 # number of misc regfile reads -system.cpu1.misc_regfile_writes 723831 # number of misc regfile writes -system.cpu1.toL2Bus.trans_dist::ReadReq 2172389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1977860 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 758382 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 758382 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 290106 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 274324 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 56101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 54306 # Transaction distribution +system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads +system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes +system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 157043 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 149501 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1094031 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4942031 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17483 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65557 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 6119102 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34999952 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51368490 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29544 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119816 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86517802 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 597240 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1872325 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.291637 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.454516 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 595717 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1326285 70.84% 70.84% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 546040 29.16% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1872325 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2993294877 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 46728999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 821422427 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 2122306221 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 10104485 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 36085284 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.icache.tags.replacements 546512 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.931613 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16242826 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 547024 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 29.693077 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73724433000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.931613 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974476 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974476 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 546235 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 34157735 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 34157735 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 16242826 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16242826 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16242826 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16242826 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16242826 # number of overall hits -system.cpu1.icache.overall_hits::total 16242826 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 562520 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 562520 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 562520 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 562520 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 562520 # number of overall misses -system.cpu1.icache.overall_misses::total 562520 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4745618430 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4745618430 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4745618430 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4745618430 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4745618430 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4745618430 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16805346 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16805346 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16805346 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16805346 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16805346 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16805346 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033473 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033473 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033473 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033473 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033473 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033473 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.355027 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.355027 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8436.355027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.355027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8436.355027 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 306365 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 40679 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits +system.cpu1.icache.overall_hits::total 16238797 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses +system.cpu1.icache.overall_misses::total 562244 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.531281 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 1 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15477 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 15477 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 15477 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 15477 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 15477 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 15477 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 547043 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 547043 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 547043 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 547043 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 547043 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 547043 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3841218666 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3841218666 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3841218666 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3841218666 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3841218666 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3841218666 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5375499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5375499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5375499 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5375499 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032552 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.032552 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032552 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.032552 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7021.785611 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7021.785611 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7021.785611 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7021.785611 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5064887 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 196421 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4608715 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49903 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5063185 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 195793 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4609637 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49643 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8275 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 201573 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 431249 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8256 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 199856 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 430863 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 190012 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15761.494789 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1049012 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 205401 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.107142 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2533064784000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4779.201022 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.066276 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030051 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 839.580286 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2141.602652 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7985.014503 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.291699 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000859 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.051244 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130713 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.487367 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.962005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8393 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6988 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2144 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2546 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3703 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2618 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1697 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2673 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.512268 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426514 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21490349 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21490349 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29593 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7243 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535438 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 196668 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 768942 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 290105 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 290105 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2163 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2163 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1236 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1236 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122721 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 122721 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29593 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7243 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 535438 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 319389 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 891663 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29593 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7243 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 535438 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 319389 # number of overall hits -system.cpu1.l2cache.overall_hits::total 891663 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 361 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 143 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11420 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 60562 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 72486 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20521 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 20521 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13163 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 13163 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25394 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 25394 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 361 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 143 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 11420 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 85956 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 97880 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 361 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 143 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 11420 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 85956 # number of overall misses -system.cpu1.l2cache.overall_misses::total 97880 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8348750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3077500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344518477 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610493915 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1966438642 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 355504452 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 355504452 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267510078 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267510078 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1281000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1281000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1148633604 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1148633604 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8348750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3077500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344518477 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2759127519 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3115072246 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8348750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3077500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344518477 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2759127519 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3115072246 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29954 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7386 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546858 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257230 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 841428 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 290106 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 290106 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22684 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 22684 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14399 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 14399 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148115 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 148115 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29954 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7386 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 546858 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 405345 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 989543 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29954 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7386 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 546858 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 405345 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 989543 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019361 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020883 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235439 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.086146 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.904646 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.904646 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.914161 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.914161 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171448 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171448 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019361 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020883 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212056 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.098914 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012052 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019361 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020883 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212056 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.098914 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21520.979021 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30167.992732 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26592.482332 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27128.530227 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17323.934116 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17323.934116 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20322.880650 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20322.880650 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45232.480271 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45232.480271 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21520.979021 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30167.992732 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32099.301026 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31825.421394 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23126.731302 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21520.979021 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30167.992732 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32099.301026 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31825.421394 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 8171 # number of cycles access was blocked +system.cpu1.l2cache.tags.replacements 189917 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15760.362755 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1051721 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 205349 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.121627 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2533057390500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4796.141133 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.055492 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.249384 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 825.564654 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2172.411955 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7947.940138 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.292733 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001041 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000076 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.050388 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132594 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485104 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.961936 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.514404 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426880 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21502320 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21502320 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29274 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7085 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535244 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 196892 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 768495 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 291031 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 291031 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2209 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2209 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1205 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1205 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122716 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 122716 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29274 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7085 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 535244 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 319608 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 891211 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29274 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7085 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 535244 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 319608 # number of overall hits +system.cpu1.l2cache.overall_hits::total 891211 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 364 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 158 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11361 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 60780 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 72663 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20588 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 20588 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13188 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 13188 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25387 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 25387 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 364 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 158 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 11361 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 86167 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 98050 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 364 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 158 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 11361 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 86167 # number of overall misses +system.cpu1.l2cache.overall_misses::total 98050 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8462000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3365000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344449975 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612650155 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1968927130 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 357562229 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 357562229 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267838079 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267838079 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1192000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1192000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1149303620 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1149303620 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8462000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3365000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344449975 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2761953775 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3118230750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8462000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3365000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344449975 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2761953775 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3118230750 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29638 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7243 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148103 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 148103 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29638 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7243 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 546605 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 405775 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 989261 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29638 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.903101 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.903101 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.916279 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.916279 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171414 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171414 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.021814 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020785 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212352 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.099114 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.021814 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020785 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212352 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.099114 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21297.468354 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45271.344389 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45271.344389 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31802.455380 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31802.455380 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 8115 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 441 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 442 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.528345 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.359729 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 108610 # number of writebacks -system.cpu1.l2cache.writebacks::total 108610 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 108849 # number of writebacks +system.cpu1.l2cache.writebacks::total 108849 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2944 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 155 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 3100 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1588 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 1588 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2808 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 143 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 2953 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1573 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 1573 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2944 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1743 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 4688 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2808 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1716 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 4526 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2944 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1743 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 4688 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 360 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 143 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8476 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60407 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 69386 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 201557 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 201557 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20521 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20521 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13163 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13163 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23806 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 23806 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 360 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 143 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8476 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84213 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 93192 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 360 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 143 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8476 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84213 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 201557 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 294749 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2076500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 233530753 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1183485205 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1424904708 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10818711595 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10818711595 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 343673223 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 343673223 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188113563 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188113563 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1071000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1071000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 694199615 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 694199615 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2076500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 233530753 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1877684820 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2119104323 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5812250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2076500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 233530753 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1877684820 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10818711595 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 12937815918 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4830750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174824022755 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174828853505 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29482934435 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29482934435 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4830750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204306957190 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204311787940 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.234837 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082462 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2808 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1716 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 4526 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 363 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 157 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8553 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60637 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 69710 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 199848 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20588 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20588 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13188 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13188 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23814 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 23814 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 363 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 157 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8553 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84451 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 93524 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 363 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 157 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8553 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84451 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 293372 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2254500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 234181256 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1184058953 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1426398709 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2254500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 234181256 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1874848035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2117187791 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2254500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 234181256 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1874848035 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204307878917 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204312450917 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.235326 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082874 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.904646 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.904646 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.914161 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914161 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160726 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160726 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.207756 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094177 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012018 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019361 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015499 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.207756 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.903101 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.903101 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.916279 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916279 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160794 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160794 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094539 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.297864 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19591.855331 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20535.910818 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.692707 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.692707 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16747.391599 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16747.391599 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14291.085847 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14291.085847 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29160.699614 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29160.699614 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22739.122704 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16145.138889 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14520.979021 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27552.000118 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22296.852267 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.692707 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43894.350508 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22637.908890 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2961,190 +2990,190 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 381157 # number of replacements -system.cpu1.dcache.tags.tagsinuse 482.358158 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12336025 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 381566 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 32.329990 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70967583500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.358158 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942106 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.942106 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 27772556 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 27772556 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7207091 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7207091 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4859664 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4859664 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24710 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 24710 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94182 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 94182 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93506 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 93506 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12066755 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12066755 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12091465 # number of overall hits -system.cpu1.dcache.overall_hits::total 12091465 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 361330 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 361330 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 966559 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 966559 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47195 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 47195 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14954 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14954 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14399 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 14399 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1327889 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1327889 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1375084 # number of overall misses -system.cpu1.dcache.overall_misses::total 1375084 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4284258220 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4284258220 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15637986446 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 15637986446 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254935748 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 254935748 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 331661328 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 331661328 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1371000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1371000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 19922244666 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 19922244666 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 19922244666 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 19922244666 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7568421 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7568421 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5826223 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5826223 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 71905 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 71905 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109136 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 109136 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107905 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107905 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 13394644 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 13394644 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 13466549 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 13466549 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047742 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.047742 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.165898 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.165898 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.656352 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.656352 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137022 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137022 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133441 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133441 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099136 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.099136 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102111 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.102111 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11856.912573 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 11856.912573 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16179.029367 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16179.029367 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17047.997058 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17047.997058 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23033.636225 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23033.636225 # average StoreCondReq miss latency +system.cpu1.dcache.tags.replacements 381661 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940978 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12063851 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12063851 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12088353 # number of overall hits +system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 362275 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 967298 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 967298 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1377109 # number of overall misses +system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5825520 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 72038 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15002.944272 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15002.944272 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14488.020125 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14488.020125 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 5063 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 2164841 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 227 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 93890 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.303965 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 23.057205 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 290106 # number of writebacks -system.cpu1.dcache.writebacks::total 290106 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147611 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 147611 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 796581 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 796581 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1422 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1422 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 944192 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 944192 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 944192 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 944192 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213719 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 213719 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 169978 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 169978 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30150 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 30150 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13532 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13532 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 14399 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 383697 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 383697 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 413847 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 413847 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2234589083 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2234589083 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2566083982 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2566083982 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 631981244 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 631981244 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208947501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208947501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 301752672 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 301752672 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1311000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1311000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4800673065 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4800673065 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5432654309 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5432654309 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183654680990 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183654680990 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50890148887 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50890148887 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234544829877 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234544829877 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028238 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028238 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029175 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029175 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.419303 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.419303 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123992 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123992 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133441 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133441 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028646 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030731 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030731 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10455.734319 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10455.734319 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15096.565332 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15096.565332 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20961.235290 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20961.235290 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15440.991797 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15440.991797 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20956.501979 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20956.501979 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks +system.cpu1.dcache.writebacks::total 291033 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12511.625228 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12511.625228 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13127.204762 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13127.204762 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -3168,18 +3197,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1735774629169 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735774629169 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1735774629169 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42920 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50586 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 8ecc8ed09..c184c0913 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.542157 # Nu sim_ticks 2542156879500 # Number of ticks simulated final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53622 # Simulator instruction rate (inst/s) -host_op_rate 64601 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2260157205 # Simulator tick rate (ticks/s) -host_mem_usage 463148 # Number of bytes of host memory used -host_seconds 1124.77 # Real time elapsed on the host +host_inst_rate 53387 # Simulator instruction rate (inst/s) +host_op_rate 64319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2250271387 # Simulator tick rate (ticks/s) +host_mem_usage 465820 # Number of bytes of host memory used +host_seconds 1129.71 # Real time elapsed on the host sim_insts 60311972 # Number of instructions simulated sim_ops 72661518 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -275,6 +275,24 @@ system.physmem.memoryStateTime::REF 84888180000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3819501000 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3820982760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2084053125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2084861625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 59549568000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 59530130400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 339202080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 347386320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 166041280080 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 166041280080 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 145728636750 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 145839613185 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1397461683000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1397364335250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1775023924035 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1775028589620 # Total energy per rank (pJ) +system.physmem.averagePower::0 698.235540 # Core power per rank (mW) +system.physmem.averagePower::1 698.237375 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 91e62d8ff..8dbd1b2bc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,27 +4,15 @@ sim_seconds 2.400978 # Nu sim_ticks 2400977890000 # Number of ticks simulated final_tick 2400977890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184738 # Simulator instruction rate (inst/s) -host_op_rate 222291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7354994241 # Simulator tick rate (ticks/s) -host_mem_usage 464680 # Number of bytes of host memory used -host_seconds 326.44 # Real time elapsed on the host +host_inst_rate 187249 # Simulator instruction rate (inst/s) +host_op_rate 225312 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7454963168 # Simulator tick rate (ticks/s) +host_mem_usage 414124 # Number of bytes of host memory used +host_seconds 322.06 # Real time elapsed on the host sim_insts 60306316 # Number of instructions simulated sim_ops 72565030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -332,6 +320,36 @@ system.physmem.memoryStateTime::REF 80173860000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 155638381250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3260847240 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3287337480 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1779232125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1793686125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 52225695600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 52659235200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 153692640 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 152461440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 156820070160 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 156820070160 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 104351437575 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 103839738030 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1349049300750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1349498160000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1667640276090 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1668050688435 # Total energy per rank (pJ) +system.physmem.averagePower::0 694.567634 # Core power per rank (mW) +system.physmem.averagePower::1 694.738569 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.membus.trans_dist::ReadReq 15564561 # Transaction distribution system.membus.trans_dist::ReadResp 15564561 # Transaction distribution system.membus.trans_dist::WriteReq 763190 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 9300fd8b1..6d01b379d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.539695 # Nu sim_ticks 2539695141000 # Number of ticks simulated final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55026 # Simulator instruction rate (inst/s) -host_op_rate 66292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2316696588 # Simulator tick rate (ticks/s) -host_mem_usage 466732 # Number of bytes of host memory used -host_seconds 1096.26 # Real time elapsed on the host +host_inst_rate 66572 # Simulator instruction rate (inst/s) +host_op_rate 80202 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2802822069 # Simulator tick rate (ticks/s) +host_mem_usage 418352 # Number of bytes of host memory used +host_seconds 906.12 # Real time elapsed on the host sim_insts 60322278 # Number of instructions simulated sim_ops 72673006 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -317,6 +317,24 @@ system.physmem.memoryStateTime::REF 84805760000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3810769200 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3815857080 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2079288750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2082064875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 59414885400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 59440056000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 341813520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 349511760 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 165880066560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 165880066560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 143884087110 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 144952782390 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1397598764250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1396661312250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1773009674790 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1773181650915 # Total energy per rank (pJ) +system.physmem.averagePower::0 698.121024 # Core power per rank (mW) +system.physmem.averagePower::1 698.188739 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 231f5f650..3aad6c8ee 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.627904 # Nu sim_ticks 2627903712000 # Number of ticks simulated final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497056 # Simulator instruction rate (inst/s) -host_op_rate 593637 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21691918305 # Simulator tick rate (ticks/s) -host_mem_usage 460332 # Number of bytes of host memory used -host_seconds 121.15 # Real time elapsed on the host +host_inst_rate 449186 # Simulator instruction rate (inst/s) +host_op_rate 536465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19602826894 # Simulator tick rate (ticks/s) +host_mem_usage 462988 # Number of bytes of host memory used +host_seconds 134.06 # Real time elapsed on the host sim_insts 60216663 # Number of instructions simulated sim_ops 71917112 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -312,6 +312,24 @@ system.physmem.memoryStateTime::REF 87751300000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 285203111500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3933127800 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3930897600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2146051875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2144835000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 61220499600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 61166492400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 339707520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 339798240 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 171641542800 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 171641542800 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 154602145665 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 155429248725 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1441123214250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1440397685250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1835006289510 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1835050500015 # Total energy per rank (pJ) +system.physmem.averagePower::0 698.278968 # Core power per rank (mW) +system.physmem.averagePower::1 698.295792 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 442dd3c07..02f62080c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.129877 # Nu sim_ticks 5129876981500 # Number of ticks simulated final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179907 # Simulator instruction rate (inst/s) -host_op_rate 355619 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2263051238 # Simulator tick rate (ticks/s) -host_mem_usage 804092 # Number of bytes of host memory used -host_seconds 2266.80 # Real time elapsed on the host +host_inst_rate 181923 # Simulator instruction rate (inst/s) +host_op_rate 359604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2288414721 # Simulator tick rate (ticks/s) +host_mem_usage 752624 # Number of bytes of host memory used +host_seconds 2241.67 # Real time elapsed on the host sim_insts 407812863 # Number of instructions simulated sim_ops 806114915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -289,6 +289,24 @@ system.physmem.memoryStateTime::REF 171297620000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 267480360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 282131640 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 145946625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 153940875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 719347200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 730392000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 482144400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 488449440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 335058144720 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 335058144720 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 129492550125 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 129753331110 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 2964331954500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 2964103199250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 3430497567930 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 3430569589035 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.729942 # Core power per rank (mW) +system.physmem.averagePower::1 668.743982 # Core power per rank (mW) system.membus.trans_dist::ReadReq 662528 # Transaction distribution system.membus.trans_dist::ReadResp 662520 # Transaction distribution system.membus.trans_dist::WriteReq 13776 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 9d272e2fa..76fedc0c9 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.300439 # Nu sim_ticks 5300438650000 # Number of ticks simulated final_tick 5300438650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184616 # Simulator instruction rate (inst/s) -host_op_rate 353991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9163289290 # Simulator tick rate (ticks/s) -host_mem_usage 842832 # Number of bytes of host memory used -host_seconds 578.44 # Real time elapsed on the host +host_inst_rate 211376 # Simulator instruction rate (inst/s) +host_op_rate 405302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10491513446 # Simulator tick rate (ticks/s) +host_mem_usage 792492 # Number of bytes of host memory used +host_seconds 505.21 # Real time elapsed on the host sim_insts 106789618 # Number of instructions simulated sim_ops 204763566 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -258,6 +258,24 @@ system.physmem.memoryStateTime::REF 176993180000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 0 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 0 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 0 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 0 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 0 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 0 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 0 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 346198660080 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 346198660080 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 114660947205 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 114660947205 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 3079681479750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 3079681479750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 3540541087035 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 3540541087035 # Total energy per rank (pJ) +system.physmem.averagePower::0 667.971742 # Core power per rank (mW) +system.physmem.averagePower::1 667.971742 # Core power per rank (mW) system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index cf390c4d1..9fd6d97ff 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.133872 # Nu sim_ticks 5133872107500 # Number of ticks simulated final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 287663 # Simulator instruction rate (inst/s) -host_op_rate 571806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6046720341 # Simulator tick rate (ticks/s) -host_mem_usage 1024224 # Number of bytes of host memory used -host_seconds 849.03 # Real time elapsed on the host +host_inst_rate 332026 # Simulator instruction rate (inst/s) +host_op_rate 659988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6979227984 # Simulator tick rate (ticks/s) +host_mem_usage 973372 # Number of bytes of host memory used +host_seconds 735.59 # Real time elapsed on the host sim_insts 244235751 # Number of instructions simulated sim_ops 485482573 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -311,6 +311,24 @@ system.physmem.memoryStateTime::REF 171431260000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 145575360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 156537360 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 79431000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 85412250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 323294400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 341772600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 270468720 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 280344240 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 335319544560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 335319544560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 122941148535 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 123404461065 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 2972480080500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 2972073666000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 3431559543075 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 3431661738075 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.415487 # Core power per rank (mW) +system.physmem.averagePower::1 668.435393 # Core power per rank (mW) system.membus.trans_dist::ReadReq 5056260 # Transaction distribution system.membus.trans_dist::ReadResp 5056258 # Transaction distribution system.membus.trans_dist::WriteReq 13754 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index d00c8cdc7..477530da6 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061144 # Nu sim_ticks 61144411500 # Number of ticks simulated final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 269135 # Simulator instruction rate (inst/s) -host_op_rate 270476 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181629122 # Simulator tick rate (ticks/s) -host_mem_usage 440052 # Number of bytes of host memory used -host_seconds 336.64 # Real time elapsed on the host +host_inst_rate 271316 # Simulator instruction rate (inst/s) +host_op_rate 272668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 183101149 # Simulator tick rate (ticks/s) +host_mem_usage 442968 # Number of bytes of host memory used +host_seconds 333.94 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -223,6 +223,24 @@ system.physmem.memoryStateTime::REF 2041520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 6305040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 5254200 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3440250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2866875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 63671400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 57454800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3993213120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3993213120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 2474179335 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 2524417425 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 34512404250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 34468335750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 41053213395 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 41051542170 # Total energy per rank (pJ) +system.physmem.averagePower::0 671.485556 # Core power per rank (mW) +system.physmem.averagePower::1 671.458220 # Core power per rank (mW) system.membus.trans_dist::ReadReq 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index c9174d583..863245d9d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.057713 # Nu sim_ticks 57712782000 # Number of ticks simulated final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133015 # Simulator instruction rate (inst/s) -host_op_rate 133677 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84740771 # Simulator tick rate (ticks/s) -host_mem_usage 440040 # Number of bytes of host memory used -host_seconds 681.05 # Real time elapsed on the host +host_inst_rate 133110 # Simulator instruction rate (inst/s) +host_op_rate 133773 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84801314 # Simulator tick rate (ticks/s) +host_mem_usage 388280 # Number of bytes of host memory used +host_seconds 680.56 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -255,6 +255,24 @@ system.physmem.memoryStateTime::REF 1927120000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 11854080 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 10636920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 6468000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 5803875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 71299800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 62602800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3842640 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3395520 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 2993861160 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 3031288785 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 32001000000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 31968168750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 38857772400 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 38851343370 # Total energy per rank (pJ) +system.physmem.averagePower::0 673.305017 # Core power per rank (mW) +system.physmem.averagePower::1 673.193618 # Core power per rank (mW) system.membus.trans_dist::ReadReq 17158 # Transaction distribution system.membus.trans_dist::ReadResp 17158 # Transaction distribution system.membus.trans_dist::Writeback 1150 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 7c30be235..5a7700eb4 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061857 # Nu sim_ticks 61857343500 # Number of ticks simulated final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115241 # Simulator instruction rate (inst/s) -host_op_rate 202921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45120347 # Simulator tick rate (ticks/s) -host_mem_usage 449832 # Number of bytes of host memory used -host_seconds 1370.94 # Real time elapsed on the host +host_inst_rate 117254 # Simulator instruction rate (inst/s) +host_op_rate 206466 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45908562 # Simulator tick rate (ticks/s) +host_mem_usage 395064 # Number of bytes of host memory used +host_seconds 1347.40 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -249,6 +249,24 @@ system.physmem.memoryStateTime::REF 2065440000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 10939320 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 9623880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 5968875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 5251125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 122226000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 114246600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 1095120 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 51840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 4040000640 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 4040000640 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 2776037940 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 2977033050 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 34677417000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 34501105500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 41633684895 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 41647312635 # Total energy per rank (pJ) +system.physmem.averagePower::0 673.093577 # Core power per rank (mW) +system.physmem.averagePower::1 673.313897 # Core power per rank (mW) system.membus.trans_dist::ReadReq 1465 # Transaction distribution system.membus.trans_dist::ReadResp 1462 # Transaction distribution system.membus.trans_dist::Writeback 197 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index c9c70abd5..d4eaaecb0 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.409380 # Nu sim_ticks 409379703500 # Number of ticks simulated final_tick 409379703500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330737 # Simulator instruction rate (inst/s) -host_op_rate 330737 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 221272474 # Simulator tick rate (ticks/s) -host_mem_usage 294228 # Number of bytes of host memory used -host_seconds 1850.12 # Real time elapsed on the host +host_inst_rate 295886 # Simulator instruction rate (inst/s) +host_op_rate 295886 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197956312 # Simulator tick rate (ticks/s) +host_mem_usage 239696 # Number of bytes of host memory used +host_seconds 2068.03 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -261,6 +261,24 @@ system.physmem.memoryStateTime::REF 13670020000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 120335301000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 544939920 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 524943720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 297338250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 286427625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1495143000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1465986600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 953104320 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 942425280 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 26738559120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 26738559120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 61488174015 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 58208465835 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 191689779750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 194566716750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 283207038375 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 282733524930 # Total energy per rank (pJ) +system.physmem.averagePower::0 691.798455 # Core power per rank (mW) +system.physmem.averagePower::1 690.641789 # Core power per rank (mW) system.membus.trans_dist::ReadReq 173391 # Transaction distribution system.membus.trans_dist::ReadResp 173391 # Transaction distribution system.membus.trans_dist::Writeback 292561 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 70e92b094..c27afafd9 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361881 # Nu sim_ticks 361880862500 # Number of ticks simulated final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239591 # Simulator instruction rate (inst/s) -host_op_rate 259509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171154005 # Simulator tick rate (ticks/s) -host_mem_usage 311472 # Number of bytes of host memory used -host_seconds 2114.36 # Real time elapsed on the host +host_inst_rate 214559 # Simulator instruction rate (inst/s) +host_op_rate 232396 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153272119 # Simulator tick rate (ticks/s) +host_mem_usage 259716 # Number of bytes of host memory used +host_seconds 2361.04 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -254,6 +254,24 @@ system.physmem.memoryStateTime::REF 12083760000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 246146040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 242562600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134305875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 132350625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 560164800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 562497000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 310469760 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 314539200 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 23635834560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 23635834560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 46793455740 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 46253268450 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 176077509750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 176551358250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 247757886525 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 247692410685 # Total energy per rank (pJ) +system.physmem.averagePower::0 684.652353 # Core power per rank (mW) +system.physmem.averagePower::1 684.471418 # Core power per rank (mW) system.membus.trans_dist::ReadReq 43225 # Transaction distribution system.membus.trans_dist::ReadResp 43225 # Transaction distribution system.membus.trans_dist::Writeback 96521 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 42984a2d0..97da265c5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.231519 # Nu sim_ticks 231518815500 # Number of ticks simulated final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126327 # Simulator instruction rate (inst/s) -host_op_rate 136857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57887815 # Simulator tick rate (ticks/s) -host_mem_usage 321348 # Number of bytes of host memory used -host_seconds 3999.44 # Real time elapsed on the host +host_inst_rate 137569 # Simulator instruction rate (inst/s) +host_op_rate 149036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63039200 # Simulator tick rate (ticks/s) +host_mem_usage 324016 # Number of bytes of host memory used +host_seconds 3672.62 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -262,6 +262,24 @@ system.physmem.memoryStateTime::REF 7730840000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 1204270200 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 1209705840 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 657091875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 660057750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1746123600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1733674800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 981894960 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 986450400 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 15121523040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 15121523040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 75885673770 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 75815795475 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 72343590000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 72404886750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 167940167445 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 167932094055 # Total energy per rank (pJ) +system.physmem.averagePower::0 725.391418 # Core power per rank (mW) +system.physmem.averagePower::1 725.356546 # Core power per rank (mW) system.membus.trans_dist::ReadReq 445006 # Transaction distribution system.membus.trans_dist::ReadResp 445005 # Transaction distribution system.membus.trans_dist::Writeback 303849 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 75f1d4e39..d2976812f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.451764 # Nu sim_ticks 451764406000 # Number of ticks simulated final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99375 # Simulator instruction rate (inst/s) -host_op_rate 183755 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54293474 # Simulator tick rate (ticks/s) -host_mem_usage 421524 # Number of bytes of host memory used -host_seconds 8320.79 # Real time elapsed on the host +host_inst_rate 112231 # Simulator instruction rate (inst/s) +host_op_rate 207527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61317335 # Simulator tick rate (ticks/s) +host_mem_usage 367016 # Number of bytes of host memory used +host_seconds 7367.65 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -266,6 +266,24 @@ system.physmem.memoryStateTime::REF 15085200000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 567642600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 546300720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 309725625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 298080750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1526397600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1488559800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 976736880 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 928272960 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 29506651200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 29506651200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 64826566830 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 62404533090 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 214189673250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 216314264250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 311903393985 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 311486662770 # Total energy per rank (pJ) +system.physmem.averagePower::0 690.420687 # Core power per rank (mW) +system.physmem.averagePower::1 689.498222 # Core power per rank (mW) system.membus.trans_dist::ReadReq 179971 # Transaction distribution system.membus.trans_dist::ReadResp 179970 # Transaction distribution system.membus.trans_dist::Writeback 294074 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index e79be71e4..fb931db93 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.220941 # Nu sim_ticks 220941341500 # Number of ticks simulated final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 328458 # Simulator instruction rate (inst/s) -host_op_rate 328458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182032431 # Simulator tick rate (ticks/s) -host_mem_usage 297876 # Number of bytes of host memory used -host_seconds 1213.75 # Real time elapsed on the host +host_inst_rate 295257 # Simulator instruction rate (inst/s) +host_op_rate 295257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163632311 # Simulator tick rate (ticks/s) +host_mem_usage 243348 # Number of bytes of host memory used +host_seconds 1350.23 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -223,6 +223,24 @@ system.physmem.memoryStateTime::REF 7377500000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 6743520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 4717440 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3679500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2574000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 34164000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 26902200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 14430390000 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 14430390000 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 5688842535 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 5444083395 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 127570849500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 127785550500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 147734669055 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 147694217535 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.679022 # Core power per rank (mW) +system.physmem.averagePower::1 668.495929 # Core power per rank (mW) system.membus.trans_dist::ReadReq 4737 # Transaction distribution system.membus.trans_dist::ReadResp 4737 # Transaction distribution system.membus.trans_dist::ReadExReq 3138 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 7fec5fb4b..52c9c0408 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.069652 # Nu sim_ticks 69651704000 # Number of ticks simulated final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258321 # Simulator instruction rate (inst/s) -host_op_rate 258321 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47906543 # Simulator tick rate (ticks/s) -host_mem_usage 298148 # Number of bytes of host memory used -host_seconds 1453.91 # Real time elapsed on the host +host_inst_rate 274902 # Simulator instruction rate (inst/s) +host_op_rate 274902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50981523 # Simulator tick rate (ticks/s) +host_mem_usage 244336 # Number of bytes of host memory used +host_seconds 1366.21 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 2325700000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 5843880 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 4362120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3188625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2380125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 32385600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 25373400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 2090120175 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1977791130 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 39955521000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 40054055250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 46636128480 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 46613031225 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.594966 # Core power per rank (mW) +system.physmem.averagePower::1 669.263339 # Core power per rank (mW) system.membus.trans_dist::ReadReq 4328 # Transaction distribution system.membus.trans_dist::ReadResp 4328 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index b4d2bc6bd..3f279951b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212377 # Nu sim_ticks 212377413000 # Number of ticks simulated final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164145 # Simulator instruction rate (inst/s) -host_op_rate 197075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 127677508 # Simulator tick rate (ticks/s) -host_mem_usage 316656 # Number of bytes of host memory used -host_seconds 1663.39 # Real time elapsed on the host +host_inst_rate 195363 # Simulator instruction rate (inst/s) +host_op_rate 234555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 151959329 # Simulator tick rate (ticks/s) +host_mem_usage 264884 # Number of bytes of host memory used +host_seconds 1397.59 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -223,6 +223,24 @@ system.physmem.memoryStateTime::REF 7091500000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 4921560 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 6380640 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2685375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 3481500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 29897400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 28977000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 13870974000 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 13870974000 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 5549858010 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 5731608780 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 122553840750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 122394410250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 142012177095 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 142035832170 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.700966 # Core power per rank (mW) +system.physmem.averagePower::1 668.812352 # Core power per rank (mW) system.membus.trans_dist::ReadReq 4730 # Transaction distribution system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadExReq 2853 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index f8fbd30b2..373457bb0 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.112541 # Nu sim_ticks 112540655000 # Number of ticks simulated final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123771 # Simulator instruction rate (inst/s) -host_op_rate 148600 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51015836 # Simulator tick rate (ticks/s) -host_mem_usage 322668 # Number of bytes of host memory used -host_seconds 2205.99 # Real time elapsed on the host +host_inst_rate 132153 # Simulator instruction rate (inst/s) +host_op_rate 158665 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54470958 # Simulator tick rate (ticks/s) +host_mem_usage 270904 # Number of bytes of host memory used +host_seconds 2066.07 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -231,6 +231,24 @@ system.physmem.memoryStateTime::REF 3757780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 4460400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 4845960 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2433750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2644125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 38220000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 37221600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 7350217680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 7350217680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 3071428470 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 3094710975 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 64826723250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 64806300000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 75293483550 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 75295940340 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.067664 # Core power per rank (mW) +system.physmem.averagePower::1 669.089495 # Core power per rank (mW) system.membus.trans_dist::ReadReq 9170 # Transaction distribution system.membus.trans_dist::ReadResp 9170 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 2ef1dce8d..ba9298aae 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.555533 # Nu sim_ticks 555532734000 # Number of ticks simulated final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 337976 # Simulator instruction rate (inst/s) -host_op_rate 337976 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 202152446 # Simulator tick rate (ticks/s) -host_mem_usage 300884 # Number of bytes of host memory used -host_seconds 2748.09 # Real time elapsed on the host +host_inst_rate 316770 # Simulator instruction rate (inst/s) +host_op_rate 316770 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189468265 # Simulator tick rate (ticks/s) +host_mem_usage 247360 # Number of bytes of host memory used +host_seconds 2932.06 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -248,6 +248,24 @@ system.physmem.memoryStateTime::REF 18550220000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 396060840 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 398223000 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 216104625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 217284375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1136803200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1134198000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 215557200 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 36284230320 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 36284230320 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 106733795895 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 107171521695 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 239689369500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 239305399500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 384672802860 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 384726414090 # Total energy per rank (pJ) +system.physmem.averagePower::0 692.448078 # Core power per rank (mW) +system.physmem.averagePower::1 692.544584 # Core power per rank (mW) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index b682164e9..ce136ba27 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.278139 # Nu sim_ticks 278139424500 # Number of ticks simulated final_tick 278139424500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187672 # Simulator instruction rate (inst/s) -host_op_rate 187672 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61966028 # Simulator tick rate (ticks/s) -host_mem_usage 301896 # Number of bytes of host memory used -host_seconds 4488.58 # Real time elapsed on the host +host_inst_rate 197644 # Simulator instruction rate (inst/s) +host_op_rate 197644 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65258345 # Simulator tick rate (ticks/s) +host_mem_usage 248388 # Number of bytes of host memory used +host_seconds 4262.13 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -252,6 +252,24 @@ system.physmem.memoryStateTime::REF 9287460000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 194735825750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 377969760 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 381175200 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 206233500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 207982500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1136124600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1133831400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 215524800 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 18166271760 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 18166271760 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 79684218180 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79920417060 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 96981320250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 96774128250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 196768576530 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 196799330970 # Total energy per rank (pJ) +system.physmem.averagePower::0 707.462354 # Core power per rank (mW) +system.physmem.averagePower::1 707.572929 # Core power per rank (mW) system.membus.trans_dist::ReadReq 224829 # Transaction distribution system.membus.trans_dist::ReadResp 224829 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index ff20ac42e..12718eef7 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.537826 # Nu sim_ticks 537826498500 # Number of ticks simulated final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160425 # Simulator instruction rate (inst/s) -host_op_rate 197504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134676016 # Simulator tick rate (ticks/s) -host_mem_usage 315984 # Number of bytes of host memory used -host_seconds 3993.48 # Real time elapsed on the host +host_inst_rate 182992 # Simulator instruction rate (inst/s) +host_op_rate 225287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153620567 # Simulator tick rate (ticks/s) +host_mem_usage 318916 # Number of bytes of host memory used +host_seconds 3501.01 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -248,6 +248,24 @@ system.physmem.memoryStateTime::REF 17958980000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 422248680 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 421734600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 230393625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 230113125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1134268200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1129057800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 215634960 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 212524560 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 35127764880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 35127764880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 108230961600 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 107988304905 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 227752503750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 227965360500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 373113775695 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 373074860370 # Total energy per rank (pJ) +system.physmem.averagePower::0 693.752260 # Core power per rank (mW) +system.physmem.averagePower::1 693.679903 # Core power per rank (mW) system.membus.trans_dist::ReadReq 224439 # Transaction distribution system.membus.trans_dist::ReadResp 224439 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 9c87a9d2e..183fc2417 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.407884 # Nu sim_ticks 407883784500 # Number of ticks simulated final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87874 # Simulator instruction rate (inst/s) -host_op_rate 108185 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55946898 # Simulator tick rate (ticks/s) -host_mem_usage 2562780 # Number of bytes of host memory used -host_seconds 7290.55 # Real time elapsed on the host +host_inst_rate 91837 # Simulator instruction rate (inst/s) +host_op_rate 113063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58469822 # Simulator tick rate (ticks/s) +host_mem_usage 2565440 # Number of bytes of host memory used +host_seconds 6975.97 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -277,6 +277,24 @@ system.physmem.memoryStateTime::REF 13620100000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 524928600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 520778160 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 286419375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 284154750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1248351000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1238000400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 216380160 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 212718960 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 26640915600 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 26640915600 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 97043660235 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 97028348895 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 159603762000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 159617193000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 285564416970 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 285542109765 # Total energy per rank (pJ) +system.physmem.averagePower::0 700.113612 # Core power per rank (mW) +system.physmem.averagePower::1 700.058922 # Core power per rank (mW) system.membus.trans_dist::ReadReq 317731 # Transaction distribution system.membus.trans_dist::ReadResp 317731 # Transaction distribution system.membus.trans_dist::Writeback 66312 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index a8bf58a9c..2a99c07ac 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.058385 # Nu sim_ticks 58384546000 # Number of ticks simulated final_tick 58384546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 341517 # Simulator instruction rate (inst/s) -host_op_rate 341516 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 225460414 # Simulator tick rate (ticks/s) -host_mem_usage 300016 # Number of bytes of host memory used -host_seconds 258.96 # Real time elapsed on the host +host_inst_rate 341117 # Simulator instruction rate (inst/s) +host_op_rate 341117 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 225196692 # Simulator tick rate (ticks/s) +host_mem_usage 245432 # Number of bytes of host memory used +host_seconds 259.26 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -251,6 +251,24 @@ system.physmem.memoryStateTime::REF 1949480000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 24496780500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 198434880 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 212398200 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 108273000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 115891875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 642478200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 656705400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 367733520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 370876320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3813182880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3813182880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 12240327915 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 12673025460 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 24291807750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 23912248500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 41662238145 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 41754328635 # Total energy per rank (pJ) +system.physmem.averagePower::0 713.619786 # Core power per rank (mW) +system.physmem.averagePower::1 715.197176 # Core power per rank (mW) system.membus.trans_dist::ReadReq 35730 # Transaction distribution system.membus.trans_dist::ReadResp 35730 # Transaction distribution system.membus.trans_dist::Writeback 114048 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 8732e3592..f3059ec0c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022330 # Nu sim_ticks 22329989500 # Number of ticks simulated final_tick 22329989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232150 # Simulator instruction rate (inst/s) -host_op_rate 232150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65131135 # Simulator tick rate (ticks/s) -host_mem_usage 301288 # Number of bytes of host memory used -host_seconds 342.85 # Real time elapsed on the host +host_inst_rate 240121 # Simulator instruction rate (inst/s) +host_op_rate 240121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67367468 # Simulator tick rate (ticks/s) +host_mem_usage 247512 # Number of bytes of host memory used +host_seconds 331.47 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -257,6 +257,24 @@ system.physmem.memoryStateTime::REF 745420000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 12015383500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 189642600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 202358520 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 103475625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 110413875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 641035200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 654732000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 367578000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 370610640 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1458041520 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1458041520 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 6640293375 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 6800916240 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 7569244500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 7428347250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 16969310820 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 17025420045 # Total energy per rank (pJ) +system.physmem.averagePower::0 760.156668 # Core power per rank (mW) +system.physmem.averagePower::1 762.670135 # Core power per rank (mW) system.membus.trans_dist::ReadReq 35446 # Transaction distribution system.membus.trans_dist::ReadResp 35446 # Transaction distribution system.membus.trans_dist::Writeback 114014 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c0db0b0bb..92998cd4b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.056374 # Nu sim_ticks 56374399500 # Number of ticks simulated final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197105 # Simulator instruction rate (inst/s) -host_op_rate 252068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 156689619 # Simulator tick rate (ticks/s) -host_mem_usage 315764 # Number of bytes of host memory used -host_seconds 359.78 # Real time elapsed on the host +host_inst_rate 200830 # Simulator instruction rate (inst/s) +host_op_rate 256832 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159651052 # Simulator tick rate (ticks/s) +host_mem_usage 319716 # Number of bytes of host memory used +host_seconds 353.11 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -251,6 +251,24 @@ system.physmem.memoryStateTime::REF 1882400000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 150716160 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 138521880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 82236000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 75582375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 512857800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 492039600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 272347920 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 271479600 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3681974400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3681974400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 11715197175 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 11107328085 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 23547137250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 24080355750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 39962466705 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 39847281690 # Total energy per rank (pJ) +system.physmem.averagePower::0 708.897385 # Core power per rank (mW) +system.physmem.averagePower::1 706.854109 # Core power per rank (mW) system.membus.trans_dist::ReadReq 26583 # Transaction distribution system.membus.trans_dist::ReadResp 26583 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6f17594b7..5624de336 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.032615 # Nu sim_ticks 32615215000 # Number of ticks simulated final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86014 # Simulator instruction rate (inst/s) -host_op_rate 110001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39563517 # Simulator tick rate (ticks/s) -host_mem_usage 333060 # Number of bytes of host memory used -host_seconds 824.38 # Real time elapsed on the host +host_inst_rate 125661 # Simulator instruction rate (inst/s) +host_op_rate 160706 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57800178 # Simulator tick rate (ticks/s) +host_mem_usage 335740 # Number of bytes of host memory used +host_seconds 564.28 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -262,6 +262,24 @@ system.physmem.memoryStateTime::REF 1088880000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 352167480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 337674960 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 192154875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 184247250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 628633200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 584321400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 319101120 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 318206880 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 2129849280 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 2129849280 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 12060126405 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 11622718665 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 8986386750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 9370077750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 24668419110 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 24547096185 # Total energy per rank (pJ) +system.physmem.averagePower::0 756.489386 # Core power per rank (mW) +system.physmem.averagePower::1 752.768859 # Core power per rank (mW) system.membus.trans_dist::ReadReq 149976 # Transaction distribution system.membus.trans_dist::ReadResp 149976 # Transaction distribution system.membus.trans_dist::Writeback 98491 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 25a59730e..3052ca460 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.182263 # Nu sim_ticks 1182263011500 # Number of ticks simulated final_tick 1182263011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 338169 # Simulator instruction rate (inst/s) -host_op_rate 338169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 218905814 # Simulator tick rate (ticks/s) -host_mem_usage 291920 # Number of bytes of host memory used -host_seconds 5400.78 # Real time elapsed on the host +host_inst_rate 317111 # Simulator instruction rate (inst/s) +host_op_rate 317111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205274325 # Simulator tick rate (ticks/s) +host_mem_usage 237352 # Number of bytes of host memory used +host_seconds 5759.43 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -260,6 +260,24 @@ system.physmem.memoryStateTime::REF 39478140000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 756941975000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 6738530400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 7145810280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3676777500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 3899003625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7383534600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 7902102000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3233772720 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3364338240 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 77219241840 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 77219241840 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 405130664925 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 418464065025 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 353976228000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 342280263000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 857358749985 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 860274824010 # Total energy per rank (pJ) +system.physmem.averagePower::0 725.188336 # Core power per rank (mW) +system.physmem.averagePower::1 727.654868 # Core power per rank (mW) system.membus.trans_dist::ReadReq 1181608 # Transaction distribution system.membus.trans_dist::ReadResp 1181608 # Transaction distribution system.membus.trans_dist::Writeback 1018252 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a0b66714a..704344325 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.662267 # Nu sim_ticks 662266942000 # Number of ticks simulated final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180229 # Simulator instruction rate (inst/s) -host_op_rate 180229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68753783 # Simulator tick rate (ticks/s) -host_mem_usage 293196 # Number of bytes of host memory used -host_seconds 9632.44 # Real time elapsed on the host +host_inst_rate 189043 # Simulator instruction rate (inst/s) +host_op_rate 189043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72116099 # Simulator tick rate (ticks/s) +host_mem_usage 239436 # Number of bytes of host memory used +host_seconds 9183.34 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -266,6 +266,24 @@ system.physmem.memoryStateTime::REF 22114300000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 6510407400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 6915200040 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3552305625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 3773174625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7409890800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 7939939800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3239831520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3372004080 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 43255570800 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 43255570800 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 299907401805 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 307252084365 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 134279187750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 127836483750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 498154595700 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 500344457460 # Total energy per rank (pJ) +system.physmem.averagePower::0 752.204234 # Core power per rank (mW) +system.physmem.averagePower::1 755.510885 # Core power per rank (mW) system.membus.trans_dist::ReadReq 1197969 # Transaction distribution system.membus.trans_dist::ReadResp 1197969 # Transaction distribution system.membus.trans_dist::Writeback 1020376 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 217d3879c..9172e88dd 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.096187 # Nu sim_ticks 1096186990500 # Number of ticks simulated final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242878 # Simulator instruction rate (inst/s) -host_op_rate 261664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172372275 # Simulator tick rate (ticks/s) -host_mem_usage 308000 # Number of bytes of host memory used -host_seconds 6359.42 # Real time elapsed on the host +host_inst_rate 245276 # Simulator instruction rate (inst/s) +host_op_rate 264248 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174074375 # Simulator tick rate (ticks/s) +host_mem_usage 310916 # Number of bytes of host memory used +host_seconds 6297.23 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -257,6 +257,24 @@ system.physmem.memoryStateTime::REF 36603840000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 7068978000 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 7417161360 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 3857081250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 4047062250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7754580600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 8267360400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3307910400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3472476480 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 71597111040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 71597111040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 413628192720 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 422690389875 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 294876051750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 286926756000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 802089905760 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 804418317405 # Total energy per rank (pJ) +system.physmem.averagePower::0 731.713906 # Core power per rank (mW) +system.physmem.averagePower::1 733.838021 # Core power per rank (mW) system.membus.trans_dist::ReadReq 1255486 # Transaction distribution system.membus.trans_dist::ReadResp 1255486 # Transaction distribution system.membus.trans_dist::Writeback 1046381 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 6fb6c2d5a..20a214b43 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.753004 # Nu sim_ticks 753003557500 # Number of ticks simulated final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139511 # Simulator instruction rate (inst/s) -host_op_rate 150302 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68014357 # Simulator tick rate (ticks/s) -host_mem_usage 308752 # Number of bytes of host memory used -host_seconds 11071.24 # Real time elapsed on the host +host_inst_rate 139146 # Simulator instruction rate (inst/s) +host_op_rate 149909 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67836303 # Simulator tick rate (ticks/s) +host_mem_usage 311432 # Number of bytes of host memory used +host_seconds 11100.30 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -279,6 +279,24 @@ system.physmem.memoryStateTime::REF 25144340000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 16285857840 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 16557549120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 8886132750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 9034377000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 19540895400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 20189722800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 5361143760 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5476960800 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 49182329040 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 49182329040 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 403433749845 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 404376910605 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 97911188250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 97083854250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 600601296885 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 601901703615 # Total energy per rank (pJ) +system.physmem.averagePower::0 797.610503 # Core power per rank (mW) +system.physmem.averagePower::1 799.337469 # Core power per rank (mW) system.membus.trans_dist::ReadReq 4164250 # Transaction distribution system.membus.trans_dist::ReadResp 4164249 # Transaction distribution system.membus.trans_dist::Writeback 1672636 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 6b0be7058..d4fe531fc 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051523 # Nu sim_ticks 51522973500 # Number of ticks simulated final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 356175 # Simulator instruction rate (inst/s) -host_op_rate 356175 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 199679816 # Simulator tick rate (ticks/s) -host_mem_usage 295568 # Number of bytes of host memory used -host_seconds 258.03 # Real time elapsed on the host +host_inst_rate 234694 # Simulator instruction rate (inst/s) +host_op_rate 234694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131574801 # Simulator tick rate (ticks/s) +host_mem_usage 241032 # Number of bytes of host memory used +host_seconds 391.59 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -223,6 +223,24 @@ system.physmem.memoryStateTime::REF 1720420000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1333970250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3470040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3810240 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1893375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2079000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 19999200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 21340800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3365141520 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3365141520 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1727742960 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1771093170 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29397561750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29359535250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34515808845 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34522999980 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.925309 # Core power per rank (mW) +system.physmem.averagePower::1 670.064883 # Core power per rank (mW) system.membus.trans_dist::ReadReq 3595 # Transaction distribution system.membus.trans_dist::ReadResp 3595 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index e94df92e1..3e567522b 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022159 # Nu sim_ticks 22159411000 # Number of ticks simulated final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 217065 # Simulator instruction rate (inst/s) -host_op_rate 217065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57140149 # Simulator tick rate (ticks/s) -host_mem_usage 296848 # Number of bytes of host memory used -host_seconds 387.81 # Real time elapsed on the host +host_inst_rate 173006 # Simulator instruction rate (inst/s) +host_op_rate 173006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45541949 # Simulator tick rate (ticks/s) +host_mem_usage 243048 # Number of bytes of host memory used +host_seconds 486.57 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 739700000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 868697500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3137400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3341520 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1711875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1823250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 19453200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 20802600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 893934990 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 919865430 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 12507131250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 12484385250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 14872221915 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 14877071250 # Total energy per rank (pJ) +system.physmem.averagePower::0 671.367239 # Core power per rank (mW) +system.physmem.averagePower::1 671.586150 # Core power per rank (mW) system.membus.trans_dist::ReadReq 3523 # Transaction distribution system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1709 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 997617f78..5a483b5e7 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131652 # Nu sim_ticks 131652469500 # Number of ticks simulated final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246188 # Simulator instruction rate (inst/s) -host_op_rate 259522 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188090070 # Simulator tick rate (ticks/s) -host_mem_usage 311300 # Number of bytes of host memory used -host_seconds 699.94 # Real time elapsed on the host +host_inst_rate 162179 # Simulator instruction rate (inst/s) +host_op_rate 170963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123906567 # Simulator tick rate (ticks/s) +host_mem_usage 259776 # Number of bytes of host memory used +host_seconds 1062.51 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -223,6 +223,24 @@ system.physmem.memoryStateTime::REF 4396080000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3039120 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3780000 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1658250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2062500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 16185000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 13774800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 8598732480 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 8598732480 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 3574139400 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 3578406705 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 75854895000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 75851151750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 88048649250 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 88047908235 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.807689 # Core power per rank (mW) +system.physmem.averagePower::1 668.802060 # Core power per rank (mW) system.membus.trans_dist::ReadReq 2779 # Transaction distribution system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 79dbc6b32..613bdf71b 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.084956 # Nu sim_ticks 84955935500 # Number of ticks simulated final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135379 # Simulator instruction rate (inst/s) -host_op_rate 142711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66749907 # Simulator tick rate (ticks/s) -host_mem_usage 309000 # Number of bytes of host memory used -host_seconds 1272.75 # Real time elapsed on the host +host_inst_rate 133775 # Simulator instruction rate (inst/s) +host_op_rate 141021 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65959289 # Simulator tick rate (ticks/s) +host_mem_usage 311648 # Number of bytes of host memory used +host_seconds 1288.01 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -231,6 +231,24 @@ system.physmem.memoryStateTime::REF 2836600000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 905088250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 2585520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2623320 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1410750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1431375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 20943000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 18306600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 5548898160 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 5548898160 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 2301036705 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 2237438385 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 48955167000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 49010955000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 56830041135 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 56819652840 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.934726 # Core power per rank (mW) +system.physmem.averagePower::1 668.812447 # Core power per rank (mW) system.membus.trans_dist::ReadReq 4821 # Transaction distribution system.membus.trans_dist::ReadResp 4821 # Transaction distribution system.membus.trans_dist::ReadExReq 211 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 7d82b8535..55e2f8708 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.148694 # Nu sim_ticks 148694012000 # Number of ticks simulated final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84654 # Simulator instruction rate (inst/s) -host_op_rate 141888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95308980 # Simulator tick rate (ticks/s) -host_mem_usage 341916 # Number of bytes of host memory used -host_seconds 1560.13 # Real time elapsed on the host +host_inst_rate 81223 # Simulator instruction rate (inst/s) +host_op_rate 136137 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91445548 # Simulator tick rate (ticks/s) +host_mem_usage 288088 # Number of bytes of host memory used +host_seconds 1626.04 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 4964960000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 4982040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3500280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2718375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1909875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 22776000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 19507800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 9711461760 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 9711461760 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 4022315865 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 3825718020 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 85683555000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 85856009250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 99447809040 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 99418106985 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.842205 # Core power per rank (mW) +system.physmem.averagePower::1 668.642442 # Core power per rank (mW) system.membus.trans_dist::ReadReq 3933 # Transaction distribution system.membus.trans_dist::ReadResp 3932 # Transaction distribution system.membus.trans_dist::UpgradeReq 296 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 977509ec9..f259fe3aa 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.961827 # Nu sim_ticks 1961826628500 # Number of ticks simulated final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1388652 # Simulator instruction rate (inst/s) -host_op_rate 1388652 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44739465331 # Simulator tick rate (ticks/s) -host_mem_usage 370560 # Number of bytes of host memory used -host_seconds 43.85 # Real time elapsed on the host +host_inst_rate 855480 # Simulator instruction rate (inst/s) +host_op_rate 855480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27561784483 # Simulator tick rate (ticks/s) +host_mem_usage 318220 # Number of bytes of host memory used +host_seconds 71.18 # Real time elapsed on the host sim_insts 60892387 # Number of instructions simulated sim_ops 60892387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -299,6 +299,24 @@ system.physmem.memoryStateTime::REF 65509600000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 248270400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 253917720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 135465000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 138546375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1587175200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1592791200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 385326720 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 397949760 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 128136777600 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 128136777600 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 65365947855 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 65768853780 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1119755735250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1119402309000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1315614698025 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1315691145435 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.607978 # Core power per rank (mW) +system.physmem.averagePower::1 670.646945 # Core power per rank (mW) system.membus.trans_dist::ReadReq 292757 # Transaction distribution system.membus.trans_dist::ReadResp 292757 # Transaction distribution system.membus.trans_dist::WriteReq 14067 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index a960683a9..a2e01807e 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.919439 # Nu sim_ticks 1919439025000 # Number of ticks simulated final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1426339 # Simulator instruction rate (inst/s) -host_op_rate 1426339 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48799693433 # Simulator tick rate (ticks/s) -host_mem_usage 367228 # Number of bytes of host memory used -host_seconds 39.33 # Real time elapsed on the host +host_inst_rate 960719 # Simulator instruction rate (inst/s) +host_op_rate 960718 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32869301826 # Simulator tick rate (ticks/s) +host_mem_usage 317196 # Number of bytes of host memory used +host_seconds 58.40 # Real time elapsed on the host sim_insts 56102180 # Number of instructions simulated sim_ops 56102180 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -289,6 +289,24 @@ system.physmem.memoryStateTime::REF 64094160000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 236499480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 247272480 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 129042375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 134920500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1564266600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1569867000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 370954080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 378814320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 125368176960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 125368176960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 63948324510 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 64460493450 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1095566249250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1095116978250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1287183513255 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1287276522960 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.605262 # Core power per rank (mW) +system.physmem.averagePower::1 670.653719 # Core power per rank (mW) system.membus.trans_dist::ReadReq 292357 # Transaction distribution system.membus.trans_dist::ReadResp 292357 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 73c076f14..20253081d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,33 +4,15 @@ sim_seconds 2.675181 # Nu sim_ticks 2675180779000 # Number of ticks simulated final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 485184 # Simulator instruction rate (inst/s) -host_op_rate 579312 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20736099933 # Simulator tick rate (ticks/s) -host_mem_usage 486856 # Number of bytes of host memory used -host_seconds 129.01 # Real time elapsed on the host +host_inst_rate 349036 # Simulator instruction rate (inst/s) +host_op_rate 416751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14917331050 # Simulator tick rate (ticks/s) +host_mem_usage 433588 # Number of bytes of host memory used +host_seconds 179.33 # Real time elapsed on the host sim_insts 62593972 # Number of instructions simulated sim_ops 74737529 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory @@ -318,6 +300,42 @@ system.physmem.memoryStateTime::REF 89330020000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 258906121500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3975289920 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3974851440 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2169057000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2168817750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 61291097400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 61250069400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 371874240 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 371731680 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 174729519120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 174729519120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 149034867885 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 147923300340 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1474373657250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1475348716500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1865945362815 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1865767006230 # Total energy per rank (pJ) +system.physmem.averagePower::0 697.503604 # Core power per rank (mW) +system.physmem.averagePower::1 697.436933 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.membus.trans_dist::ReadReq 16891737 # Transaction distribution system.membus.trans_dist::ReadResp 16891737 # Transaction distribution system.membus.trans_dist::WriteReq 769090 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 51c016582..a50c29900 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,27 +4,15 @@ sim_seconds 2.614572 # Nu sim_ticks 2614571564500 # Number of ticks simulated final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536806 # Simulator instruction rate (inst/s) -host_op_rate 641128 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23319189669 # Simulator tick rate (ticks/s) -host_mem_usage 459056 # Number of bytes of host memory used -host_seconds 112.12 # Real time elapsed on the host +host_inst_rate 393660 # Simulator instruction rate (inst/s) +host_op_rate 470163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17100811132 # Simulator tick rate (ticks/s) +host_mem_usage 408168 # Number of bytes of host memory used +host_seconds 152.89 # Real time elapsed on the host sim_insts 60187274 # Number of instructions simulated sim_ops 71883961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory @@ -279,6 +267,36 @@ system.physmem.memoryStateTime::REF 87306180000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3884796720 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3881470320 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2119680750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2117865750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 60443307600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 60403543200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 339986160 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 343329840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 170770888080 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 170770888080 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 155970246555 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 156681731385 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1431925089750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1431300980250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1825453995615 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1825499808825 # Total energy per rank (pJ) +system.physmem.averagePower::0 698.185571 # Core power per rank (mW) +system.physmem.averagePower::1 698.203093 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.membus.trans_dist::ReadReq 16546657 # Transaction distribution system.membus.trans_dist::ReadResp 16546657 # Transaction distribution system.membus.trans_dist::WriteReq 763381 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 0fe5602ce..c82f08e25 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.192511 # Nu sim_ticks 5192511044000 # Number of ticks simulated final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1018343 # Simulator instruction rate (inst/s) -host_op_rate 1963050 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41210458750 # Simulator tick rate (ticks/s) -host_mem_usage 646888 # Number of bytes of host memory used -host_seconds 126.00 # Real time elapsed on the host +host_inst_rate 1399863 # Simulator instruction rate (inst/s) +host_op_rate 2698503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56649883486 # Simulator tick rate (ticks/s) +host_mem_usage 595716 # Number of bytes of host memory used +host_seconds 91.66 # Real time elapsed on the host sim_insts 128310974 # Number of instructions simulated sim_ops 247343919 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -289,6 +289,24 @@ system.physmem.memoryStateTime::REF 173389320000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 214242840 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 218884680 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 116898375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 119431125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 608189400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 600186600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 411266160 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 411946560 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 339149509920 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 339149509920 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 134171647065 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 134426407995 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 2997811704000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 2997588229500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 3472483457760 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 3472514596380 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.748507 # Core power per rank (mW) +system.physmem.averagePower::1 668.754504 # Core power per rank (mW) system.membus.trans_dist::ReadReq 623858 # Transaction distribution system.membus.trans_dist::ReadResp 623858 # Transaction distribution system.membus.trans_dist::WriteReq 13773 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 353f5c8e3..a15c23d57 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35024500 # Number of ticks simulated final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173753 # Simulator instruction rate (inst/s) -host_op_rate 173686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 950177695 # Simulator tick rate (ticks/s) -host_mem_usage 289108 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 72507 # Simulator instruction rate (inst/s) +host_op_rate 72491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 396631772 # Simulator tick rate (ticks/s) +host_mem_usage 236200 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -223,6 +223,24 @@ system.physmem.memoryStateTime::REF 1040000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 30394500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 140250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 210375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2082600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1677000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 20168595 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1170000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 25645770 # Total energy per rank (pJ) +system.physmem.averagePower::0 827.295718 # Core power per rank (mW) +system.physmem.averagePower::1 815.802457 # Core power per rank (mW) system.membus.trans_dist::ReadReq 460 # Transaction distribution system.membus.trans_dist::ReadResp 460 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index b6d7e6ec3..d8727c544 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20537500 # Number of ticks simulated final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100086 # Simulator instruction rate (inst/s) -host_op_rate 100066 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 322455292 # Simulator tick rate (ticks/s) -host_mem_usage 290128 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 69014 # Simulator instruction rate (inst/s) +host_op_rate 69006 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 222388397 # Simulator tick rate (ticks/s) +host_mem_usage 237256 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15339250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 234360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 332640 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 127875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 181500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1755000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1365000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 10809765 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 10569510 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 38250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 249000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 13982370 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 13714770 # Total energy per rank (pJ) +system.physmem.averagePower::0 881.195525 # Core power per rank (mW) +system.physmem.averagePower::1 864.330865 # Core power per rank (mW) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 415 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 6f17c0be9..cff801d36 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18662000 # Number of ticks simulated final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154264 # Simulator instruction rate (inst/s) -host_op_rate 154144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1111892278 # Simulator tick rate (ticks/s) -host_mem_usage 287792 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 40123 # Simulator instruction rate (inst/s) +host_op_rate 40110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 289474844 # Simulator tick rate (ticks/s) +host_mem_usage 234892 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -223,6 +223,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15310750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 90720 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 49500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1302600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 10733670 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 84000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 12770610 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 13448430 # Total energy per rank (pJ) +system.physmem.averagePower::0 806.607295 # Core power per rank (mW) +system.physmem.averagePower::1 849.419233 # Core power per rank (mW) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 286f63d05..dd62dc740 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11765500 # Number of ticks simulated final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81487 # Simulator instruction rate (inst/s) -host_op_rate 81445 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 401265305 # Simulator tick rate (ticks/s) -host_mem_usage 288836 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 35174 # Simulator instruction rate (inst/s) +host_op_rate 35164 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173275234 # Simulator tick rate (ticks/s) +host_mem_usage 235920 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 260000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 7778000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 68040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 158760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 37125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 86625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 631800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 850200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 5478840 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 5222340 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 246750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 6746115 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 7073235 # Total energy per rank (pJ) +system.physmem.averagePower::0 838.417275 # Core power per rank (mW) +system.physmem.averagePower::1 879.072239 # Core power per rank (mW) system.membus.trans_dist::ReadReq 248 # Transaction distribution system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 59eccf84d..54adfc503 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27911000 # Number of ticks simulated final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116522 # Simulator instruction rate (inst/s) -host_op_rate 136369 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 705946329 # Simulator tick rate (ticks/s) -host_mem_usage 304192 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 3437 # Simulator instruction rate (inst/s) +host_op_rate 4023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20833659 # Simulator tick rate (ticks/s) +host_mem_usage 251612 # Number of bytes of host memory used +host_seconds 1.34 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,6 +222,24 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22840500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ) +system.physmem.averagePower::0 856.166817 # Core power per rank (mW) +system.physmem.averagePower::1 786.636676 # Core power per rank (mW) system.membus.trans_dist::ReadReq 377 # Transaction distribution system.membus.trans_dist::ReadResp 377 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index bbf908c21..092386ab8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16223000 # Number of ticks simulated final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55920 # Simulator instruction rate (inst/s) -host_op_rate 65484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197542740 # Simulator tick rate (ticks/s) -host_mem_usage 304472 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 26356 # Simulator instruction rate (inst/s) +host_op_rate 30865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93111675 # Simulator tick rate (ticks/s) +host_mem_usage 251576 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -226,6 +226,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 317520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 151200 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 173250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 82500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2238600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 795600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 10477170 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 309000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 14571510 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 12832590 # Total energy per rank (pJ) +system.physmem.averagePower::0 920.354334 # Core power per rank (mW) +system.physmem.averagePower::1 810.522027 # Core power per rank (mW) system.membus.trans_dist::ReadReq 355 # Transaction distribution system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index f52a81778..ce3916e93 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11859500 # Number of ticks simulated final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50616 # Simulator instruction rate (inst/s) -host_op_rate 59274 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130716325 # Simulator tick rate (ticks/s) -host_mem_usage 300356 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 34923 # Simulator instruction rate (inst/s) +host_op_rate 40896 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90188816 # Simulator tick rate (ticks/s) +host_mem_usage 248256 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -231,6 +231,24 @@ system.physmem.memoryStateTime::REF 260000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 7800750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 249480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 90720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 136125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 49500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3088800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1037400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 5483970 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 5436945 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 63000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 9488685 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 7186125 # Total energy per rank (pJ) +system.physmem.averagePower::0 1178.169797 # Core power per rank (mW) +system.physmem.averagePower::1 892.270681 # Core power per rank (mW) system.membus.trans_dist::ReadReq 704 # Transaction distribution system.membus.trans_dist::ReadResp 702 # Transaction distribution system.membus.trans_dist::ReadExReq 29 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 2de82825c..beeb90a4c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24907000 # Number of ticks simulated final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110455 # Simulator instruction rate (inst/s) -host_op_rate 110427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 472950648 # Simulator tick rate (ticks/s) -host_mem_usage 286112 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 46022 # Simulator instruction rate (inst/s) +host_op_rate 46018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197122402 # Simulator tick rate (ticks/s) +host_mem_usage 234444 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -226,6 +226,24 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22841500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 196560 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 582120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 107250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 317625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 756600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 2644200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 14747040 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 16041510 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1235250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 99750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 18568380 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 21210885 # Total energy per rank (pJ) +system.physmem.averagePower::0 786.171156 # Core power per rank (mW) +system.physmem.averagePower::1 898.052818 # Core power per rank (mW) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index cc5bb948f..83678472a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21611500 # Number of ticks simulated final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87050 # Simulator instruction rate (inst/s) -host_op_rate 87030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 364707967 # Simulator tick rate (ticks/s) -host_mem_usage 288672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 52948 # Simulator instruction rate (inst/s) +host_op_rate 52941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221880610 # Simulator tick rate (ticks/s) +host_mem_usage 236528 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -226,6 +226,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 136080 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 536760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 74250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 292875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 569400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 2285400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 9955620 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 10734525 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 766500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 83250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 12518970 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 14949930 # Total energy per rank (pJ) +system.physmem.averagePower::0 790.713406 # Core power per rank (mW) +system.physmem.averagePower::1 944.255803 # Core power per rank (mW) system.membus.trans_dist::ReadReq 428 # Transaction distribution system.membus.trans_dist::ReadResp 428 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 2b23aa030..8d84a5cfe 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18857500 # Number of ticks simulated final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98075 # Simulator instruction rate (inst/s) -host_op_rate 98051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 319158839 # Simulator tick rate (ticks/s) -host_mem_usage 285824 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 71546 # Simulator instruction rate (inst/s) +host_op_rate 71536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232873039 # Simulator tick rate (ticks/s) +host_mem_usage 233800 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 476280 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 68040 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 259875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 37125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2644200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 288600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 8055810 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 2433000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 15222495 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 11899695 # Total energy per rank (pJ) +system.physmem.averagePower::0 961.471341 # Core power per rank (mW) +system.physmem.averagePower::1 751.599242 # Core power per rank (mW) system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 8a50d5754..951c5abaa 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20927500 # Number of ticks simulated final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84066 # Simulator instruction rate (inst/s) -host_op_rate 84047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 330123200 # Simulator tick rate (ticks/s) -host_mem_usage 286520 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 61359 # Simulator instruction rate (inst/s) +host_op_rate 61351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 240990471 # Simulator tick rate (ticks/s) +host_mem_usage 234980 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -225,6 +225,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15312750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 196560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 107250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1497600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1107600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 10702035 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 10576350 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 111750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 222000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 13784220 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 13226880 # Total energy per rank (pJ) +system.physmem.averagePower::0 870.628138 # Core power per rank (mW) +system.physmem.averagePower::1 835.425865 # Core power per rank (mW) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 0db4f4424..a38f35e7a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19678000 # Number of ticks simulated final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48979 # Simulator instruction rate (inst/s) -host_op_rate 88725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 179100946 # Simulator tick rate (ticks/s) -host_mem_usage 305852 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 30596 # Simulator instruction rate (inst/s) +host_op_rate 55428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111894824 # Simulator tick rate (ticks/s) +host_mem_usage 253080 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -225,6 +225,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15318250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 219240 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 446040 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 119625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 243375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1084200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1567800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 10796085 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 10703745 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 112500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 13267770 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 14090580 # Total energy per rank (pJ) +system.physmem.averagePower::0 837.810088 # Core power per rank (mW) +system.physmem.averagePower::1 889.767464 # Core power per rank (mW) system.membus.trans_dist::ReadReq 339 # Transaction distribution system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 5f7cff1f0..c3dfe7f26 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu sim_ticks 23061500 # Number of ticks simulated final_tick 23061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90290 # Simulator instruction rate (inst/s) -host_op_rate 90281 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163358622 # Simulator tick rate (ticks/s) -host_mem_usage 290460 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 45645 # Simulator instruction rate (inst/s) +host_op_rate 45641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82586308 # Simulator tick rate (ticks/s) +host_mem_usage 237816 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15300500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 710640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 438480 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 387750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 239250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3798600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1747200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 10760175 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 10602000 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 60750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 199500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 16735035 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 14243550 # Total energy per rank (pJ) +system.physmem.averagePower::0 1057.005211 # Core power per rank (mW) +system.physmem.averagePower::1 899.639981 # Core power per rank (mW) system.membus.trans_dist::ReadReq 833 # Transaction distribution system.membus.trans_dist::ReadResp 833 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index bc6a50393..2e75d917e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27671000 # Number of ticks simulated final_tick 27671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87465 # Simulator instruction rate (inst/s) -host_op_rate 87458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 159601098 # Simulator tick rate (ticks/s) -host_mem_usage 286440 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 16681 # Simulator instruction rate (inst/s) +host_op_rate 16680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30441710 # Simulator tick rate (ticks/s) +host_mem_usage 234904 # Number of bytes of host memory used +host_seconds 0.91 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -226,6 +226,24 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 21626500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 287280 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 204120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 156750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 111375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1786200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1232400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 15269445 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 14648715 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 797250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1341750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 19822605 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 19064040 # Total energy per rank (pJ) +system.physmem.averagePower::0 838.076525 # Core power per rank (mW) +system.physmem.averagePower::1 806.005285 # Core power per rank (mW) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 5e7063deb..118b6451d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25944000 # Number of ticks simulated final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79125 # Simulator instruction rate (inst/s) -host_op_rate 79119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 142180718 # Simulator tick rate (ticks/s) -host_mem_usage 289004 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 15615 # Simulator instruction rate (inst/s) +host_op_rate 15615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28062245 # Simulator tick rate (ticks/s) +host_mem_usage 236980 # Number of bytes of host memory used +host_seconds 0.92 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,24 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22761250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 309960 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 226800 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 169125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 123750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2106000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1318200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 16044930 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 14873580 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 96750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1124250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 20252445 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 19192260 # Total energy per rank (pJ) +system.physmem.averagePower::0 857.473194 # Core power per rank (mW) +system.physmem.averagePower::1 812.585763 # Core power per rank (mW) system.membus.trans_dist::ReadReq 409 # Transaction distribution system.membus.trans_dist::ReadResp 408 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 2281d59b5..759a62336 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu sim_ticks 105696000 # Number of ticks simulated final_tick 105696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162054 # Simulator instruction rate (inst/s) -host_op_rate 162054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17251704 # Simulator tick rate (ticks/s) -host_mem_usage 304448 # Number of bytes of host memory used -host_seconds 6.13 # Real time elapsed on the host +host_inst_rate 145069 # Simulator instruction rate (inst/s) +host_op_rate 145069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15443503 # Simulator tick rate (ticks/s) +host_mem_usage 252160 # Number of bytes of host memory used +host_seconds 6.84 # Real time elapsed on the host sim_insts 992854 # Number of instructions simulated sim_ops 992854 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -257,6 +257,24 @@ system.physmem.memoryStateTime::REF 3380000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 52590250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 695520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 355320 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 379500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 193875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 2776800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 2051400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 36176760 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 31269060 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29154750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 33459750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 75794610 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 73940685 # Total energy per rank (pJ) +system.physmem.averagePower::0 746.882897 # Core power per rank (mW) +system.physmem.averagePower::1 728.614251 # Core power per rank (mW) system.membus.trans_dist::ReadReq 538 # Transaction distribution system.membus.trans_dist::ReadResp 537 # Transaction distribution system.membus.trans_dist::UpgradeReq 276 # Transaction distribution diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 3240ac711..8a9cf2f50 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 14153017614 # Simulator tick rate (ticks/s) -host_mem_usage 261088 # Number of bytes of host memory used -host_seconds 7.07 # Real time elapsed on the host +host_tick_rate 8686903737 # Simulator tick rate (ticks/s) +host_mem_usage 208524 # Number of bytes of host memory used +host_seconds 11.51 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -249,6 +249,24 @@ system.physmem.memoryStateTime::REF 3339180000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 96654559510 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 12463083360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 12456445680 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 6800293500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 6796671750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 6499693200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 6497868000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 5404598640 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5396297760 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 6531436080 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 6531436080 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 67803083460 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 67799803680 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 523052250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 525929250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 106025240490 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 106004452200 # Total energy per rank (pJ) +system.physmem.averagePower::0 1060.262279 # Core power per rank (mW) +system.physmem.averagePower::1 1060.054394 # Core power per rank (mW) system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution |