diff options
| author | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-03-09 09:59:28 -0500 |
|---|---|---|
| committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-03-09 09:59:28 -0500 |
| commit | da0d67c3d6468bedae93d14a9b7461e2b9d7a645 (patch) | |
| tree | cc450e9463d24939d2482b8135f7473c5d15acc2 /tests | |
| parent | 98cf57fb89b76a8ca423083d52cc647c7923fe51 (diff) | |
| download | gem5-da0d67c3d6468bedae93d14a9b7461e2b9d7a645.tar.xz | |
CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
Diffstat (limited to 'tests')
17 files changed, 3846 insertions, 1 deletions
diff --git a/tests/SConscript b/tests/SConscript index 46d4ca400..93bdcf9b4 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -277,11 +277,14 @@ if env['TARGET_ISA'] == 'sparc': configs += ['t1000-simple-atomic', 't1000-simple-timing'] if env['TARGET_ISA'] == 'arm': - configs += ['realview-simple-atomic', + configs += ['simple-atomic-dummychecker', + 'o3-timing-checker', + 'realview-simple-atomic', 'realview-simple-atomic-dual', 'realview-simple-timing', 'realview-simple-timing-dual', 'realview-o3', + 'realview-o3-checker', 'realview-o3-dual'] if env['TARGET_ISA'] == 'x86': configs += ['pc-simple-atomic', diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py new file mode 100644 index 000000000..dd68a39d7 --- /dev/null +++ b/tests/configs/o3-timing-checker.py @@ -0,0 +1,68 @@ +# Copyright (c) 2011 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Geoffrey Blake + +import m5 +from m5.objects import * +m5.util.addToPath('../configs/common') + +class MyCache(BaseCache): + assoc = 2 + block_size = 64 + latency = '1ns' + mshrs = 10 + tgts_per_mshr = 5 + +class MyL1Cache(MyCache): + is_top_level = True + tgts_per_mshr = 20 + +cpu = DerivO3CPU(cpu_id=0) +cpu.createInterruptController() +cpu.addCheckerCpu() +cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), + MyL1Cache(size = '256kB'), + MyCache(size = '2MB')) +cpu.clock = '2GHz' + +system = System(cpu = cpu, + physmem = PhysicalMemory(), + membus = Bus()) +system.system_port = system.membus.slave +system.physmem.port = system.membus.master +cpu.connectAllPorts(system.membus) + +root = Root(full_system = False, system = system) diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py new file mode 100644 index 000000000..c07c2ca9e --- /dev/null +++ b/tests/configs/realview-o3-checker.py @@ -0,0 +1,109 @@ +# Copyright (c) 2011 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Geoffrey Blake + +import m5 +from m5.objects import * +m5.util.addToPath('../configs/common') +import FSConfig + + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 20 + is_top_level = True + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +# --------------------- +# I/O Cache +# --------------------- +class IOCache(BaseCache): + assoc = 8 + block_size = 64 + latency = '50ns' + mshrs = 20 + size = '1kB' + tgts_per_mshr = 12 + addr_ranges = [AddrRange(0, size='256MB')] + forward_snoops = False + +#cpu +cpu = DerivO3CPU(cpu_id=0) +#the system +system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) + +system.cpu = cpu +#create the l1/l2 bus +system.toL2Bus = Bus() +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave + + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave + +#connect up the checker +cpu.addCheckerCpu() +#connect up the cpu and l1s +cpu.createInterruptController() +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectAllPorts(system.toL2Bus, system.membus) +cpu.clock = '2GHz' + +root = Root(full_system=True, system=system) +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/simple-atomic-dummychecker.py b/tests/configs/simple-atomic-dummychecker.py new file mode 100644 index 000000000..15c287130 --- /dev/null +++ b/tests/configs/simple-atomic-dummychecker.py @@ -0,0 +1,51 @@ +# Copyright (c) 2011 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Geoffrey Blake + +import m5 +from m5.objects import * + +system = System(cpu = AtomicSimpleCPU(cpu_id=0), + physmem = PhysicalMemory(), + membus = Bus()) +system.system_port = system.membus.slave +system.physmem.port = system.membus.master +system.cpu.addCheckerCpu() +system.cpu.createInterruptController() +system.cpu.connectAllPorts(system.membus) +system.cpu.clock = '2GHz' + +root = Root(full_system = False, system = system) diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini new file mode 100644 index 000000000..3f759d7fa --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -0,0 +1,1059 @@ +[root] +type=Root +children=system +full_system=true +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +atags_addr=256 +boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader_mem=system.realview.nvmem +boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +flags_addr=268435504 +gic_cpu_addr=520093952 +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +load_addr_mask=268435455 +machine_type=RealView_PBX +mem_mode=timing +memories=system.physmem system.realview.nvmem +midr_regval=890224640 +num_work_ids=16 +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.bridge] +type=Bridge +delay=50000 +nack_delay=4000 +ranges=268435456:520093695 1073741824:1610612735 +req_size=16 +resp_size=16 +write_ack=false +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-arm-ael.img +read_only=true + +[system.cpu] +type=DerivO3CPU +children=checker dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=system.cpu.checker +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.checker] +type=O3Checker +children=dtb itb tracer +checker=Null +clock=1 +cpu_id=-1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.checker.dtb +exitOnError=false +function_trace=false +function_trace_start=0 +interrupts=Null +itb=system.cpu.checker.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu.checker.tracer +updateOnError=true +warnOnlyOnLoadError=true +workload= + +[system.cpu.checker.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.checker.dtb.walker + +[system.cpu.checker.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.slave[5] + +[system.cpu.checker.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.checker.itb.walker + +[system.cpu.checker.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.slave[4] + +[system.cpu.checker.tracer] +type=ExeTracer + +[system.cpu.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu.interrupts] +type=ArmInterrupts + +[system.cpu.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu.tracer] +type=ExeTracer + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma + +[system.iocache] +type=BaseCache +addr_ranges=0:268435455 +assoc=8 +block_size=64 +forward_snoops=false +hash_delay=1 +is_top_level=false +latency=50000 +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[25] +mem_side=system.membus.slave[1] + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.membus] +type=Bus +children=badaddr_responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +slave=system.system_port system.iocache.mem_side system.l2c.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +fake_mem=false +pio_addr=0 +pio_latency=1000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[2] + +[system.realview] +type=RealView +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +intrctrl=system.intrctrl +max_mem_size=268435456 +mem_start_addr=0 +pci_cfg_base=0 +system=system + +[system.realview.a9scu] +type=A9SCU +pio_addr=520093696 +pio_latency=1000 +system=system +pio=system.membus.master[5] + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268451840 +pio_latency=1000 +system=system +pio=system.iobus.master[21] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=402653184 +BAR0LegacyIO=true +BAR0Size=16 +BAR1=402653440 +BAR1LegacyIO=true +BAR1Size=1 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +ctrl_offset=2 +disks=system.cf0 +io_shift=1 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=2 +pci_dev=7 +pci_func=0 +pio_latency=1000 +platform=system.realview +system=system +config=system.iobus.master[8] +dma=system.iobus.slave[2] +pio=system.iobus.master[7] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clock=41667 +gic=system.realview.gic +int_num=55 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pio_addr=268566528 +pio_latency=10000 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268632064 +pio_latency=1000 +system=system +pio=system.iobus.master[9] + +[system.realview.flash_fake] +type=IsaFake +fake_mem=true +pio_addr=1073741824 +pio_latency=1000 +pio_size=536870912 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[24] + +[system.realview.gic] +type=Gic +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +int_latency=10000 +it_lines=128 +platform=system.realview +system=system +pio=system.membus.master[3] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268513280 +pio_latency=1000 +system=system +pio=system.iobus.master[16] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268517376 +pio_latency=1000 +system=system +pio=system.iobus.master[17] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268521472 +pio_latency=1000 +system=system +pio=system.iobus.master[18] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=1000000 +int_num=52 +is_mouse=false +pio_addr=268460032 +pio_latency=1000 +system=system +vnc=system.vncserver +pio=system.iobus.master[5] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=1000000 +int_num=53 +is_mouse=true +pio_addr=268464128 +pio_latency=1000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.l2x0_fake] +type=IsaFake +fake_mem=false +pio_addr=520101888 +pio_latency=1000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.master[4] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clock=1000 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=1000 +system=system +pio=system.membus.master[6] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268455936 +pio_latency=1000 +system=system +pio=system.iobus.master[22] + +[system.realview.nvmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=2147483648:2214592511 +zero=true +port=system.membus.master[1] + +[system.realview.realview_io] +type=RealViewCtrl +idreg=0 +pio_addr=268435456 +pio_latency=1000 +proc_id0=201326592 +proc_id1=201327138 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc_fake] +type=AmbaFake +amba_id=266289 +ignore_access=false +pio_addr=268529664 +pio_latency=1000 +system=system +pio=system.iobus.master[23] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268492800 +pio_latency=1000 +system=system +pio=system.iobus.master[20] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=269357056 +pio_latency=1000 +system=system +pio=system.iobus.master[13] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +ignore_access=true +pio_addr=268439552 +pio_latency=1000 +system=system +pio=system.iobus.master[14] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268488704 +pio_latency=1000 +system=system +pio=system.iobus.master[19] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=1000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=1000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +end_on_eot=false +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=1000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268476416 +pio_latency=1000 +system=system +pio=system.iobus.master[10] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268480512 +pio_latency=1000 +system=system +pio=system.iobus.master[11] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268484608 +pio_latency=1000 +system=system +pio=system.iobus.master[12] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268500992 +pio_latency=1000 +system=system +pio=system.iobus.master[15] + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port + +[system.vncserver] +type=VncServer +frame_capture=false +number=0 +port=5900 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr new file mode 100755 index 000000000..c3520687e --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -0,0 +1,25 @@ +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: 5655885500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5665876500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5705833500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5722480500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6171915000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: LCD dual screen mode not supported +warn: 53400472000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout new file mode 100755 index 000000000..cda9d1fbb --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -0,0 +1,15 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Mar 7 2012 20:12:09 +gem5 started Mar 7 2012 20:48:24 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker +The currently selected ARM platforms doesn't support + the amount of DRAM you've selected. Please try + another platform +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2503289265500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt new file mode 100644 index 000000000..7ed4fc446 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -0,0 +1,881 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.503289 # Number of seconds simulated +sim_ticks 2503289265500 # Number of ticks simulated +final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 68005 # Simulator instruction rate (inst/s) +host_op_rate 87841 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2863403297 # Simulator tick rate (ticks/s) +host_mem_usage 387312 # Number of bytes of host memory used +host_seconds 874.24 # Real time elapsed on the host +sim_insts 59452703 # Number of instructions simulated +sim_ops 76793713 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory +system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory +system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory +system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read 130753040 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9587720 # Number of bytes written to this memory +system.physmem.num_reads 15117482 # Number of read requests responded to by this memory +system.physmem.num_writes 856700 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 446670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3830049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56062542 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119784 # number of replacements +system.l2c.tagsinuse 26074.057253 # Cycle average of tags in use +system.l2c.total_refs 1841990 # Total number of references to valid blocks. +system.l2c.sampled_refs 150687 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.223948 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 14309.337346 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 64.598044 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.929730 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6189.709081 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5509.483052 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.218343 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.094447 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.084068 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.397859 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 152573 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11543 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 997778 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 377343 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1539237 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 633058 # number of Writeback hits +system.l2c.Writeback_hits::total 633058 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 105979 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105979 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 152573 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 997778 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 483322 # number of demand (read+write) hits +system.l2c.demand_hits::total 1645216 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 152573 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11543 # number of overall hits +system.l2c.overall_hits::cpu.inst 997778 # number of overall hits +system.l2c.overall_hits::cpu.data 483322 # number of overall hits +system.l2c.overall_hits::total 1645216 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 150 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 17347 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 19146 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36655 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 3332 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3332 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 140332 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140332 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 17347 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 159478 # number of demand (read+write) misses +system.l2c.demand_misses::total 176987 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 150 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu.inst 17347 # number of overall misses +system.l2c.overall_misses::cpu.data 159478 # number of overall misses +system.l2c.overall_misses::total 176987 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7830000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 643000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 909187000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1001254500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1918914500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1009500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1009500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7379766000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7379766000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 7830000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 643000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 909187000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8381020500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9298680500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 7830000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 643000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 909187000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8381020500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9298680500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 152723 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11555 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1015125 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 396489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1575892 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 633058 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 633058 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3381 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3381 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246311 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246311 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 152723 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11555 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1015125 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 642800 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1822203 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 152723 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11555 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1015125 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 642800 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1822203 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001039 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017089 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048289 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985507 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.569735 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001039 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.017089 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.248099 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001039 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017089 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.248099 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52200 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53583.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52411.771488 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52295.753682 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 302.971188 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52587.905823 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52200 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 53583.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52411.771488 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52552.831739 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52200 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 53583.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52411.771488 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52552.831739 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 102682 # number of writebacks +system.l2c.writebacks::total 102682 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 80 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 150 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 17335 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 19066 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 36562 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 3332 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3332 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140332 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140332 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 17335 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 159398 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176894 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 17335 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159398 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176894 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6012000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 462000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 696908500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 765299500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1468682000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 134589000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636704500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5636704500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6012000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 462000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 696908500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6402004000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7105386500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6012000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 462000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 696908500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6402004000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7105386500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131761112000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131766619000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32348627763 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164109739763 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164115246763 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048087 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569735 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017077 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.247974 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 42000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40202.394001 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40139.489143 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40392.857143 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40166.922014 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40080 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 42000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40202.394001 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40163.640698 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu.checker.dtb.inst_hits 0 # ITB inst hits +system.cpu.checker.dtb.inst_misses 0 # ITB inst misses +system.cpu.checker.dtb.read_hits 15017434 # DTB read hits +system.cpu.checker.dtb.read_misses 7313 # DTB read misses +system.cpu.checker.dtb.write_hits 11274974 # DTB write hits +system.cpu.checker.dtb.write_misses 2190 # DTB write misses +system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 15024747 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11277164 # DTB write accesses +system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dtb.hits 26292408 # DTB hits +system.cpu.checker.dtb.misses 9503 # DTB misses +system.cpu.checker.dtb.accesses 26301911 # DTB accesses +system.cpu.checker.itb.inst_hits 60619265 # ITB inst hits +system.cpu.checker.itb.inst_misses 4471 # ITB inst misses +system.cpu.checker.itb.read_hits 0 # DTB read hits +system.cpu.checker.itb.read_misses 0 # DTB read misses +system.cpu.checker.itb.write_hits 0 # DTB write hits +system.cpu.checker.itb.write_misses 0 # DTB write misses +system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.itb.read_accesses 0 # DTB read accesses +system.cpu.checker.itb.write_accesses 0 # DTB write accesses +system.cpu.checker.itb.inst_accesses 60623736 # ITB inst accesses +system.cpu.checker.itb.hits 60619265 # DTB hits +system.cpu.checker.itb.misses 4471 # DTB misses +system.cpu.checker.itb.accesses 60623736 # DTB accesses +system.cpu.checker.numCycles 77072082 # number of cpu cycles simulated +system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 51991464 # DTB read hits +system.cpu.dtb.read_misses 102104 # DTB read misses +system.cpu.dtb.write_hits 11910179 # DTB write hits +system.cpu.dtb.write_misses 24558 # DTB write misses +system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 8002 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5528 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 717 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 2750 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52093568 # DTB read accesses +system.cpu.dtb.write_accesses 11934737 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 63901643 # DTB hits +system.cpu.dtb.misses 126662 # DTB misses +system.cpu.dtb.accesses 64028305 # DTB accesses +system.cpu.itb.inst_hits 13706914 # ITB inst hits +system.cpu.itb.inst_misses 11634 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 5188 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 6661 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 13718548 # ITB inst accesses +system.cpu.itb.hits 13706914 # DTB hits +system.cpu.itb.misses 11634 # DTB misses +system.cpu.itb.accesses 13718548 # DTB accesses +system.cpu.numCycles 414369636 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 15625474 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12104785 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 954505 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11141912 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8550078 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 1319848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 195832 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33026569 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102466950 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15625474 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9869926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22757995 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6647547 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 147850 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92972764 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133718 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 218178 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 532 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13699500 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 999735 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6482 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153797054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.827732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.202835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131058833 85.22% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1482677 0.96% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2033464 1.32% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2746838 1.79% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2006274 1.30% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1249103 0.81% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2843395 1.85% 93.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 830139 0.54% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9546331 6.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 153797054 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037709 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.247284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35048577 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92898724 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20403369 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090511 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4355873 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2264859 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 184542 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119404764 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 595579 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4355873 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37137128 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36905254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49913788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19399307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6085704 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 111719644 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3150 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 969173 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3986800 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44721 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116183301 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 513866964 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 513772287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94677 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77497386 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38685914 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1179207 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1074915 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12764218 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21542479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14020388 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1893002 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2399626 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101427658 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1855104 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 125968969 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 213520 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25665704 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69757934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 355346 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153797054 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108075061 70.27% 70.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14788281 9.62% 79.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7369782 4.79% 84.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5814520 3.78% 88.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12712346 8.27% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2776756 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693530 1.10% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 431004 0.28% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 135774 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153797054 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 56704 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8414937 94.55% 95.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 428693 4.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59520968 47.25% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95881 0.08% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 42 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 37 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2281 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53674365 42.61% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12568853 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 125968969 # Type of FU issued +system.cpu.iq.rate 0.304001 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8900337 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070655 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 414950878 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128966853 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86636419 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24045 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13082 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134749943 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12833 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 592097 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 5860643 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10887 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32446 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2240776 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 34115661 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1150165 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 4355873 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28439880 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 429508 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103498796 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 345453 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21542479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14020388 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1231045 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 92628 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11369 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32446 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 597024 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332843 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 929867 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122679068 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52684410 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3289901 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 216034 # number of nop insts executed +system.cpu.iew.exec_refs 65104045 # number of memory reference insts executed +system.cpu.iew.exec_branches 11571925 # Number of branches executed +system.cpu.iew.exec_stores 12419635 # Number of stores executed +system.cpu.iew.exec_rate 0.296062 # Inst execution rate +system.cpu.iew.wb_sent 121147574 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86646811 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46911516 # num instructions producing a value +system.cpu.iew.wb_consumers 86713430 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.209105 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540995 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 59603084 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76944094 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26377882 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499758 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 817257 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149523536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514595 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.479322 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121178940 81.04% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14398423 9.63% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4065564 2.72% 93.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2131324 1.43% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1770497 1.18% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1046764 0.70% 96.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1546784 1.03% 97.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657861 0.44% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2727379 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149523536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59603084 # Number of instructions committed +system.cpu.commit.committedOps 76944094 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 27461448 # Number of memory references committed +system.cpu.commit.loads 15681836 # Number of loads committed +system.cpu.commit.membars 413071 # Number of memory barriers committed +system.cpu.commit.branches 9891470 # Number of branches committed +system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. +system.cpu.commit.int_insts 68496808 # Number of committed integer instructions. +system.cpu.commit.function_calls 995631 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2727379 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 248361579 # The number of ROB reads +system.cpu.rob.rob_writes 211126300 # The number of ROB writes +system.cpu.timesIdled 1891134 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260572582 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592120905 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59452703 # Number of Instructions Simulated +system.cpu.committedOps 76793713 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59452703 # Number of Instructions Simulated +system.cpu.cpi 6.969736 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.969736 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143477 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143477 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556236615 # number of integer regfile reads +system.cpu.int_regfile_writes 88987616 # number of integer regfile writes +system.cpu.fp_regfile_reads 8813 # number of floating regfile reads +system.cpu.fp_regfile_writes 2942 # number of floating regfile writes +system.cpu.misc_regfile_reads 134801411 # number of misc regfile reads +system.cpu.misc_regfile_writes 912350 # number of misc regfile writes +system.cpu.icache.replacements 1015901 # number of replacements +system.cpu.icache.tagsinuse 511.619298 # Cycle average of tags in use +system.cpu.icache.total_refs 12592690 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1016413 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.389344 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.619298 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999256 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999256 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12592690 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12592690 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12592690 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12592690 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12592690 # number of overall hits +system.cpu.icache.overall_hits::total 12592690 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1106667 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1106667 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1106667 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1106667 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1106667 # number of overall misses +system.cpu.icache.overall_misses::total 1106667 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16295196980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16295196980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16295196980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16295196980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16295196980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16295196980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13699357 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13699357 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13699357 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13699357 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13699357 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13699357 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080782 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.080782 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.080782 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.571149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.571149 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2918982 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7427.435115 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 58562 # number of writebacks +system.cpu.icache.writebacks::total 58562 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90216 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90216 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90216 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90216 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90216 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90216 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1016451 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1016451 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1016451 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1016451 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1016451 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1016451 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12139346482 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12139346482 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12139346482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12139346482 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12139346482 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074197 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11942.874258 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11942.874258 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 645034 # number of replacements +system.cpu.dcache.tagsinuse 511.991558 # Cycle average of tags in use +system.cpu.dcache.total_refs 22002707 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645546 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.083872 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991558 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 14161876 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14161876 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7265482 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7265482 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 286317 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 286317 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285516 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285516 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21427358 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21427358 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21427358 # number of overall hits +system.cpu.dcache.overall_hits::total 21427358 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 733645 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 733645 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2966203 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966203 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13700 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13700 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3699848 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699848 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699848 # number of overall misses +system.cpu.dcache.overall_misses::total 3699848 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11049364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11049364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110410743261 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110410743261 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223098500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223098500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 187500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121460107261 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121460107261 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121460107261 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121460107261 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14895521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14895521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10231685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 300017 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 300017 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285524 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285524 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 25127206 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 25127206 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25127206 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 25127206 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045664 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.147245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.147245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15060.913657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37222.922120 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16284.562044 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.404643 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16049941 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7647500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2833 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5665.351571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27910.583942 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 574496 # number of writebacks +system.cpu.dcache.writebacks::total 574496 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716633 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716633 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1361 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1361 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3063259 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3063259 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3063259 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3063259 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387019 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387019 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249570 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249570 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12339 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636589 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636589 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636589 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636589 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265487500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265487500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926165441 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926165441 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191652941 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14191652941 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191652941 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14191652941 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147155039500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147155039500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42275098470 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42275098470 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189430137970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189430137970 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025335 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.242895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35766.179593 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13401.288597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22293.273904 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs no_value # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307962166200 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307962166200 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 87991 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini new file mode 100644 index 000000000..e76d62054 --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -0,0 +1,607 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.cpu] +type=DerivO3CPU +children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=system.cpu.checker +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.checker] +type=O3Checker +children=dtb itb tracer +checker=Null +clock=1 +cpu_id=-1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.checker.dtb +exitOnError=false +function_trace=false +function_trace_start=0 +interrupts=Null +itb=system.cpu.checker.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu.checker.tracer +updateOnError=true +warnOnlyOnLoadError=true +workload=system.cpu.workload + +[system.cpu.checker.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.checker.dtb.walker + +[system.cpu.checker.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.checker.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.checker.itb.walker + +[system.cpu.checker.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.checker.tracer] +type=ExeTracer + +[system.cpu.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.interrupts] +type=ArmInterrupts + +[system.cpu.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=1000 +max_miss_count=0 +mshrs=10 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +system=system +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[0] + diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout new file mode 100755 index 000000000..5166f789f --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Mar 7 2012 20:12:09 +gem5 started Mar 7 2012 20:12:14 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 10389500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt new file mode 100644 index 000000000..96a493c86 --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -0,0 +1,676 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 10389500 # Number of ticks simulated +final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 3665 # Simulator instruction rate (inst/s) +host_op_rate 4572 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8277068 # Simulator tick rate (ticks/s) +host_mem_usage 225396 # Number of bytes of host memory used +host_seconds 1.26 # Real time elapsed on the host +sim_insts 4600 # Number of instructions simulated +sim_ops 5739 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 400 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) +system.cpu.checker.dtb.inst_hits 0 # ITB inst hits +system.cpu.checker.dtb.inst_misses 0 # ITB inst misses +system.cpu.checker.dtb.read_hits 0 # DTB read hits +system.cpu.checker.dtb.read_misses 0 # DTB read misses +system.cpu.checker.dtb.write_hits 0 # DTB write hits +system.cpu.checker.dtb.write_misses 0 # DTB write misses +system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 0 # DTB read accesses +system.cpu.checker.dtb.write_accesses 0 # DTB write accesses +system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dtb.hits 0 # DTB hits +system.cpu.checker.dtb.misses 0 # DTB misses +system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.itb.inst_hits 0 # ITB inst hits +system.cpu.checker.itb.inst_misses 0 # ITB inst misses +system.cpu.checker.itb.read_hits 0 # DTB read hits +system.cpu.checker.itb.read_misses 0 # DTB read misses +system.cpu.checker.itb.write_hits 0 # DTB write hits +system.cpu.checker.itb.write_misses 0 # DTB write misses +system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.itb.read_accesses 0 # DTB read accesses +system.cpu.checker.itb.write_accesses 0 # DTB write accesses +system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.itb.hits 0 # DTB hits +system.cpu.checker.itb.misses 0 # DTB misses +system.cpu.checker.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.checker.numCycles 5752 # number of cpu cycles simulated +system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.numCycles 20780 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 2550 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2634 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 9138 # Type of FU issued +system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1 # number of nop insts executed +system.cpu.iew.exec_refs 3325 # number of memory reference insts executed +system.cpu.iew.exec_branches 1404 # Number of branches executed +system.cpu.iew.exec_stores 1195 # Number of stores executed +system.cpu.iew.exec_rate 0.415544 # Inst execution rate +system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8156 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3863 # num instructions producing a value +system.cpu.iew.wb_consumers 7813 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4600 # Number of instructions committed +system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 2139 # Number of memory references committed +system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.membars 12 # Number of memory barriers committed +system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 22664 # The number of ROB reads +system.cpu.rob.rob_writes 24737 # The number of ROB writes +system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4600 # Number of Instructions Simulated +system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4600 # Number of Instructions Simulated +system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads +system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39570 # number of integer regfile reads +system.cpu.int_regfile_writes 8020 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.misc_regfile_reads 16023 # number of misc regfile reads +system.cpu.misc_regfile_writes 24 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use +system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits +system.cpu.icache.overall_hits::total 1663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.icache.overall_misses::total 365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use +system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits +system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use +system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits +system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses +system.cpu.l2cache.overall_misses::total 404 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini new file mode 100644 index 000000000..305feda00 --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -0,0 +1,188 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.cpu] +type=AtomicSimpleCPU +children=checker dtb interrupts itb tracer workload +checker=system.cpu.checker +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.checker] +type=DummyChecker +children=dtb itb tracer +checker=Null +clock=1 +cpu_id=-1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.checker.dtb +function_trace=false +function_trace_start=0 +interrupts=Null +itb=system.cpu.checker.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu.checker.tracer +workload=system.cpu.workload + +[system.cpu.checker.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.checker.dtb.walker + +[system.cpu.checker.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system + +[system.cpu.checker.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.checker.itb.walker + +[system.cpu.checker.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system + +[system.cpu.checker.tracer] +type=ExeTracer + +[system.cpu.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.slave[4] + +[system.cpu.interrupts] +type=ArmInterrupts + +[system.cpu.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.slave[3] + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[0] + diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout new file mode 100755 index 000000000..ee81f724d --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Mar 8 2012 09:03:12 +gem5 started Mar 8 2012 09:06:54 +gem5 executing on u200540-lin +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 2875500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt new file mode 100644 index 000000000..f9b36225f --- /dev/null +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -0,0 +1,135 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2875500 # Number of ticks simulated +final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 76819 # Simulator instruction rate (inst/s) +host_op_rate 95818 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47998674 # Simulator tick rate (ticks/s) +host_mem_usage 212240 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 4600 # Number of instructions simulated +sim_ops 5739 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 22944 # Number of bytes read from this memory +system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3648 # Number of bytes written to this memory +system.physmem.num_reads 5771 # Number of read requests responded to by this memory +system.physmem.num_writes 924 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.cpu.checker.dtb.inst_hits 0 # ITB inst hits +system.cpu.checker.dtb.inst_misses 0 # ITB inst misses +system.cpu.checker.dtb.read_hits 0 # DTB read hits +system.cpu.checker.dtb.read_misses 0 # DTB read misses +system.cpu.checker.dtb.write_hits 0 # DTB write hits +system.cpu.checker.dtb.write_misses 0 # DTB write misses +system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 0 # DTB read accesses +system.cpu.checker.dtb.write_accesses 0 # DTB write accesses +system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dtb.hits 0 # DTB hits +system.cpu.checker.dtb.misses 0 # DTB misses +system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.itb.inst_hits 0 # ITB inst hits +system.cpu.checker.itb.inst_misses 0 # ITB inst misses +system.cpu.checker.itb.read_hits 0 # DTB read hits +system.cpu.checker.itb.read_misses 0 # DTB read misses +system.cpu.checker.itb.write_hits 0 # DTB write hits +system.cpu.checker.itb.write_misses 0 # DTB write misses +system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.itb.read_accesses 0 # DTB read accesses +system.cpu.checker.itb.write_accesses 0 # DTB write accesses +system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.itb.hits 0 # DTB hits +system.cpu.checker.itb.misses 0 # DTB misses +system.cpu.checker.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.checker.numCycles 0 # number of cpu cycles simulated +system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.numCycles 5752 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 4600 # Number of instructions committed +system.cpu.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 185 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls +system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 25237 # number of times the integer registers were read +system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 2139 # number of memory refs +system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_store_insts 938 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/test.py b/tests/quick/se/00.hello/test.py index d765e9fc3..000181850 100644 --- a/tests/quick/se/00.hello/test.py +++ b/tests/quick/se/00.hello/test.py @@ -28,3 +28,5 @@ root.system.cpu.workload = LiveProcess(cmd = 'hello', executable = binpath('hello')) +if root.system.cpu.checker != NULL: + root.system.cpu.checker.workload = root.system.cpu.workload |