PhysicalMemory has vector of uniform ports instead of one special one.

configs/example/memtest.py:
    PhysicalMemory has vector of uniform ports instead of one special one.
    Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
    Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
    Add comment.

--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1

3 files changed, 15 insertions, 27 deletions

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 15a4f8f05..6fe244acf 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -57,7 +57,8 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
+                physmem = PhysicalMemory(),
+                membus = Bus(clock="500GHz", width=16))
 
 # l2cache & bus
 system.toL2Bus = Bus(clock="500GHz", width=16)
@@ -67,18 +68,12 @@ system.l2c.cpu_side = system.toL2Bus.port
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
 
-which_port = 0
 # add L1 caches
 for cpu in cpus:
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.port
-    if  which_port == 0:
-         system.funcmem.port = cpu.functional
-         which_port = 1
-    else:
-         system.funcmem.functional = cpu.functional
-
+    system.funcmem.port = cpu.functional
 
 # connect memory to membus
 system.physmem.port = system.membus.port
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index bf66a6947..a6e3a8480 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -22,7 +22,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.port
+functional=system.funcmem.port[0]
 test=system.cpu0.l1c.cpu_side
 
 [system.cpu0.l1c]
@@ -82,7 +82,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[1]
 test=system.cpu1.l1c.cpu_side
 
 [system.cpu1.l1c]
@@ -142,7 +142,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[2]
 test=system.cpu2.l1c.cpu_side
 
 [system.cpu2.l1c]
@@ -202,7 +202,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[3]
 test=system.cpu3.l1c.cpu_side
 
 [system.cpu3.l1c]
@@ -262,7 +262,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[4]
 test=system.cpu4.l1c.cpu_side
 
 [system.cpu4.l1c]
@@ -322,7 +322,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[5]
 test=system.cpu5.l1c.cpu_side
 
 [system.cpu5.l1c]
@@ -382,7 +382,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[6]
 test=system.cpu6.l1c.cpu_side
 
 [system.cpu6.l1c]
@@ -442,7 +442,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 trace_addr=0
-functional=system.funcmem.functional
+functional=system.funcmem.port[7]
 test=system.cpu7.l1c.cpu_side
 
 [system.cpu7.l1c]
@@ -495,8 +495,7 @@ file=
 latency=1
 range=0:134217727
 zero=false
-functional=system.cpu7.functional
-port=system.cpu0.functional
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
 
 [system.l2c]
 type=BaseCache
@@ -543,7 +542,7 @@ bus_id=0
 clock=2
 responder_set=false
 width=16
-port=system.l2c.mem_side system.physmem.port
+port=system.l2c.mem_side system.physmem.port[0]
 
 [system.physmem]
 type=PhysicalMemory
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
index fb8e47d20..661781580 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
@@ -5,15 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May 14 2007 16:35:50
-M5 started Tue May 15 12:18:46 2007
+M5 compiled May 18 2007 23:44:20
+M5 started Fri May 18 23:46:19 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
-warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional
-warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional
-warning: overwriting port funcmem.functional value cpu3.functional with cpu4.functional
-warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional
-warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional
-warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 84350509 because Maximum number of loads reached!